Search results for "array"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Fayez Gebali, A. N. M. Ehtesham Rafiq	Processor Array Architectures for Deep Packet Classification.	IEEE Trans. Parallel Distributed Syst.	2006	DBLP DOI BibTeX RDF	deep packet classification, parallel hardware, Processor array, string search
19	Yuan-Long Jeang, Ping-Shou Cheng, Jiun-Hau Tu, Kai-Jyun Liang, Ching-Ta Chen	A New EmbeddedWavelet Image Coding Based on Zero-block and Array (N-EZBA) and Its Efficient Hardware Implementation.	ICICIC (2)	2006	DBLP DOI BibTeX RDF	embedded zero- block and array (EZBA), wavelet transform (DWT)
19	Dinakar Dhurjati, Vikram S. Adve	Backwards-compatible array bounds checking for C with very low overhead.	ICSE	2006	DBLP DOI BibTeX RDF	automatic pool allocation, compilers, programming languages, array bounds checking, region management
19	Gui Liang Feng, Robert H. Deng, Feng Bao 0001, Jia-Chen Shen	New Efficient MDS Array Codes for RAID Part I: Reed-Solomon-Like Codes for Tolerating Three Disk Failures.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	MDS array codes, multiple disk failures, RAID, Reed-Solomon codes, Low-density-parity-check codes
19	Yukiko Kubo, Atsushi Takahashi 0001	A global routing method for 2-layer ball grid array packages.	ISPD	2005	DBLP DOI BibTeX RDF	2-layer routing, ball grid array, cost graph, heuristic, global routing, monotonic, greedy
19	Qiuhua Cao, John A. Stankovic	Dual face phased array radar scheduling with multiple constraints.	EMSOFT	2005	DBLP DOI BibTeX RDF	dual phased array radars systems, scheduling, performance, real time systems, resource allocations, heuristic algorithms
19	Weichung Wang, Tsung-Min Hwang	Numerical Simulation of Three-Dimensional Vertically Aligned Quantum Dot Array.	International Conference on Computational Science (3)	2005	DBLP DOI BibTeX RDF	Semiconductor quantum dot array, the Schrödinger equation, energy levels, numerical simulation, wave function
19	Cristian Coarfa, Yuri Dotsenko, John M. Mellor-Crummey, François Cantonnet, Tarek A. El-Ghazawi, Ashrujit Mohanti, Yiyi Yao, Daniel G. Chavarría-Miranda	An evaluation of global address space languages: co-array fortran and unified parallel C.	PPoPP	2005	DBLP DOI BibTeX RDF	co-array fortran, global address space languages, unified parallel C, performance, scalability, compilers, parallel languages, UPC, CAF
19	Arun Natarajan 0001, Abbas Komijani, Ali Hajimiri	A 24 GHz phased-array transmitter in 0.18µm CMOS.	DAC	2005	DBLP DOI BibTeX RDF	24GHz, phased-array, wireless, CMOS, IC, transmitters
19	Yutao Zhong 0001, Maksim Orlovich, Xipeng Shen, Chen Ding 0001	Array regrouping and structure splitting using whole-program reference affinity.	PLDI	2004	DBLP DOI BibTeX RDF	array regrouping, reference affinity, reuse signature, structure splitting, volume distance, program transformation, program locality
19	Wei Xu, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin	Design of a nanosensor array architecture.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	gas sensing, nanowire sensor array, sensor pre-processing, pattern recognition, electronic nose
19	Marina L. Gavrilova, Muhammad H. Alsuwaiyel	Computing the Euclidean Distance Transform on a Linear Array of Processors.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	linear array of processors, parallel algorithm, image processing, distance transform, Euclidean distance, feature transform
19	Matthew Moe, Herman Schmit	Floorplanning of pipelined array modules using sequence pairs.	ISPD	2003	DBLP DOI BibTeX RDF	pipelined array, floorplan, sequence pair
19	Siddika Berna Örs, Lejla Batina, Bart Preneel, Joos Vandewalle	Hardware Implementation of a Montgomery Modular Multiplier in a Systolic Array.	IPDPS	2003	DBLP DOI BibTeX RDF	Montgomery’s Multiplication Method, FPGA, RSA, ECC, Public Key Cryptography, systolic array
19	Shi-Jinn Horng, Horng-Ren Tsai, Yi Pan 0001, Jennifer Seitzer	Optimal Algorithms for the Channel-Assignment Problem on a Reconfigurable Array of Processors with Wider Bus Networks.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	minimum coloring problem, reconfigurable array of processors with wider bus networks, parallel algorithm, interval graph, list ranking, integer sorting, Channel-assignment problem
19	Peter R. Cappello, Ömer Egecioglu	Automatic Processor Lower Bound Formulas for Array Computations.	ISPAN	2002	DBLP DOI BibTeX RDF	Array computation, Diophantine system, lower bound
19	Keqin Li, Victor Y. Pan	Parallel Matrix Multiplication on a Linear Array with a Reconfigurable Pipelined Bus System.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	Bilinear algorithm, optical pipelined bus, distributed memory system, matrix multiplication, speedup, PRAM, reconfigurable system, linear array, cost-optimality
19	Yao-Wen Chang, Kai Zhu 0001, D. F. Wong 0001	Timing-driven routing for symmetrical array-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	field-programmable gate array, synthesis, layout, computer-aided design of VLSI
19	Rainer Schaffer, Renate Merker, Francky Catthoor	Combining Background Memory Management and Regular Array Co-Partitioning, Illustrated on a Full Motion Estimation Kernel.	VLSI Design	2000	DBLP DOI BibTeX RDF	low-power system design, regular array synthesis, motion estimation architecture, memory management
19	Richard Rasala	Automatic array algorithm animation in C++.	SIGCSE	1999	DBLP DOI BibTeX RDF	algorithm, animation, C++, template, array
19	Joao Paulo Kitajima, Gonzalo Navarro 0001	A Fast Distributed Suffix Array Generation Algorithm.	SPIRE/CRIWG	1999	DBLP DOI BibTeX RDF	Parallel Algorithm, Sorting, Suffix Array
19	Karl-Heinz Zimmermann, Wolfgang Achtziger	On Time Optimal Implementation of Uniform Recurrences onto Array Processors via Quadratic Programming.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF	space-time transformation, systolic array, quadratic programming, uniform recurrence equation
19	Teruhisa Hochin, Tatsuo Tsuji	A Storage Structure for Graph-Oriented Databases Using an Array of Element Types.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	Graph-oriented databases, Graph, Array, Directory, Storage structure
19	Kumar N. Ganapathy, Benjamin W. Wah, Chien-Wei Li	Designing a Scalable Processor Array for Recurrent Computations.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	Access unit, affine dependencies, area index, clock-rate reduction, multimesh graph, uniform dependencies, scheduling, partitioning, memory bandwidth, processor array, dependence graph
19	Vasily G. Moshnyaga, Keikichi Tamaru	A Memory Efficient Array Architecture for Real-Time Motion Estimation.	IPPS	1997	DBLP DOI BibTeX RDF	array architecture, real-time motion estimation, video picture, video memory distribution, HDTV picture format, motion estimation, video-coding, VLSI implementation, memory requirements
19	Michiel de Bakker, Piet W. Verbeek, Gijs K. Steenvoorden	Design Considerations for a Range Image Sensor Containing a PSD-array and An On-chip Multiplexer.	3DIM	1997	DBLP DOI BibTeX RDF	range image sensor, PSD-array, on-chip multiplexer, PSD-chip, light range imaging, analog preamplifiers, analog current multiplexer, image sensors, image sensor, low-pass filtering
19	Yi Pan 0001, Keqin Li 0001, Si-Qing Zheng	Fast nearest neighbor algorithms on a linear array with a reconfigurable pipelined bus system.	ISPAN	1997	DBLP DOI BibTeX RDF	reconfigurable pipelined bus, nearest neighbor problem, O(log log n)time, n/sup 3/ processors, O(1) time, image processing, binary image, linear array, nearest neighbor algorithms
19	Rajeev Thakur, Alok N. Choudhary, J. Ramanujam	Efficient Algorithms for Array Redistribution.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	data distribution, High Performance Fortran (HPF), runtime support, distributed-memory computers, Array redistribution
19	István Forgács	An Exact Array Reference Analysis for Data Flow Testing.	ICSE	1996	DBLP BibTeX RDF	approximate information, definition-use pairs, exact array reference analysis, formulae negation avoidance, precise method, program path execution, program testing, data flow analysis, arrays, program optimization, data flow testing, program parallelization
19	Mounir Hamdi, Yi Pan 0001	Communication-efficient algorithms on reconfigurable array of processors with spanning optical buses.	ISPAN	1996	DBLP DOI BibTeX RDF	reconfigurable array of processors, spanning optical buses, optical signal transmissions, RASOB, semi-group computations, parallel algorithms, parallel architectures, reconfiguration, reconfigurable architectures, optical interconnections, Gaussian eliminations
19	Siddhartha Chatterjee, John R. Gilbert, Robert Schreiber, Shang-Hua Teng	Optimal Evaluation of Array Expressions on Massively Parallel Machines.	ACM Trans. Program. Lang. Syst.	1995	DBLP DOI BibTeX RDF	array alignment, compact dynamic programming, distributed memory parallel processors, fixed topology Steiner tree, Fortran 90, data-parallel programming
19	Martin C. Herbordt, Charles C. Weems	An empirical study of datapath, memory hierarchy, and network in SIMD array architectures.	ICCD	1995	DBLP DOI BibTeX RDF	SIMD array architectures, SIMD arrays, ENPASSANT, router network, local transfers, performance evaluation, performance, parallel architectures, broadcast, virtual machines, memory hierarchy, reduction, associativity, memory architecture, cache storage, simulation environment, datapath, block size
19	Junya Kudoh, Toshiro Takahashi, Yukio Umada, Masaharu Kimura, Shigeru Yamamoto, Youichi Ito	A CMOS gate array with dynamic-termination GTL I/O circuits.	ICCD	1995	DBLP DOI BibTeX RDF	CMOS gate array, dynamic-termination GTL I/O circuits, triple-metal-layer process technology, push-pull output driver, dynamic termination receiver, 250 Mb/s data, stub line, terminated bus line, IDDQ testability, differential receiver, delay time overheads, 0.5 micron, 250 Mbit/s, logic testing, delays, CMOS logic circuits, logic arrays
19	H. Dhanesha, K. Falakshahi, Mark Horowitz	Array-of-arrays architecture for parallel floating point multiplication.	ARVLSI	1995	DBLP DOI BibTeX RDF	array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron
19	Puneet Sawhney, Haroon Rasheed	Static RAM generators with automated characterization techniques for a 0.5 micron triple-metal embedded array.	VLSI Design	1995	DBLP DOI BibTeX RDF	static RAM generators, automatic generator characterisation tool, triple-metal embedded array, metallized SRAMs, single-port static RAMs, dual-port static RAMs, user-defined size, 0.5 micron, application specific integrated circuits, integrated circuit design, circuit CAD, aspect ratio, ASIC design, SRAM chips, SRAM chips, module generators
19	Santanu Chattopadhyay, Samir Roy, Parimal Pal Chaudhuri	Technology mapping on a multi-output logic module built around Cellular Automata Array for a new FPGA architecture.	VLSI Design	1995	DBLP DOI BibTeX RDF	multi-output logic module, cellular automata array, design turn-around time, field programmability, rapid circuit realization, logic blocks, AND-XOR based logic, library based technology mapping technique, MCNC benchmarks, field programmable gate arrays, VLSI, cellular automata, logic CAD, testability, technology mapping, multivalued logic circuits, FPGA architecture
19	Santanu Chattopadhyay, Dipanwita Roy Chowdhury, Subarna Bhattacharjee, Parimal Pal Chaudhuri	Board level fault diagnosis using cellular automata array.	VLSI Design	1995	DBLP DOI BibTeX RDF	board level fault diagnosis, cellular automata array, output responses, encoding strategy, byte error correcting code, encoded symbols, decoding structure, VLSI, fault diagnosis, logic testing, cellular automata, error correction codes, VLSI implementation, test vectors
19	Young-Joon Kim, Seong-Whan Lee, Myung-Won Kim	Parallel hardware implementation of handwritten character recognition system on wavefront array processor architecture.	ICDAR	1995	DBLP DOI BibTeX RDF	character recognition equipment, parallel hardware, wavefront array processor, unconstrained handwritten numerals, parallel architectures, character recognition, handwriting recognition, image classification, neural nets, clock skew, handwritten character recognition, neural network classifier
19	Roberto R. Osorio, Elisardo Antelo, Javier D. Bruguera, Julio Villalba, Emilio L. Zapata	Digit On-line Large Radix CORDIC Rotator.	ASAP	1995	DBLP DOI BibTeX RDF	Digit on-line processing, Pipelined array architecture, VLSI architecture, Application-specific processor, CORDIC algorithm
19	Thomas Alexander, John L. Ellis, Gershon Kedem	A Solid Translation Engine using Ray Representation.	ASAP	1995	DBLP DOI BibTeX RDF	solid modeling, array processors, raycasting
19	Chris J. Scheiman, Peter R. Cappello	A Processor-Time-Minimal Schedule for 3D Rectilinear Mesh Algorithms.	ASAP	1995	DBLP DOI BibTeX RDF	systolic array, multiprocessor schedule
19	Yen-Chun Lin	On Balancing Sorting on a Linear Array.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	balanced parallel algorithm, balanced computation, parallel algorithms, computational complexity, sorting, linear array, local memory
19	Myung Hoon Sunwoo, J. K. Aggarwal	A Sliding Memory Plane Array Processor.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	sliding memory, plane array processor, mesh-connected, single-input multiple-data, SliM, image processing, image processing, parallel architectures
19	David R. O'Hallaron	Uniform Approach for Solving some Classical Problems on a Linear Array.	IEEE Trans. Parallel Distributed Syst.	1991	DBLP DOI BibTeX RDF	matrixtriangularization, unidirectional linear array, linearalgebra, parallel algorithms, graph theory, graph theory, matrix multiplication, linear algebra, matrix algebra, matrix transpose, algebraic path problem
18	Mahesh Balakrishnan 0001, Asim Kadav, Vijayan Prabhakaran, Dahlia Malkhi	Differential RAID: rethinking RAID for SSD reliability.	EuroSys	2010	DBLP DOI BibTeX RDF	RAID, flash, SSD
18	Peyman Nayeri, Charles J. Colbourn, Goran Konjevod	Randomized Postoptimization of Covering Arrays.	IWOCA	2009	DBLP DOI BibTeX RDF
18	Zhu Liang Yu, Wee Ser, Meng Hwa Er, Huawei Chen	Robust Adaptive Beamformer with LMI Constraints on Magnitude Response.	ICC	2008	DBLP DOI BibTeX RDF
18	Shuchin Aeron, Sandip Bose, Henri-Pierre Valero	Automatic dispersion extraction using continuous wavelet transform.	ICASSP	2008	DBLP DOI BibTeX RDF
18	Chun-Yang Chen, Palghat P. Vaidyanathan	Minimum redundancy MIMO radars.	ISCAS	2008	DBLP DOI BibTeX RDF
18	Naoki Yamaguchi, Minoru Watanabe	An Optical Reconfiguration System with Four Contexts.	VLSI Design	2008	DBLP DOI BibTeX RDF
18	I. Balmages, Boaz Rafaely	Open-Sphere Designs for Spherical Microphone Arrays.	IEEE Trans. Speech Audio Process.	2007	DBLP DOI BibTeX RDF
18	Arne Maus, Stein Gjessing	A Model for the Effect of Caching on Algorithmic Efficiency in Radix based Sorting.	ICSEA	2007	DBLP DOI BibTeX RDF	cache friendly algorithms, caches, sorting, cache models, radix
18	Jue Wang 0013, Changjun Hu, Jianjiang Li	Contention-Free Communication Scheduling for Group Communication in Data Parallelism.	OTM Conferences (2)	2007	DBLP DOI BibTeX RDF	Distributed memory multi-computers, Group communication, Parallel compiling, Data parallelism, Communication scheduling
18	Mahendra Kumar Angamuthu Ganesan, Sundeep Singh, Frank May, Jürgen Becker 0001	H.264 Decoder at HD Resolution on a Coarse Grain Dynamically Reconfigurable Architecture.	FPL	2007	DBLP DOI BibTeX RDF
18	Minoru Watanabe, Fuminori Kobayashi	Holographic memory reconfigurable VLSI.	ISCAS	2007	DBLP DOI BibTeX RDF
18	Yen-Ying Huang, Shi-Chun Tsai, Hsin-Lung Wu	On the Construction of Permutation Arrays via Mappings from Binary Vectors to Permutations.	Des. Codes Cryptogr.	2006	DBLP DOI BibTeX RDF	AMS Classification 94B05
18	Jehan-François Pâris, Thomas J. E. Schwarz, Darrell D. E. Long	Self-adaptive Disk Arrays.	SSS	2006	DBLP DOI BibTeX RDF	k-out-of-n systems, storage systems, fault-tolerant systems, repairable systems
18	Masakazu Kumakiri, Li Bei, Tatsuo Tsuji, Ken Higuchi	Flexibly Resizable Multidimensional Arrays.	ICDE Workshops	2006	DBLP DOI BibTeX RDF
18	Wen-Qing Xu, Solomon W. Golomb	Optimal 2-D interleaving with latin rectangles.	IEEE Trans. Inf. Theory	2005	DBLP DOI BibTeX RDF
18	Omid S. Jahromi, Parham Aarabi	Theory and design of multirate sensor arrays.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
18	Mary W. Hall, Saman P. Amarasinghe, Brian R. Murphy, Shih-Wei Liao, Monica S. Lam	Interprocedural parallelization analysis in SUIF.	ACM Trans. Program. Lang. Syst.	2005	DBLP DOI BibTeX RDF	parallelization, symbolic analysis, Data dependence analysis, interprocedural data-flow analysis
18	P. Zhang, Graham A. Jullien	Microneedle Arrays for Drug Delivery and Fluid Extraction.	ICMENS	2005	DBLP DOI BibTeX RDF
18	Michael L. Seltzer, Bhiksha Raj, Richard M. Stern	Likelihood-maximizing beamforming for robust hands-free speech recognition.	IEEE Trans. Speech Audio Process.	2004	DBLP DOI BibTeX RDF
18	Dong Kyue Kim, Junha Jo, Heejin Park	A Fast Algorithm for Constructing Suffix Arrays for Fixed-Size Alphabets.	WEA	2004	DBLP DOI BibTeX RDF
18	Gianni Franceschini, Roberto Grossi	No Sorting? Better Searching!	FOCS	2004	DBLP DOI BibTeX RDF
18	Chao Huang, Srivaths Ravi 0001, Anand Raghunathan, Niraj K. Jha	Synthesis of Heterogeneous Distributed Architectures for Memory-Intensive Applications.	ICCAD	2003	DBLP DOI BibTeX RDF
18	Wataru Kaneko, Akira Nomoto, Yasuo Watanabe, Shugo Nakamura, Kentaro Shimizu	Design and Implementation of a Parallel Programming Environment Based on Distributed Shared Arrays.	ISHPC	2003	DBLP DOI BibTeX RDF
18	Sri Vinayagamoorthy, Richard Hornsey	On chip Gaussian processing for high resolution CMOS image sensors.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
18	Xiaoling Sun, Bruce F. Cockburn, Duncan G. Elliott	An Efficient Functional Test for the Massively-Parallel C ?RAM Logic-Enhanced Memory Architecture.	DFT	2003	DBLP DOI BibTeX RDF
18	Myra B. Cohen, Peter B. Gibbons, Warwick B. Mugridge, Charles J. Colbourn	Constructing Test Suites for Interaction Testing.	ICSE	2003	DBLP DOI BibTeX RDF
18	Mahmut T. Kandemir	A Compiler-Based Approach for Improving Intra-Iteration Data Reuse.	DATE	2002	DBLP DOI BibTeX RDF
18	Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty	Automatic generation and compaction of March tests for memory arrays.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
18	Tatsuo Tsuji, Hidetatsu Kawahara, Teruhisa Hochin, Ken Higuchi	Sharing Extendible Arrays in a Distributed Environment.	IICS	2001	DBLP DOI BibTeX RDF
18	Dhruva R. Chakrabarti, Prithviraj Banerjee	Global optimization techniques for automatic parallelization of hybrid applications.	ICS	2001	DBLP DOI BibTeX RDF
18	Mihalis Psarakis, Antonis M. Paschalis, Nektarios Kranitis, Dimitris Gizopoulos, Yervant Zorian	Robust and Low-Cost BIST Architectures for Sequential Fault Testing in Datapath Multipliers.	VTS	2001	DBLP DOI BibTeX RDF
18	Steven J. E. Wilton	Heterogeneous technology mapping for area reduction in FPGAs withembedded memory arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
18	Tsutomu Maruyama, Tsutomu Hoshino	A C to HDL Compiler for Pipeline Processing on FPGAs.	FCCM	2000	DBLP DOI BibTeX RDF
18	Daniel Mange, Eduardo Sanchez, André Stauffer, Gianluca Tempesti, Pierre Marchal, Christian Piguet	Embryonics: a new methodology for designing field-programmable gate arrays with self-repair and self-replicating properties.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
18	Gabriel Rivera, Chau-Wen Tseng	Data Transformations for Eliminating Conflict Misses.	PLDI	1998	DBLP DOI BibTeX RDF
18	Kamran Zarrineh, Shambhu J. Upadhyaya, Sreejit Chakravarty	A new framework for generating optimal March tests for memory arrays.	ITC	1998	DBLP DOI BibTeX RDF
18	Florin Balasa, Francky Catthoor, Hugo De Man	Practical solutions for counting scalars and dependences in ATOMIUM-a memory management system for multidimensional signal processing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
18	T. Utsumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato	Multiple-Valued Programmable Logic Arrays with Universal Literals.	ISMVL	1997	DBLP DOI BibTeX RDF	universal literals, multiple-valued programmable logic, universal literal generators, operator structures, programmable logic arrays, programmable logic arrays
18	Francis H. Y. Chan, Francis K. Lam, Hon Fung Li, J. G. Liu 0001	An all adder systolic structure for fast computation of moments.	J. VLSI Signal Process.	1996	DBLP DOI BibTeX RDF
18	Paolo Ienne, Marc A. Viredaz	GENES IV: A bit-serial processing element for a multi-model neural-network accelerator.	J. VLSI Signal Process.	1995	DBLP DOI BibTeX RDF
18	Peiyi Tang	Exact Side Effects for Interprocedural Dependence Analysis.	International Conference on Supercomputing	1993	DBLP DOI BibTeX RDF
18	K. Wojtek Przytula, Viktor K. Prasanna, Wei-Ming Lin	Parallel implementation of neural networks.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
18	Evelyn Duesterwald, Rajiv Gupta 0001, Mary Lou Soffa	Register Pipelining: An Integrated Approach to Register Allocation for Scalar and Subscripted Variables.	CC	1992	DBLP DOI BibTeX RDF
18	Tyng-Ruey Chuang	Fully Persistent Arrays for Efficient Incremental Updates and Voluminous Reads.	ESOP	1992	DBLP DOI BibTeX RDF
18	Fabrizio Lombardi, Donatella Sciuto, Renato Stefanelli	An algorithm for functional reconfiguration of fixed-size arrays.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
18	Xu Jiang, Yurong Cheng, Siyi Zhang, Juan Wang, Baoquan Ma	APIE: An information extraction module designed based on the pipeline method.	Array	2024	DBLP DOI BibTeX RDF
18	Achraf El Bouazzaoui, Abdelkader Hadjoudja, Omar Mouhib, Nazha Cherkaoui	FPGA-based ML adaptive accelerator: A partial reconfiguration approach for optimized ML accelerator utilization.	Array	2024	DBLP DOI BibTeX RDF
18	Marianne Abi Kanaan, Jean-François Couchot, Christophe Guyeux, David Laiymani, Talar Atéchian, Rony Darazi	Combining a multi-feature neural network with multi-task learning for emergency calls severity prediction.	Array	2024	DBLP DOI BibTeX RDF
18	Abdillah Abdillah, Ida Widianingsih, Rd Ahmad Buchari, Heru Nurasa	Big data security & individual (psychological) resilience: A review of social media risks and lessons learned from Indonesia.	Array	2024	DBLP DOI BibTeX RDF
18	Aditya Rajbongshi, Rashiduzzaman Shakil, Bonna Akter, Munira Akter Lata, Md. Mahbubul Alam Joarder	A comprehensive analysis of feature ranking-based fish disease recognition.	Array	2024	DBLP DOI BibTeX RDF
18	Peng Zhu, Gang Wang, Jingheng He, Yueli Dong, Yu Chang	An encrypted traffic identification method based on multi-scale feature fusion.	Array	2024	DBLP DOI BibTeX RDF
18	Maneerut Chatrangsan, Chatpong Tangmanee	Robustness and user test on text-based CAPTCHA: Letter segmenting is not too easy or too hard.	Array	2024	DBLP DOI BibTeX RDF
18	Arif Mahmud, Afjal Hossan Sarower, Amir Sohel, Md Assaduzzaman, Touhid Bhuiyan	Adoption of ChatGPT by university students for academic purposes: Partial least square, artificial neural network, deep neural network and classification algorithms approach.	Array	2024	DBLP DOI BibTeX RDF
18	Stuart Gallina Ottersen, Flávio L. Pinheiro, Fernando Bação	Triplet extraction leveraging sentence transformers and dependency parsing.	Array	2024	DBLP DOI BibTeX RDF
18	Chao Tu, Ming Chen, Liwen Zhang, Long Zhao, Di Wu, Ziyang Yue	Towards efficient multi-granular anomaly detection in distributed systems.	Array	2024	DBLP DOI BibTeX RDF
18	Rasha Al Jahdali, Samuel Kortas, M. Shaikh, Lisandro Dalcín, Matteo Parsani	Evaluation of next-generation high-order compressible fluid dynamic solver on cloud computing for complex industrial flows.	Array	2023	DBLP DOI BibTeX RDF