Search results for "interconnect"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
22	Xiaodong Yang, Walter H. Ku, Chung-Kuan Cheng	RLC interconnect delay estimation via moments of amplitude and phase response.	ICCAD	1999	DBLP DOI BibTeX RDF
22	Dirk Herrmann, Rolf Ernst	Improved interconnect sharing by identity operation insertion.	ICCAD	1999	DBLP DOI BibTeX RDF
22	Jing-Rebecca Li, Jacob K. White 0001	Efficient model reduction of interconnect via approximate system gramians.	ICCAD	1999	DBLP DOI BibTeX RDF	truncated balanced realization, vector ADI, model reduction, Krylov subspace, Lyapunov equation
22	Janet Meiling Wang, Ernest S. Kuh, Qingjian Yu	The Chebyshev expansion based passive model for distributed interconnect networks.	ICCAD	1999	DBLP DOI BibTeX RDF
22	Jason Cong, Tianming Kong, David Zhigang Pan	Buffer block planning for interconnect-driven floorplanning.	ICCAD	1999	DBLP DOI BibTeX RDF
22	Mattan Kamon, Steve McCormick, Ken Sheperd	Interconnect parasitic extraction in the digital IC design methodology.	ICCAD	1999	DBLP DOI BibTeX RDF
22	Ninglong Lu, Ibrahim N. Hajj	A reduced-order scheme for coupled lumped-distributed interconnect simulation.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
22	Kevin T. Tang, Eby G. Friedman	Peak noise prediction in loosely coupled interconnect [VLSI circuits].	ISCAS (1)	1999	DBLP DOI BibTeX RDF
22	Frank M. G. Dorenberg, Huesung Kim, Arun K. Somani	The Effect of Interconnect Schemes on the Dependability of a Modular Multi-Processor System with Shared Resources.	PRDC	1999	DBLP DOI BibTeX RDF
22	Noel Menezes, Chung-Ping Chen	Spec-Based Repeater Insertion and Wire Sizing for On-chip Interconnect.	VLSI Design	1999	DBLP DOI BibTeX RDF
22	Rui Escadas Martins, Wolfgang Pyka, Rainer Sabelka, Siegfried Selberherr	High-precision interconnect analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
22	Jeff Larson	The HAL Interconnect PCI Card.	CANPC	1998	DBLP DOI BibTeX RDF
22	S. Grout, G. Ledenbach, R. G. Bushroe, P. Fisher, Donald Cottrell, David Mallis, S. DasGupta, Joseph Morrell, Amrich Chokhavtia	CHDStd - application support for reusable hierarchical interconnect timing views.	ISPD	1998	DBLP DOI BibTeX RDF
22	Charles E. Stroud, Sajitha Wijesuriya, Carter Hamilton, Miron Abramovici	Built-in self-test of FPGA interconnect.	ITC	1998	DBLP DOI BibTeX RDF
22	Yehia Massoud, Steve S. Majors, Tareq Bustami, Jacob K. White 0001	Layout Techniques for Minimizing On-Chip Interconnect Self Inductance.	DAC	1998	DBLP DOI BibTeX RDF
22	Mike Chou, Jacob K. White 0001	Efficient formulation and model-order reduction for the transient simulation of three-dimensional VLSI interconnect.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
22	Ibrahim M. Elfadel, David D. Ling	Zeros and Passivity of Arnoldi-Reduced-Order Models for Interconnect Networks.	DAC	1997	DBLP DOI BibTeX RDF
22	Keith Nabors, Tze-Ting Fang, Hung-Wen Chang, Kenneth S. Kundert	Lumped Interconnect Models Via Gaussian Quadrature.	DAC	1997	DBLP DOI BibTeX RDF
22	Weiping Shi, W. Kent Fuchs	Optimal interconnect diagnosis of wiring networks.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
22	Eli Chiprout, Michel S. Nakhla	Analysis of interconnect networks using complex frequency hopping (CFH).	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
22	Janusz A. Starzyk	Hierarchical analysis of high frequency interconnect networks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
22	Bradly J. Cooke, John L. Prince, Andreas C. Cangellaris	S-parameter analysis of multiconductor, integrated circuit interconnect systems.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
22	Neeraj Suri, Avi Mendelson, Dhiraj K. Pradhan	BDG-torus union graph-an efficient algorithmically specializedparallel interconnect.	SPDP	1991	DBLP DOI BibTeX RDF
22	Leon Stok	Interconnect optimisation during data path allocation.	EURO-DAC	1990	DBLP DOI BibTeX RDF
22	Maciej J. Ciesielski	Layer assignment for VLSI interconnect delay minimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
22	Qiang Xu 0001, Yubin Zhang, Krishnendu Chakrabarty	SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Core-based system-on-chip, test scheduling, test-access mechanism (TAM), interconnect testing
22	Martin Thuresson, Magnus Själander, Magnus Björk, Lars J. Svensson, Per Larsson-Edefors, Per Stenström	FlexCore: Utilizing Exposed Datapath Control for Efficient Computing.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Reconfigurable, Computer architecture, Interconnect, Flexible
22	Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel	A Flexible Framework for Communication Evaluation in SoC Design.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Interconnect simulator, Network on chip, Trace based simulation, Multiprocessor simulator
22	M.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong, Glenn Reinman	RF interconnects for communications on-chip.	ISPD	2008	DBLP DOI BibTeX RDF	RF-interconnect, network-on-chip, chip multiprocessors
22	Venkata Krishnan	Evaluation of an Integrated PCI Express IO Expansion and Clustering Fabric.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	IO Expansion, clustering, interconnect, sockets, PCI Express
22	Luis A. Plana, Stephen B. Furber, Steve Temple, Muhammad Mukaram Khan, Yebin Shi, Jian Wu, Shufan Yang	A GALS Infrastructure for a Massively Parallel Multiprocessor.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	massively parallel multiprocessor, Spinnaker, self-timed interconnect, GALS, neural modeling
22	Andrew Over, Bill Clarke, Peter E. Strazdins	A Comparison of Two Approaches to Parallel Simulation of Multiprocessors.	ISPASS	2007	DBLP DOI BibTeX RDF	speedup analysis, Sparc Sulima, UltraSPARC IIICu-based multiprocessor systems, careful locking, simulation time quantum, serial simulation, load-balancing, parallel simulation, parallel discrete event simulation, interconnect model, NAS parallel benchmarks
22	Antonio Robles-Gómez, Aurelio Bermúdez, Rafael Casado, Francisco J. Quiles 0001, Tor Skeie	A distributed approach to handle topological changes in advanced switching.	PM2HW2N	2007	DBLP DOI BibTeX RDF	advanced switching interconnect, performance evaluation, network management, network reconfiguration, network availability
22	Gajinder Panesar, Daniel Towner, Andrew Duller, Alan Gray, Will Robbins	Deterministic Parallel Processing.	Int. J. Parallel Program.	2006	DBLP DOI BibTeX RDF	hetrogeneous, wireless, interconnect, Deterministic
22	Xiangdong Xuan, Adit D. Singh, Abhijit Chatterjee	Lifetime Prediction and Design-for-Reliability of IC Interconnections with Electromigration Induced Degradation in the Presence of Manufacturing Defects.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	IC reliability, reliability simulation, design for reliability, interconnect, electromigration, defect modeling
22	Yuantao Peng, Xun Liu	Low-power repeater insertion with both delay and slew rate constraints.	DAC	2006	DBLP DOI BibTeX RDF	low power, interconnect, repeater insertion, slew rate
22	Yibo Wang, Yici Cai, Xianlong Hong	A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model.	VLSI Design	2005	DBLP DOI BibTeX RDF	accurate delay model, obstacle-aware routing, buffer insertion, interconnect optimization
22	Yuantao Peng, Xun Liu	Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method.	DAC	2005	DBLP DOI BibTeX RDF	low power, interconnect, repeater insertion
22	Yuantao Peng, Xun Liu	Power macromodeling of global interconnects considering practical repeater insertion.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	low power, interconnect, macromodeling, repeater insertion
22	Vikas Chandra, Herman Schmit	Simultaneous Optimization of Driving Buffer and Routing Switch Sizes in an FPGA using an Iso-Area Approach.	ISVLSI	2002	DBLP DOI BibTeX RDF	FPGA Interconnect
22	Davide Bertozzi, Luca Benini, Bruno Riccò	Parametric timing and power macromodels for high level simulation of low-swing interconnects.	ISLPED	2002	DBLP DOI BibTeX RDF	delay, interconnect, power, macromodel, low-swing
22	Amir H. Farrahi, David J. Hathaway, Maogang Wang, Majid Sarrafzadeh	Quality of EDA CAD Tools: Definitions, Metrics and Directions.	ISQED	2000	DBLP DOI BibTeX RDF	Design Quality Metrics, Integrated Design Exploration, Incremental Synthesis, Layout-Driven Synthesis' System-Level Interconnect Prediction and Planning, Tool Interoperability, Deep Submicron Designs
22	Zhiping Yu, Dan Yergeau, Robert W. Dutton, O. Sam Nakagawa, Norman Chang, Shen Lin, Weize Xie	Full Chip Thermal Simulation.	ISQED	2000	DBLP DOI BibTeX RDF	full chip, interconnect, SOI, thermal simulation
22	Mitsuo Ishii	Cluster Technologies for High Performance Computing.	ISPAN	1999	DBLP DOI BibTeX RDF	cluster, interconnect
22	Chris C. N. Chu, D. F. Wong 0001	A Polynomial Time Optimal Algorithm for Simultaneous Buffer and Wire Sizing.	DATE	1998	DBLP DOI BibTeX RDF	Simultaneous buffer and wire sizing, buffer sizing, interconnect optimization, wire sizing
22	V. Chandramouli, Karem A. Sakallah, Ayman I. Kayssi	Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity.	ARVLSI	1997	DBLP DOI BibTeX RDF	Coupled interconnects, Distributed lines, Proximity effects, Interconnect delay, Moment matching
22	Jatan C. Shah, Sachin S. Sapatnekar	Wiresizing with Buffer Placement and Sizing for Power-Delay Tradeoffs.	VLSI Design	1996	DBLP DOI BibTeX RDF	power-delay tradeoffs, dynamic programming, Interconnect, sensitivity, buffer, sizing, repeaters, drivers
22	Noel Menezes, Ross Baldick, Lawrence T. Pileggi	A sequential quadratic programming approach to concurrent gate and wire sizing.	ICCAD	1995	DBLP DOI BibTeX RDF	RC interconnect, optimization, sequential quadratic programming
22	Tong Liu 0007, Fabrizio Lombardi, José Salinas	Diagnosis of interconnects and FPICs using a structured walking-1 approach.	VTS	1995	DBLP DOI BibTeX RDF	field programmable interconnect chips, structured walking-1 approach, boundary scan architectures, one-step test generation, two-step test generation, fault diagnosis, integrated circuit testing, diagnosis, automatic testing, boundary scan testing, interconnects testing, integrated circuit interconnections
21	Scott Beamer, Chen Sun 0003, Yong-Jin Kwon, Ajay Joshi, Christopher Batten, Vladimir Stojanovic, Krste Asanovic	Re-architecting DRAM memory systems with monolithically integrated silicon photonics.	ISCA	2010	DBLP DOI BibTeX RDF	dram architecture, energy-efficiency, silicon photonics
21	Niket Agarwal, Tushar Krishna, Li-Shiuan Peh, Niraj K. Jha	GARNET: A detailed on-chip network model inside a full-system simulator.	ISPASS	2009	DBLP DOI BibTeX RDF
21	Nancy Ying Zhou, Rouwaida Kanj, Kanak Agarwal, Zhuo Li 0001, Rajiv V. Joshi, Sani R. Nassif, Weiping Shi	The impact of BEOL lithography effects on the SRAM cell performance and yield.	ISQED	2009	DBLP DOI BibTeX RDF
21	Aditya P. Karmarkar, Xiaopeng Xu, Victor Moroz, Greg Rollins, Xiao Lin	Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology.	ISQED	2009	DBLP DOI BibTeX RDF
21	Lei Li, Zheng Cao, Mingyu Chen 0001, Jianping Fan 0002	Design and Evaluation of Optical Bus in High Performance Computer.	ICYCS	2008	DBLP DOI BibTeX RDF
21	Kees Goossens, Bart Vermeulen, Remco van Steeden, Martijn T. Bennebroek	Transaction-Based Communication-Centric Debug.	NOCS	2007	DBLP DOI BibTeX RDF
21	Narender Hanchate, Nagarajan Ranganathan	Integrated Gate and Wire Sizing at Post Layout Level.	ISVLSI	2007	DBLP DOI BibTeX RDF
21	Basab Datta, Wayne P. Burleson	Low power on-chip thermal sensors based on wires.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
21	Mingjie Lin, Abbas El Gamal	A routing fabric for monolithically stacked 3D-FPGA.	FPGA	2007	DBLP DOI BibTeX RDF	3D monolithically stacked, FPGA, performance analysis, routing architecture
21	Ray Simar	The Changing Impact of Semiconductor Technology on Processor Architecture.	HPCC	2007	DBLP DOI BibTeX RDF
21	Ilya Levin, Benjamin Abramov, Vladimir Ostrovsky	Reduction of Fault Latency in Sequential Circuits by using Decomposition.	DFT	2007	DBLP DOI BibTeX RDF
21	Ahmed Youssef, Tor Myklebust, Mohab Anis, Mohamed I. Elmasry	A Low-Power Multi-Pin Maze Routing Methodology.	ISQED	2007	DBLP DOI BibTeX RDF
21	Nikil D. Dutt, Kaustav Banerjee, Luca Benini, Kanishka Lahiri, Sudeep Pasricha	Tutorial 5: SoC Communication Architectures: Technology, Current Practice, Research, and Trends.	VLSI Design	2007	DBLP DOI BibTeX RDF
21	Venkata Krishnan	Towards an integrated IO and clustering solution using PCI express.	CLUSTER	2007	DBLP DOI BibTeX RDF
21	Mehdi Baradaran Tahoori	Application-Dependent Testing of FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
21	Tudor Murgan, Oliver Mitea, Sujan Pandey, Petru Bogdan Bacinschi, Manfred Glesner	Simultaneous Placement and Buffer Planning for Reduction of Power Consumption in Interconnects and Repeaters.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
21	Taskin Koçak, Jacob Engel	Performance evaluation of wormhole routed network processor-memory interconnects.	IPDPS	2006	DBLP DOI BibTeX RDF
21	Vinita V. Deodhar, Jeffrey A. Davis	Optimization of throughput performance for low-power VLSI interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
21	Amir H. Ajami, Kaustav Banerjee, Massoud Pedram	Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
21	Rajeev Balasubramonian, Naveen Muralimanohar, Karthik Ramani, Venkatanand Venkatachalapathy	Microarchitectural Wire Management for Performance and Power in Partitioned Architectures.	HPCA	2005	DBLP DOI BibTeX RDF
21	Ajoy Kumar Palit, Lei Wu, Kishore K. Duganapalli, Walter Anheier, Jürgen Schlöffel	A New, Flexible and Very Accurate Crosstalk Fault Model to Analyze the Effects of Coupling Noise between the Interconnects on Signal Integrity Losses in Deep Submicron Chips.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF	crosstalk model, aggressor-victim, ABCD-model, crosstalk-hazards, signal integrity
21	Anand Ganti, Thomas Tarman, Jason Wertz	Supercomputing interconnects.	WSC	2005	DBLP BibTeX RDF
21	Somsubhra Mondal, Seda Ogrenci Memik	A low power FPGA routing architecture.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
21	Lacina M. Coulibaly, H. J. Kadim	Analytical crosstalk noise and its induced-delay estimation for distributed RLC interconnects under ramp excitation.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
21	Rakesh Kumar 0002, Victor V. Zyuban, Dean M. Tullsen	Interconnections in Multi-Core Architectures: Understanding Mechanisms, Overheads and Scaling.	ISCA	2005	DBLP DOI BibTeX RDF
21	Baris Guler, Ramesh Radhakrishnan, Ronald Pepper	Performance Effects of Interrupt Throttle Rate on Linux Clusters using Intel Gigabit Network Adapters.	CLUSTER	2005	DBLP DOI BibTeX RDF
21	James M. Baker Jr., Brian T. Gold, Mark Bucciero, Sidney Bennett, Rajneesh Mahajan, Priyadarshini Ramachandran, Jignesh Shah	SCMP: A Single-Chip Message-Passing Parallel Computer.	J. Supercomput.	2004	DBLP DOI BibTeX RDF	single-chip parallel computers, parallel architecture, high-performance computing, computer architecture, embedded computing
21	Dimitrios Velenis, Eby G. Friedman	Buffer Sizing for Crosstalk Induced Delay Uncertainty.	PATMOS	2004	DBLP DOI BibTeX RDF
21	Nicholas Weaver, John R. Hauser, John Wawrzynek	The SFRA: a corner-turn FPGA architecture.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA CAD, FPGA design study, FPGA optimization, FPGA architecture
21	Ruiming Chen, Hai Zhou 0001	A Flexible Data Structure for Efficient Buffer Insertion.	ICCD	2004	DBLP DOI BibTeX RDF
21	Madhubanti Mukherjee, Ranga Vemuri	Simultaneous Scheduling, Binding and Layer Assignment for Synthesis of Vertically Integrated 3D Systems.	ICCD	2004	DBLP DOI BibTeX RDF
21	Quming Zhou, Kartik Mohanram	Analysis of delay caused by bridging faults in RLC interconnects.	ITC	2004	DBLP DOI BibTeX RDF
21	Mohamed A. Elgamel, Kannan S. Tharmalingam, Magdy A. Bayoumi	Crosstalk Noise Analysis in Ultra Deep Submicrometer Technologies.	ISVLSI	2003	DBLP DOI BibTeX RDF
21	Christian Kurmann, Felix Rauch, Thomas Stricker	Cost/Performance Tradeoffs in Network Interconnects for Clusters of Commodity PCs.	IPDPS	2003	DBLP DOI BibTeX RDF	Clusters of commodity PCs, switch performance, full bisection bandwidth, Ethernet, Myrinet, all-to-all communication, application performance
21	Partha Pratim Pande, Cristian Grecu, André Ivanov, Res Saleh	Design of a switch for network on chip applications.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
21	Daniel Moritz	Using the Open Library Architecture (OLA) Open Source API in Heterogeneous Design Flows (invited).	ISQED	2002	DBLP DOI BibTeX RDF
21	Duane S. Boning, Joseph Panganiban, Karen Gonzalez-Valentin, Sani R. Nassif, Chandler McDowell, Anne E. Gattiker, Frank Liu 0001	Test structures for delay variability.	Timing Issues in the Specification and Synthesis of Digital Systems	2002	DBLP DOI BibTeX RDF
21	Yehea I. Ismail, Eby G. Friedman	Effects of inductance on the propagation delay and repeater insertion in VLSI circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
21	Dennis Sylvester, Kurt Keutzer	A global wiring paradigm for deep submicron design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
21	Jian Liang, Sriram Swaminathan, Russell Tessier	aSOC: A Scalable, Single-Chip Communications Architecture.	IEEE PACT	2000	DBLP DOI BibTeX RDF
21	Bruno Franzini, Cristiano Forzan, Davide Pandini, Primo Scandolara, Alessandro Dal Fabbro	Crosstalk Aware Static Timing Analysis: A Two Step Approach.	ISQED	2000	DBLP DOI BibTeX RDF
21	Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal	Inductance Characterization of Small Interconnects Using Test-Signal Method.	VLSI Design	2000	DBLP DOI BibTeX RDF	Test-Signal Injection Method, Differential Circuit, Short Interconnects, Self and Mutual-Inductance, High Frequency Test Signal, Displacement Current, Lumped Package Models, Inductance, Characterization, Transmission Lines, Capacitance, Substrate
21	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Figures of merit to characterize the importance of on-chip inductance.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
21	Atul Garg, Y. L. Le Coz, Hans J. Greub, R. B. Iverson, Robert F. Philhower, Pete M. Campbell, Cliff A. Maier, Sam A. Steidl, Matthew W. Ernest, Russell P. Kraft, Steven R. Carlough, J. W. Perry, Thomas W. Krawczyk Jr., John F. McDonald 0001	Accurate high-speed performance prediction for full differential current-mode logic: the effect of dielectric anisotropy.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
21	Chris C. N. Chu, Martin D. F. Wong	An efficient and optimal algorithm for simultaneous buffer and wire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
21	Li-Rong Zheng 0001, Hannu Tenhunen	Noise Margin Constraints for Interconnectivity in Deep Submicron Low Power and Mixed-Signal VLSI Circuits.	ARVLSI	1999	DBLP DOI BibTeX RDF	Mixed-Signal VLSI, Interconnection, Crosstalk, Noise Margin
21	Yehea I. Ismail, Eby G. Friedman, José Luis Neves	Figures of Merit to Characterize the Importance of On-Chip Inductance.	DAC	1998	DBLP DOI BibTeX RDF
21	Jason Cong, Patrick H. Madden	Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs.	DAC	1998	DBLP DOI BibTeX RDF	logic synthesis, gate-sizing, fanout optimization
21	Seong Yong Ohm, Fadi J. Kurdahi, Nikil D. Dutt	A unified lower bound estimation technique for high-level synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
21	C. P. Ravikumar, R. Aggarwal, C. Sharma	A Graph-Theoretic Approach for Register File Based Synthesis.	VLSI Design	1997	DBLP DOI BibTeX RDF
17	Reetuparna Das, Soumya Eachempati, Asit K. Mishra, Narayanan Vijaykrishnan, Chita R. Das	Design and evaluation of a hierarchical on-chip interconnect for next-generation CMPs.	HPCA	2009	DBLP DOI BibTeX RDF