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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 1863 occurrences of 889 keywords
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Results
Found 3357 publication records. Showing 3357 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
25 | Hao Qi, Liuyao Dai, Weicong Chen, Zhen Jia, Xiaoyi Lu |
Performance Characterization of Large Language Models on High-Speed Interconnects. |
HOTI |
2023 |
DBLP DOI BibTeX RDF |
|
25 | Chaoqi Zhang 0001, Paragkumar Thadesar, Muneeb Zia, Thomas E. Sarvey, Muhannad S. Bakir |
Au-NiW Mechanically Flexible Interconnects (MFIs) and TSV integration for 3D interconnects. |
3DIC |
2014 |
DBLP DOI BibTeX RDF |
|
25 | Hong Li, Wen-Yan Yin, Junfa Mao |
Comments on "Modeling of Metallic Carbon-Nanotube Interconnects for Circuit Simulations and a Comparison With Cu Interconnects for Sealed Technologies". |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
22 | Marshnil Vipin Dave, Rajkumar Satkuri, Mahavir Jain, Maryam Shojaei Baghini, Dinesh Kumar Sharma |
Low-power current-mode transceiver for on-chip bidirectional buses. |
ISLPED |
2010 |
DBLP DOI BibTeX RDF |
current-mode signaling, driver pre-emphasis, interconnects |
22 | Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic |
Floorplan-based FPGA interconnect power estimation in DSP circuits. |
SLIP |
2009 |
DBLP DOI BibTeX RDF |
fpga, low power, interconnects, power estimation |
22 | Suboh A. Suboh, Mohamed Bakhouya, Jaafar Gaber, Tarek A. El-Ghazawi |
An interconnection architecture for network-on-chip systems. |
Telecommun. Syst. |
2008 |
DBLP DOI BibTeX RDF |
Switching and routing, Network on chip, Network analysis, Modeling and simulation, On-chip interconnects |
22 | Suboh A. Suboh, Mohamed Bakhouya, Tarek A. El-Ghazawi |
Simulation and Evaluation of On-Chip Interconnect Architectures: 2D Mesh, Spidergon, and WK-Recursive Network. |
NOCS |
2008 |
DBLP DOI BibTeX RDF |
System on Chip, Network on Chip, Modeling and simulation, On Chip Interconnects |
22 | Shoaib Kamil 0001, Ali Pinar, Daniel K. Gunter, Michael Lijewski, Leonid Oliker, John Shalf |
Reconfigurable hybrid interconnection for static and dynamic scientific applications. |
Conf. Computing Frontiers |
2007 |
DBLP DOI BibTeX RDF |
hybrid interconnects, adaptive mesh refinement, feasibility, petascale |
22 | Syed Suhaib, Deepak Mathaikutty, David Berner, Sandeep K. Shukla |
Validating Families of Latency Insensitive Protocols. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
long interconnects, latency insensitive protocols, splitter, verification framework, Simulation, formal verification, merger, relay station |
22 | Kaustav Banerjee, Navin Srivastava |
Are carbon nanotubes the future of VLSI interconnections? |
DAC |
2006 |
DBLP DOI BibTeX RDF |
VLSI, interconnects, carbon nanotubes |
22 | Vasilis F. Pavlidis, Eby G. Friedman |
Interconnect delay minimization through interlayer via placement in 3-D ICs. |
ACM Great Lakes Symposium on VLSI |
2005 |
DBLP DOI BibTeX RDF |
RC interconnects, elmore delay, 3-D ICs |
22 | Ahmed Louri, Avinash Karanth Kodi |
An Optical Interconnection Network and a Modified Snooping Protocol for the Design of Large-Scale Symmetric Multiprocessors (SMPs). |
IEEE Trans. Parallel Distributed Syst. |
2004 |
DBLP DOI BibTeX RDF |
parallel optical interconnects, scalable optical networks, cache coherence, SMPs |
22 | Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne P. Burleson |
NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods. |
SLIP |
2004 |
DBLP DOI BibTeX RDF |
on-chip, spice-based, network-on-chip, interconnects, signaling |
22 | V. Chandramouli, Karem A. Sakallah, Ayman I. Kayssi |
Signal Delay in Coupled, Distributed RC Lines in the Presence of Temporal Proximity. |
ARVLSI |
1997 |
DBLP DOI BibTeX RDF |
Coupled interconnects, Distributed lines, Proximity effects, Interconnect delay, Moment matching |
22 | Rajesh Pendurkar, Abhijit Chatterjee, Craig A. Tovey |
Optimal single probe traversal algorithm for testing of MCM substrat. |
ICCD |
1996 |
DBLP DOI BibTeX RDF |
optimal single probe traversal algorithm, MCM substrate testing, single probe, MCM interconnects, total distance, terminal pad, interconnection net, tour construction, arbitrary insertion, shuffling techniques, total traversal cost, probe traversal time, electronics industry, semiconductor chips, traveling salesman problem, multichip modules, multichip modules |
22 | Frederik Beeftink, Arjan J. van Genderen, N. P. van der Meijs |
Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
MOS integrated circuits, bipolar integrated circuits, BiCMOS integrated circuits, layout-to-circuit extraction, high-speed MOS integrated circuits, bipolar/BiCMOS integrated circuits, device recognition, equivalent network, layout parasitics, interconnects, circuit analysis computing, circuit layout CAD, Space, Spice, device modeling |
22 | Huy Cat, Myunghee Lee, Brent Buchanan, D. Scott Wills, Martin A. Brooke, Nan M. Jokerst |
Silicon VLSI processing architectures incorporating integrated optoelectronic devices. |
ARVLSI |
1995 |
DBLP DOI BibTeX RDF |
silicon, integrated optoelectronics, integrated optoelectronic interconnects, I/O communication, inter-chip communication, silicon VLSI processing architectures, digital SIMD processors, frame processing, three dimensional stacked chips, thin film detector array, image processing, image processing, VLSI, optical interconnections, integrated circuit interconnections, Si |
22 | Prince Kohli, Mustaque Ahamad, Karsten Schwan |
Indigo: User-Level Support for Building Distributed Shared Abstractions. |
HPDC |
1995 |
DBLP DOI BibTeX RDF |
Indigo, user-level support, distributed shared abstractions, user-level library, state sharing techniques, DSM protocols, consistency actions, shared abstractions, programming environments, parallel machines, shared memory systems, distributed memory systems, shared memory machines, high performance interconnects |
22 | Hameed A. Naseem, Ajay P. Malshe, Rajan A. Beera, M. Shahid Haque, William D. Brown, Len W. Schaper |
CVD-diamond substrates for multi-chip modules (MCMs). |
VLSI Design |
1995 |
DBLP DOI BibTeX RDF |
diamond, laser beam machining, metallisation, CVD coatings, elemental semiconductors, chemical vapour deposition, CVD-diamond substrates, 3D MCM, chemical vapor deposition, diamond thin films, laser drilling, via holes, metallization, dielectric coatings, multilayer interconnects, C, planarization, multichip modules, multichip modules, fabrication, polishing, polishing, substrates |
22 | Chunming Qiao, Rami G. Melhem |
Reconfiguration with Time Division Multiplexed MIN's for Multiprocessor. |
IEEE Trans. Parallel Distributed Syst. |
1994 |
DBLP DOI BibTeX RDF |
MIN's, multiprocessor communications, TDM-MIN's, N time slots, n-dimensional hypercubes, Markov analysis, partition of connection requests, partitioning, mappings, reconfiguration, multiprocessor interconnection networks, embedding, meshes, NP-hard, multistage interconnection networks, optical interconnects, rings, binary trees, shift registers, time division multiplexing, time division multiplexed, round-robin, cube-connected-cycles |
21 | Joshua Hursey, Timothy Mattox, Andrew Lumsdaine |
Interconnect agnostic checkpoint/restart in open MPI. |
HPDC |
2009 |
DBLP DOI BibTeX RDF |
checkpoint coordination protocol, fault tolerance, MPI, shared memory, rollback-recovery, infiniband, myrinet, high speed interconnect, checkpoint/restart |
21 | Shan Tang, Qiang Xu 0001 |
In-band Cross-Trigger Event Transmission for Transaction-Based Debug. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Mohab Anis |
Advanced IC technology - opportunities and challenges. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
21 | Changbo Long, Lucanus J. Simonson, Weiping Liao, Lei He 0001 |
Microarchitecture Configurations and Floorplanning Co-Optimization. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Sunghoon Chun, YongJoon Kim, Sungho Kang 0001 |
MDSI: Signal Integrity Interconnect Fault Modeling and Testing for SoCs. |
J. Electron. Test. |
2007 |
DBLP DOI BibTeX RDF |
RLC interconnect model, fault modeling, signal integrity, interconnect test |
21 | Yuho Jin, Eun Jung Kim 0001, Ki Hwan Yum |
A Domain-Specific On-Chip Network Design for Large Scale Cache Systems. |
HPCA |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Deepak C. Sekar, Azad Naeemi, Reza Sarvari, Jeffrey A. Davis, James D. Meindl |
IntSim: A CAD tool for optimization of multilevel interconnect networks. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
21 | H. J. Kadim |
Analytical Modelling for Adaptive Multi-Purpose On-Chip Optical Interconnect. |
AHS |
2007 |
DBLP DOI BibTeX RDF |
|
21 | Dimitri Kagaris, Spyros Tragoudas, Sherin Kuriakose |
InTeRail: A Test Architecture for Core-Based SOCs. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
design for testability, cores, test access mechanism, System-on-chip test |
21 | Ethiopia Nigussie, Juha Plosila, Jouni Isoaho |
Delay-Insensitive On-Chip Communication Link using Low-Swing Simultaneous Bidirectional Signaling. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Akira Tsuchiya, Masanori Hashimoto, Hidetoshi Onodera |
Interconnect RL extraction at a single representative frequency. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Ya-Chi Yang, Cheng-Kok Koh, Venkataramanan Balakrishnan |
Adaptive admittance-based conductor meshing for interconnect analysis. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Andrew B. Kahng, Kambiz Samadi, Puneet Sharma |
Study of Floating Fill Impact on Interconnect Capacitance. |
ISQED |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Vishal Suthar, Shantanu Dutt |
Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Dennis Dalessandro, Pete Wyckoff, Gary R. Montry |
Initial Performance Evaluation of the NetEffect 10 Gigabit iWARP Adapter. |
CLUSTER |
2006 |
DBLP DOI BibTeX RDF |
|
21 | Jinwook Jang, Sheng Xu, Wayne P. Burleson |
Jitter in Deep Sub-Micron Interconnect. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Wolf-Dietrich Weber, Joe Chou, Ian Swarbrick, Drew Wingard |
A Quality-of-Service Mechanism for Interconnection Networks in System-on-Chips. |
DATE |
2005 |
DBLP DOI BibTeX RDF |
|
21 | Yan Lin 0001, Lei He 0001 |
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
programmable-Vdd, time slack, FPGA, low power |
21 | Yuanyuan Yang 0001, Jianchao Wang |
Routing Permutations on Optical Baseline Networks with Node-Disjoint Paths. |
ICPADS |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Pranav Anbalagan, Jeffrey A. Davis |
Maximum Multiplicity Distributions for Length Prediction Driven Placement. |
VLSI Design |
2004 |
DBLP DOI BibTeX RDF |
|
21 | Jason Cong, Yiping Fan, Zhiru Zhang |
Architecture-level synthesis for automatic interconnect pipelining. |
DAC |
2004 |
DBLP DOI BibTeX RDF |
interconnect pipelining, multi-cycle communication, scheduling, high-level synthesis, register binding |
21 | Junhyung Um, Taewhan Kim |
Synthesis of arithmetic circuits considering layout effects. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Pallav Gupta, Lin Zhong 0001, Niraj K. Jha |
A High-level Interconnect Power Model for Design Space Exploration. |
ICCAD |
2003 |
DBLP DOI BibTeX RDF |
|
21 | Magdy A. El-Moursy, Eby G. Friedman |
Optimum wire sizing of RLC interconnect with repeaters. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
power delay product, transient power dissipation, propagation delay, repeater insertion, wire sizing, RLC interconnect |
21 | Junhyung Um, Taewhan Kim |
Layout-aware synthesis of arithmetic circuits. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
layout, high performance, carry-save-adder |
21 | Markus Fischer |
System Area Network Extensions to the Parallel Virtual Machine. |
PVM/MPI |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Thaddeus Gabara |
Phantom Mode Signaling in VLSI Systems. |
ARVLSI |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Takeshi Saito, Ichiro Tomoda, Yoshiaki Takabatake, Keiichi Teramoto, Kensaku Fujimoto |
Gateway Technologies for Home Network and Their Implementations. |
ICDCS Workshops |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Qinwei Xu, Pinaki Mazumder, Zheng-Fan Li |
Transmission Line Modeling by Modified Method of Characteristics. |
VLSI Design |
2001 |
DBLP DOI BibTeX RDF |
|
21 | Byungwoo Choi, D. M. H. Walker |
Timing Analysis of Combinational Circuits Including Capacitive Coupling and Statistical Process Variation. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
interconnect coupling, delay fault model, process variation, timing analysis, delay fault test |
21 | Shantanu Dutt, Vimalvel Shanmugavel, Steven Trimberger |
Efficient incremental rerouting for fault reconfiguration in field programmable gate arrays. |
ICCAD |
1999 |
DBLP DOI BibTeX RDF |
FPGA defect/fault tolerance, dynamic fault reconfiguration, incremental circuit rerouting, reconfiguration time, track overhead |
21 | Kangwoo Lee, Woo-Jong Han, Michel Dubois 0001 |
Bottleneck-Free Interconnect and IO Subsystem in SPAX. |
ICPADS |
1997 |
DBLP DOI BibTeX RDF |
|
21 | Seok-Yoon Kim, Nanda Gopal, Lawrence T. Pillage |
Time-domain macromodels for VLSI interconnect analysis. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
21 | Len Dekker, Edward E. E. Frietman |
Optical link and processor clustering in the Delft parallel processor. |
ICS |
1988 |
DBLP DOI BibTeX RDF |
|
19 | Tobias Koal, Daniel Scheit, Heinrich Theodor Vierhaus |
A scheme of logic self repair including local interconnects. |
DDECS |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Tomasz Rudnicki, Tomasz Garbolino, Krzysztof Gucwa, Andrzej Hlawiczka |
Effective BIST for crosstalk faults in interconnects. |
DDECS |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Dana Vantrease, Nathan L. Binkert, Robert Schreiber, Mikko H. Lipasti |
Light speed arbitration and flow control for nanophotonic interconnects. |
MICRO |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Boris Grot, Joel Hestness, Stephen W. Keckler, Onur Mutlu |
Express Cube Topologies for on-Chip Interconnects. |
HPCA |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Abhinav Bhatele, Eric J. Bohm, Laxmikant V. Kalé |
A Case Study of Communication Optimizations on 3D Mesh Interconnects. |
Euro-Par |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Antonio Robles-Gómez, Aurelio Bermúdez, Rafael Casado |
Implementing a Change Assimilation Mechanism for Source Routing Interconnects. |
Euro-Par |
2009 |
DBLP DOI BibTeX RDF |
performance evaluation, routing protocols, dynamic reconfiguration, High-performance networks, topology discovery |
19 | Joseph B. Cessna, Thomas R. Bewley |
Honeycomb-structured computational interconnects and their scalable extension to spherical domains. |
SLIP |
2009 |
DBLP DOI BibTeX RDF |
switchless interconnect, graph theory |
19 | Marshnil Vipin Dave, Maryam Shojaei Baghini, Dinesh Kumar Sharma |
A process variation tolerant, high-speed and low-power current mode signaling scheme for on-chip interconnects. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
current mode singnaling, dynamic overdriving, process variation tolerant |
19 | K. C. Narasimhamurthy, Roy P. Paily |
Impact of Bias Voltage on Magnetic Inductance of Carbon Nanotube Interconnects. |
VLSI Design |
2009 |
DBLP DOI BibTeX RDF |
|
19 | Xiaomeng Shi, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Erping Li |
Complex Shaped On-Wafer Interconnects Modeling for CMOS RFICs. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Kaveh Shakeri, James D. Meindl |
Accelerated Modeling of Massively Coupled RLC Interconnects Using the Relative Inductance Extraction Method. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen |
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime. |
IEEE Trans. Very Large Scale Integr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Terrence S. T. Mak, Crescenzo D'Alessandro, N. Pete Sedcole, Peter Y. K. Cheung, Alexandre Yakovlev, Wayne Luk |
Implementation of Wave-Pipelined Interconnects in FPGAs. |
NOCS |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah |
Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects. |
NOCS |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Carsten Albrecht, Philipp Roß, Roman Koch, Thilo Pionteck, Erik Maehle |
Performance Analysis of Bus-Based Interconnects for a Run-Time Reconfigurable Co-Processor Platform. |
PDP |
2008 |
DBLP DOI BibTeX RDF |
Network Co-processor, SoC Interconnect, Run-Time Reconfiguration |
19 | Tomokazu Yoneda, Hideo Fujiwara |
Wrapper and TAM Co-Optimization for Reuse of SoC Functional Interconnects. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
19 | M.-C. Frank Chang, Jason Cong, Adam Kaplan, Chunyue Liu, Mishali Naik, Jagannath Premkumar, Glenn Reinman, Eran Socher, Sai-Wang Tam |
Power reduction of CMP communication networks via RF-interconnects. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Hanyu Liu, Xiaolei Chen, Yajun Ha |
An architecture and timing-driven routing algorithm for area-efficient FPGAs with time-multiplexed interconnects. |
FPL |
2008 |
DBLP DOI BibTeX RDF |
|
19 | M.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong, Glenn Reinman |
RF interconnects for communications on-chip. |
ISPD |
2008 |
DBLP DOI BibTeX RDF |
RF-interconnect, network-on-chip, chip multiprocessors |
19 | Hanyu Liu, Xiaolei Chen, Yajun Ha |
An Area-Efficient Timing-Driven Routing Algorithm for Scalable FPGAs with Time-Multiplexed Interconnects. |
FCCM |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Joonsung Bae, Joo-Young Kim 0001, Hoi-Jun Yoo |
A 0.6pJ/b 3Gb/s/ch transceiver in 0.18 µm CMOS for 10mm on-chip interconnects. |
ISCAS |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Jiangjiang Liu 0002, Nihar R. Mahapatra |
The role of interconnects in the performance scalability of multicore architectures. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Sharath Jayaprakash, Nihar R. Mahapatra |
Energy-optimal signaling and ordering of bits for area-constrained interconnects. |
SoCC |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Ying Zhang 0040, Huawei Li 0001, Xiaowei Li 0001, Yu Hu 0001 |
Codeword Selection for Crosstalk Avoidance and Error Correction on Interconnects. |
VTS |
2008 |
DBLP DOI BibTeX RDF |
Codeword Selection, Crosstalk Avoidance, Reliable Bus |
19 | Ki Jin Han, Madhavan Swaminathan, Ege Engin |
Electric field integral equation combined with cylindrical conduction mode basis functions for electrical modeling of three-dimensional interconnects. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
conduction mode basis function, electric field integral equation, proximity effect, system-in-package, skin effect, 3-D integration |
19 | Dharmendra Saraswat, Ramachandra Achar, Michel S. Nakhla |
Fast Passivity Verification and Enforcement via Reciprocal Systems for Interconnects With Large Order Macromodels. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Atul Maheshwari, Wayne P. Burleson |
Current-Sensing and Repeater Hybrid Circuit Technique for On-Chip Interconnects. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Changzhong Chen, Emad Gad, Natalie Nakhla, Ramachandra Achar |
Analysis of Frequency-Dependent Interconnects Using Integrated Congruence Transform. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
19 | K. S. Sainarayanan, Chittarsu Raghunandan, M. B. Srinivas |
Delay and Power Minimization in VLSI Interconnects with Spatio-Temporal Bus-Encoding Scheme. |
ISVLSI |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Hengliang Zhu, Xuan Zeng 0001, Wei Cai 0003, Jintao Xue, Dian Zhou |
A sparse grid based spectral stochastic collocation method for variations-aware capacitance extraction of interconnects under nanometer process technology. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Avinash Karanth Kodi, Ahmed Louri |
Power-Aware Bandwidth-Reconfigurable Optical Interconnects for High-Performance Computing (HPC) Systems. |
IPDPS |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Jae Young Hur, Todor P. Stefanov, Stephan Wong, Stamatis Vassiliadis |
Systematic Customization of On-Chip Crossbar Interconnects. |
ARC |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Natalie Nakhla, Michel S. Nakhla, Ramachandra Achar |
Sparse and passive reduction of massively coupled large multiport interconnects. |
ICCAD |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Jianxun Liu, Wen-Ben Jone |
An efficient routing method for pseudo-exhaustive built-in self-testing of high-speed interconnects. |
ICCD |
2007 |
DBLP DOI BibTeX RDF |
|
19 | José C. García 0001, Juan A. Montiel-Nelson, Saeid Nooshabadi |
Adaptive Low/High Voltage Swing CMOS Driver for On-Chip Interconnects. |
ISCAS |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Charbel J. Akl, Magdy A. Bayoumi |
Reducing Delay Uncertainty of On-Chip Interconnects by Combining Inverting and Non-Inverting Repeaters Insertion. |
ISQED |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou 0001 |
Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Wei Huang 0003, Qi Gao 0004, Jiuxing Liu, Dhabaleswar K. Panda 0001 |
High performance virtual machine migration with RDMA over modern interconnects. |
CLUSTER |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Reza Zamani, Ahmad Afsahi, Ying Qian, V. Carl Hamacher |
A feasibility analysis of power-awareness and energy minimization in modern interconnects for high-performance computing. |
CLUSTER |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Qiang Xu 0001, Yubin Zhang, Krishnendu Chakrabarty |
SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Cary Gunn |
CMOS Photonics for High-Speed Interconnects. |
IEEE Micro |
2006 |
DBLP DOI BibTeX RDF |
CMOS photonics, high-speed optical communications, Luxtera, 10-Gbps |
19 | Junmou Zhang, Eby G. Friedman |
Crosstalk modeling for coupled RLC interconnects with application to shield insertion. |
IEEE Trans. Very Large Scale Integr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Aditya Bansal, Bipul Chandra Paul, Kaushik Roy 0001 |
An Analytical Fringe Capacitance Model for Interconnects Using Conformal Mapping. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Haitham S. Hamza, Jitender S. Deogun |
Designing Scalable WDM Optical Interconnects Using Predefined Wavelength Conversion. |
Networking |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Martin Omaña 0001, José Manuel Cazeaux, Daniele Rossi 0001, Cecilia Metra |
Low-cost and highly reliable detector for transient and crosstalk faults affecting FPGA interconnects. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Taskin Koçak, Jacob Engel |
Performance evaluation of wormhole routed network processor-memory interconnects. |
IPDPS |
2006 |
DBLP DOI BibTeX RDF |
|
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