|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 1729 occurrences of 545 keywords
|
|
|
Results
Found 1860 publication records. Showing 1843 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
16 | Foster F. Dai, Charles E. Stroud, Dayu Yang, Shuying Qi |
Automatic Linearity (IP3) Test with Built-in Pattern Generator and Analyzer. |
ITC |
2004 |
DBLP DOI BibTeX RDF |
|
16 | N. Venkateswaran 0002, Krishna Bharath |
Frequency Domain Testing of General Purpose Processors at the Instruction Execution Level. |
DELTA |
2004 |
DBLP DOI BibTeX RDF |
|
16 | Yi Zhao, Sujit Dey |
Fault-coverage analysis techniques of crosstalk in chip interconnects. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Jeongjin Roh, Jacob A. Abraham |
A comprehensive signature analysis scheme for oscillation-test. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Rei-Fu Huang, Li-Ming Denq, Cheng-Wen Wu, Jin-Fu Li 0001 |
A Testability-Driven Optimizer and Wrapper Generator for Embedded Memories. |
MTDT |
2003 |
DBLP DOI BibTeX RDF |
|
16 | John Marty Emmert, Jason A. Cheatham, Badhri Jagannathan, Sandeep Umarani |
An FFT Approximation Technique Suitable for On-Chip Generation and Analysis of Sinusoidal Signals. |
DFT |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Adam B. Kinsman, Jonathan I. Hewitt, Nicola Nicolici |
Embedded Compact Deterministic Test for IP-Protected Cores. |
DFT |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Jin-Fu Li 0001, Jen-Chieh Yeh, Rei-Fu Huang, Cheng-Wen Wu, Peir-Yuan Tsai, Archer Hsu, Eugene Chow |
A Built-In Self-Repair Scheme for Semiconductor Memories with 2-D Redundancy. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
built-in redundancy-analysis, built-in self-test, memory testing, semiconductor memory, built-in self-repair |
16 | Hamidreza Hashempour, Fred J. Meyer, Fabrizio Lombardi, Farzin Karimi |
Hybrid Multisite Testing at Manufacturing. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
16 | David M. Wu, Mike Lin, Subhasish Mitra, Kee Sup Kim, Anil Sabbavarapu, Talal Jaber, Pete Johnson, Dale March, Greg Parrish |
H-DFT: A Hybrid DFT Architecture For Low-Cost High Quality Structural Testing. |
ITC |
2003 |
DBLP DOI BibTeX RDF |
|
16 | Xrysovalantis Kavousianos, Dimitris Bakalis, Dimitris Nikolos, Spyros Tragoudas |
A new built-in TPG method for circuits with random patternresistant faults. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Shu-Rong Lee, Ming-Jun Hsiao, Tsin-Yuan Chang |
An Access Timing Measurement Unit of Embedded Memory. |
Asian Test Symposium |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Emil Gizdarski, Hideo Fujiwara |
Fault Set Partition for Efficient Width Compression. |
Asian Test Symposium |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Robert Gibbins, R. Dean Adams, Thomas J. Eckenrode, Michael Ouellette, Yuejian Wu |
Design and Test of a 9-port SRAM for a 100Gb/s STS-1 Switch. |
MTDT |
2002 |
DBLP DOI BibTeX RDF |
|
16 | N. Axelos, J. Watson, D. Taylor, A. Platts |
Built-In-Self-Test of Analogue Circuits Using Optimised Fault Sets and Transient Response Testing. |
IOLTW |
2002 |
DBLP DOI BibTeX RDF |
|
16 | Sungbae Hwang, Jacob A. Abraham |
Selective-run built-in self-test using an embedded processor. |
ACM Great Lakes Symposium on VLSI |
2002 |
DBLP DOI BibTeX RDF |
processor-based testing, built-in self-test, design for testability, SOC testing, pseudo-random number generator |
16 | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou |
Integrated test of interacting controllers and datapaths. |
ACM Trans. Design Autom. Electr. Syst. |
2001 |
DBLP DOI BibTeX RDF |
built-in self-test, register transfer level, synthesis-for-testability |
16 | Tetsuji Kishi, Mitsuyasu Ohta, Takashi Taniguchi, Hiroshi Kadota |
A New Inter-Core Built-In-Self-Test Circuits for Tri-State Buffers in the System on a Chip. |
Asian Test Symposium |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Aiman H. El-Maleh, Yahya E. Osais |
A retiming-based test pattern generator design for built-in self test of data path architectures. |
ISCAS (4) |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Gaetano Palumbo, Giuseppe Introvaia, Vincenzo Mastrocola, Promod Kumar, Francesco Pipiton |
Built-In Self Test for Low Cost Testing of a 60 MHz Synchronous Flash Memory. |
IOLTW |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Kuo-Liang Cheng, Ming-Fu Tsai, Cheng-Wen Wu |
Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories. |
VTS |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Chao-Wen Tseng, Subhasish Mitra, Edward J. McCluskey, Scott Davidson 0001 |
An Evaluation of Pseudo Random Testing for Detecting Real Defects. |
VTS |
2001 |
DBLP DOI BibTeX RDF |
|
16 | Jiun-Lang Huang, Kwang-Ting Cheng |
An On-Chip Short-Time Interval Measurement Technique for Testing High-Speed Communication Links. |
VTS |
2001 |
DBLP DOI BibTeX RDF |
|
16 | A. Schubert, Walter Anheier |
On Random Pattern Testability of Cryptographic VLSI Cores. |
J. Electron. Test. |
2000 |
DBLP DOI BibTeX RDF |
testing of cores, test-ready intellectual property, built-in self-test, pseudorandom testing |
16 | Khoan Truong |
A Simple Built-In Self Test For Dual Ported SRAMs. |
MTDT |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Melvin A. Breuer |
High End and Low End Applications for Defective Chips: Enhanced Availability and Acceptability. |
VTS |
2000 |
DBLP DOI BibTeX RDF |
|
16 | Abhijit Jas, Kartik Mohanram, Nur A. Touba |
An Embedded Core DFT Scheme to Obtain Highly Compressed Test Sets. |
Asian Test Symposium |
1999 |
DBLP DOI BibTeX RDF |
Test Vector Compression, External Testing, Weighted Pseudo-Random Testing, Built-In Self-Test, Embedded Processor, System-on-a-Chip, Automatic Test Equipment, At-Speed Testing, Scan Chains, Deterministic Testing |
16 | Larry Fenstermaker, Ilyoung Kim, Jim L. Lewandowski, Jeffrey J. Nagy |
Built In Self Test for Ring Addressed FIFOs with Transparent Latches. |
MTDT |
1999 |
DBLP DOI BibTeX RDF |
Built In Self Test, Memory testing, Embedded memories |
16 | Andrzej Krasniewski |
Application-Dependent Testing of FPGA Delay Faults. |
EUROMICRO |
1999 |
DBLP DOI BibTeX RDF |
|
16 | Y. Tsiatouhas, Th. Haniotakis |
A Zero Aliasing Built-In Self Test Technique for Delay Fault Testing. |
DFT |
1999 |
DBLP DOI BibTeX RDF |
Built-In Self Test, Delay Fault Testing |
16 | Vinay Dabholkar, Sreejit Chakravarty, Irith Pomeranz, Sudhakar M. Reddy |
Techniques for minimizing power dissipation in scan and combinational circuits during test application. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Hussain Al-Asaad, John P. Hayes, Brian T. Murray |
Scalable Test Generators for High-Speed Datapath Circuits. |
J. Electron. Test. |
1998 |
DBLP DOI BibTeX RDF |
datapath circuits, scalability, built-in self-test, test generation, on-line testing, carry lookahead |
16 | Ilyoung Kim, Yervant Zorian, Goh Komoriya, Hai Pham, Frank P. Higgins, Jim L. Lewandowski |
Built in self repair for embedded high density SRAM. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Han Bin Kim, Takeshi Takahashi 0003, Dong Sam Ha |
Test session oriented built-in self-testable data path synthesis. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Charles E. Stroud, Sajitha Wijesuriya, Carter Hamilton, Miron Abramovici |
Built-in self-test of FPGA interconnect. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Makoto Sugihara, Hiroshi Date, Hiroto Yasuura |
A novel test methodology for core-based system LSIs and a testing time minimization problem. |
ITC |
1998 |
DBLP DOI BibTeX RDF |
|
16 | Debesh K. Das, Indrajit Chaudhuri, Bhargab B. Bhattacharya |
Design of an Optimal Test Pattern Generator for Built-in Self Testing of Path Delay Faults. |
VLSI Design |
1998 |
DBLP DOI BibTeX RDF |
Built-in self-test, TPG, delay faults, robust testing, two-pattern tests |
16 | Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer |
Arithmetic built-in self-test for DSP cores. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Edward K. F. Lee |
Reconfigurable data converter as a building block for mixed-signal test. |
ED&TC |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Kanad Chakraborty, Pinaki Mazumder |
A programmable boundary scan technique for board-level, parallel functional duplex march testing of word-oriented multiport static RAMs. |
ED&TC |
1997 |
DBLP DOI BibTeX RDF |
|
16 | O. A. Petlin, Stephen B. Furber |
Built-In Self-Testing of Micropipelines. |
ASYNC |
1997 |
DBLP DOI BibTeX RDF |
Built-in self-test, Design for test, Asynchronous design, Micropipelines |
16 | Heebyung Yoon, Abhijit Chatterjee, Joseph L. A. Hughes |
Optimal Design of Checksum-Based Checkers for Fault Detection in Linear Analog Circuits. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Abhijit Chatterjee, Naveena Nagi |
Design for Testability and Built-In Self-Test of Mixed-Signal Circuits: A Tutorial. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Sudipta Bhawmik, Indradeep Ghosh |
A Practical Method for Selecting Partial Scan Flip-flops for Large Circuits. |
VLSI Design |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Mehrdad Nourani, Joan Carletta, Christos A. Papachristou |
A Scheme for Integrated Controller-Datapath Fault Testing. |
DAC |
1997 |
DBLP DOI BibTeX RDF |
|
16 | Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda |
Circular Self-Test Path for FSMs. |
IEEE Des. Test Comput. |
1996 |
DBLP DOI BibTeX RDF |
|
16 | Joan Carletta, Christos A. Papachristou |
Structural constraints for circular self-test paths. |
VTS |
1995 |
DBLP DOI BibTeX RDF |
circular self-test paths, bit-level correlation, register adjacency, logic testing, built-in self test, built-in self test, integrated circuit testing, sequential circuits, automatic testing, flip-flops, test quality, register transfer level circuits |
16 | Jos van Sas, Francky Catthoor, Hugo De Man |
Cellular automata based deterministic self-test strategies for programmable data paths. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Ad J. van de Goor, Yervant Zorian |
Effective march algorithms for testing single-order addressed memories. |
J. Electron. Test. |
1994 |
DBLP DOI BibTeX RDF |
Read/Write memories, single-address order, single-order addressed memory, SRAM, memory testing, March test |
16 | Magdy S. Abadir, Ashish R. Parikh, Linda Bal, Peter Sandborn, Ken Drake |
Analyzing Multichip Module Testing Strategies. |
IEEE Des. Test Comput. |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Salvador Mir, Vladimir Kolarik, Marcelo Lubaszewski, C. Nielsen, Bernard Courtois |
Built-in self-test and fault diagnosis of fully differential analogue circuits. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Sanjay Gupta, Janusz Rajski, Jerzy Tyszer |
Test pattern generation based on arithmetic operations. |
ICCAD |
1994 |
DBLP DOI BibTeX RDF |
|
16 | Vishwani D. Agrawal, Charles R. Kime, Kewal K. Saluja |
A Tutorial on Built-In Self-Test, Part 2: Applications. |
IEEE Des. Test Comput. |
1993 |
DBLP DOI BibTeX RDF |
|
16 | Brion L. Keller, David P. Carlson, William Maloney |
The Compiled Logic Simulator. |
IEEE Des. Test Comput. |
1991 |
DBLP DOI BibTeX RDF |
|
16 | R. P. van Riessen, Hans G. Kerkhoff, A. Kloppenburg |
Designing and Implementing an Architecture with Boundary Scan. |
IEEE Des. Test Comput. |
1990 |
DBLP DOI BibTeX RDF |
|
16 | Michael Nicolaidis |
Self-exercising checkers for unified built-in self-test (UBIST). |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1989 |
DBLP DOI BibTeX RDF |
|
16 | Shambhu J. Upadhyaya, Kewal K. Saluja |
A new approach to the design of built-in self-testing PLAs for high fault coverage. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1988 |
DBLP DOI BibTeX RDF |
|
16 | Kwanghyun Kim, Dong Sam Ha, Joseph G. Tront |
On using signature registers as pseudorandom pattern generators in built-in self-testing. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
1988 |
DBLP DOI BibTeX RDF |
|
14 | Kushagra Bhatheja, Shravan K. Chaganti, Johnathan Leisinger, Emmanuel Nti Darko, Isaac Bruce, Degang Chen 0001 |
A BIST Approach to Approximate Co-Testing of Embedded Data Converters. |
IEEE Des. Test |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Ashrith S. Harith, Yingdi Liu, Nilanjan Mukherjee 0001, Jeffrey Mayer |
X-Tolerant Logic BIST for Automotive Designs using Observation Scan Technology. |
VLSID |
2024 |
DBLP DOI BibTeX RDF |
|
14 | Ahmad Menbari, Hadi Jahanirad |
A Tunable Concurrent BIST Design Based on Reconfigurable LFSR. |
J. Electron. Test. |
2023 |
DBLP DOI BibTeX RDF |
|
14 | N. Sathiabama, S. Anila |
A Universal BIST Approach for Virtex-Ultrascale Architecture. |
Comput. Syst. Sci. Eng. |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Paolo Bernardi, Gabriele Filipponi, Matteo Sonza Reorda, Davide Appello, Claudia Bertani, Vincenzo Tancorre |
Collecting diagnostic information through dichotomic search from Logic BIST of failing in-field automotive SoCs with delay faults. |
DDECS |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Pablo Cruz-Dato, Miguel Chanca-Martín, José M. de la Rosa |
Design of a 15-Bit 160-MS/s Sigma-Delta DAC for BIST Generation in Automotive RADAR Systems. |
MWSCAS |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Armen Babayan |
Validation and Test Challenges for Multi-Memory Bus BIST Engines. |
EWDTS |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Loh Wan Ying, Weng Fook Lee, Razaidi Hussin, Aiman Zakwan Jidin, Norhawati Ahmad, Nor Azura Zakaria |
Novel March WY Approach for Dynamic Fault Detection in Memory BIST. |
MCSoC |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Enrico Jimenez Tuero, Aniello Franzese, Andrea Malignaggi |
HBT Power Detector utilizing an Ultra-compact Transformer-based Coupler for 5G BIST. |
RWS |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán |
Special Session: On-chip jitter BIST with sub-picosecond resolution at GHz frequencies. |
LATS |
2023 |
DBLP DOI BibTeX RDF |
|
14 | J. Lefevre, P. Debaud, P. Girard, Arnaud Virazel |
Predictor BIST: An "All-in-One" Optical Test Solution for CMOS Image Sensors. |
ITC |
2023 |
DBLP DOI BibTeX RDF |
|
14 | Peng Chen 0022, Jun Yin 0001, Feifei Zhang, Pui-In Mak, Rui Paulo Martins, Robert Bogdan Staszewski |
Mismatch Analysis of DTCs With an Improved BIST-TDC in 28-nm CMOS. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Ahmad Menbari, Hadi Jahanirad |
A Low-cost BIST Design Supporting Offline and Online Tests. |
J. Electron. Test. |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Guillermo G. Garayar-Leyva, Hatem Osman, Johan J. Estrada-López, Oscar Moreira-Tamayo |
Skew-Circulant-Matrix-Based Harmonic-Canceling Synthesizer for BIST Applications. |
Sensors |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Sangjukta R. Chowdhury, Sumit Bhardwaj, Jennifer Kitchen |
Application Driven Rapid Synthesis for Analog BIST Components. |
MWSCAS |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Manasa Madhvaraj, Salvador Mir, Manuel J. Barragán |
A self-referenced on-chip jitter BIST with sub-picosecond resolution in 28 nm FD-SOI technology. |
VLSI-SoC |
2022 |
DBLP DOI BibTeX RDF |
|
14 | J. Lefevre, P. Debaud, Patrick Girard 0001, Arnaud Virazel |
A Generic Fast and Low Cost BIST Solution for CMOS Image Sensors. |
ETS |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Jongho Park, Sangjun Lee, Inhwan Lee, Sungwhan Park, Sungho Kang |
Correlation Aware Random Pattern Generation for Test Time and Shift Power Reduction of Logic BIST. |
ISOCC |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Gabriele Filipponi, Giusy Iaria, Matteo Sonza Reorda, Davide Appello, Giuseppe Garozzo, Vincenzo Tancorre |
In-field Data Collection System through Logic BIST for large Automotive Systems-on-Chip. |
ITC |
2022 |
DBLP DOI BibTeX RDF |
|
14 | Jaewon Park, Jae Hoon Lee, Sang-Kil Park, Ki Chul Chun, Kyomin Sohn, Sungho Kang 0001 |
An In-DRAM BIST for 16 Gb DDR4 DRAM in the 2nd 10-nm-Class DRAM Process. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Kwonhyoung Lee, Sangjun Lee, Jongho Park, Inhwan Lee, Sungho Kang 0001 |
A Low-Power BIST Scheme Using Weight-Aware Scan Grouping and Scheduling for Automotive ICs. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Tsai-Chieh Chen, Chia-Cheng Pai, Yi-Zhan Hsieh, Hsiao-Yin Tseng, Chien-Mo James Li, Tsung-Te Liu, I-Wei Chiu |
Clock-Less DFT and BIST for Dual-Rail Asynchronous Circuits. |
J. Electron. Test. |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Antonios Pavlidis, Eric Faehn, Marie-Minerve Louërat, Haralampos-G. Stratigopoulos |
BIST-Assisted Analog Fault Diagnosis. |
ETS |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Changming Cui, Junlin Huang |
A 3DIC interconnect interface test and repair scheme based on Hybrid IEEE1838 Die Wrapper Register and BIST circuit. |
ETS |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Martin Clara, Daniel Gruber, Albert Molina, Matteo Camponeschi, Yu-shan Wang, Christian Lindholm, Hundo Shin, Ramón Sanchez-Perez, Christoph Duller, Patrick Torta, Kamran Azadet |
10.7 A 64GS/s 4×-Interpolated 1b Semi-Digital FIR DAC for Wideband Calibration and BIST of RF-Sampling A/D Converters. |
ISSCC |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Maxwell Ballot, Tinus Stander |
A RF Amplifier with Oscillation-Based BIST Based on Differential Power Detection. |
ISCAS |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Mahsa Akhsham, Zainalabedin Navabi |
Integrating an Interconnect BIST with Crosstalk Avoidance Hardware. |
IOLTS |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Maher Sarraj, Haydar Bilhan, Wahed Mohammed |
Achieving Zero ADC Production Test Time with Self-calibration and BIST. |
ISQED |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Kangkang Xu, Yang Yu 0015, Xiyuan Peng |
TSV Fault Modeling and A BIST Solution for TSV Pre-bond Test. |
VTS |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Jonti Talukdar, Siyuan Chen, Amitabh Das, Sohrab Aftabjahani, Peilin Song, Krishnendu Chakrabarty |
A BIST-based Dynamic Obfuscation Scheme for Resilience against Removal and Oracle-guided Attacks*. |
ITC |
2021 |
DBLP DOI BibTeX RDF |
|
14 | Zeynep Hilal Kilimci, Ramazan Duvar |
An Efficient Word Embedding and Deep Learning Based Model to Forecast the Direction of Stock Exchange Market Using Twitter and Financial News Sites: A Case of Istanbul Stock Exchange (BIST 100). |
IEEE Access |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Chenchen Xie, Xi Li 0012, Yu Lei 0003, Houpeng Chen, Qian Wang, Jiashu Guo, Jie Miao, Yi Lv, Zhitang Song |
BIST-Based Fault Diagnosis for PCM With Enhanced Test Scheme and Fault-Free Region Finding Algorithm. |
IEEE Trans. Very Large Scale Integr. Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Takaaki Kato, Senling Wang, Yasuo Sato, Seiji Kajihara, Xiaoqing Wen |
A Flexible Scan-in Power Control Method in Logic BIST and Its Evaluation with TEG Chips. |
IEEE Trans. Emerg. Top. Comput. |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Sandeep Dhariwal, Ravi Trivedi |
Design and Analysis of Power and Area Efficient Novel Concurrent Cellular Automation Logic Block Observer BIST Structure. |
Int. J. Perform. Eng. |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Yingdi Liu, Nilanjan Mukherjee 0001, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer |
Deterministic Stellar BIST for Automotive ICs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Abhishek Koneru, Krishnendu Chakrabarty |
An Interlayer Interconnect BIST and Diagnosis Solution for Monolithic 3-D ICs. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Hung Le, Doyen Sahoo, Nancy F. Chen, Steven C. H. Hoi |
BiST: Bi-directional Spatio-Temporal Reasoning for Video-Grounded Dialogues. |
CoRR |
2020 |
DBLP BibTeX RDF |
|
14 | Afan Hasan, Oya Kalipsiz, Selim Akyokus |
Modeling Traders' Behavior with Deep Learning and Machine Learning Methods: Evidence from BIST 100 Index. |
Complex. |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Antonios Pavlidis, Marie-Minerve Louërat, Eric Faehn, Anand Kumar, Haralampos-G. D. Stratigopoulos |
Symmetry-based A/M-S BIST (SymBIST): Demonstration on a SAR ADC IP. |
DATE |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Bartosz Kaczmarek, Grzegorz Mrugalski, Nilanjan Mukherjee 0001, Janusz Rajski, Lukasz Rybak 0001, Jerzy Tyszer |
Test Sequence-Optimized BIST for Automotive Applications. |
ETS |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Arbab Alamgir, Abu Khari bin A'Ain, Norlina Paraman, Usman Ullah Sheikh, Ian Andrew Grout |
A comparative analysis of LFSR cascading for hardware efficiency and high fault coverage in BIST applications. |
ATS |
2020 |
DBLP DOI BibTeX RDF |
|
14 | Renato S. Feitoza, Manuel J. Barragán, Antonio J. Ginés, Salvador Mir |
Static linearity BIST for Vcm-based switching SAR ADCs using a reduced-code measurement technique. |
NEWCAS |
2020 |
DBLP DOI BibTeX RDF |
|
|
|