Search results for "LUT"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
10	Gang Zhou, Harald Michalik, László Hinsenkamp	Improving Throughput of AES-GCM with Pipelined Karatsuba Multipliers on FPGAs.	ARC	2009	DBLP DOI BibTeX RDF	AES-GCM, pipelined Karatsuba multiplier, FPGAs, finite field arithmetic
10	Pratik J. Shah, Jiang Hu	Impact of lithography-friendly circuit layout.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cd variation, lithography, wirelength, routing congestion
10	Grzegorz Borowik, Tadeusz Luba	Decomposing Pattern Matching Circuit.	EUROCAST	2009	DBLP DOI BibTeX RDF	FPGA, Pattern matching, Finite state machine, Decomposition, Logic synthesis, Embedded memory, Address generator
10	Kuo-Liang Chung, Jyun-Pin Wang, Ming-Shao Cheng, Yong-Huai Huang	Speedup of Color Palette Indexing in Self-Organization of Kohonen Feature Map.	CAIP	2009	DBLP DOI BibTeX RDF	Color palette indexing, lateral update interaction, SOFM, winning neuron, speedup, learning process, lookup table
10	Zhai Zhang, Youren Wang, Shanshan Yang, Rui Yao, Jiang Cui	The research of self-repairing digital circuit based on embryonic cellular array.	Neural Comput. Appl.	2008	DBLP DOI BibTeX RDF	Self-repairing digital circuit, Embryonic cellular array, Fault-tolerance design, Digital circuit design
10	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	Julien Lamoureux, Guy G. Lemieux, Steven J. E. Wilton	GlitchLess: Dynamic Power Minimization in FPGAs Through Edge Alignment and Glitch Filtering.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert	Architectural Modifications to Enhance the Floating-Point Performance of FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	Heng-Yao Lin, Ying-Hong Lu, Bin-Da Liu, Jar-Ferr Yang	A Highly Efficient VLSI Architecture for H.264/AVC CAVLC Decoder.	IEEE Trans. Multim.	2008	DBLP DOI BibTeX RDF
10	Pramod Kumar Meher, Shrutisagar Chandrasekaran, Abbes Amira	FPGA Realization of FIR Filters by Efficient and Flexible Systolization Using Distributed Arithmetic.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
10	Kees Goossens, Martijn T. Bennebroek, Jae Young Hur, Muhammad Aqeel Wahlah	Hardwired Networks on Chip in FPGAs to Unify Functional and Con?guration Interconnects.	NOCS	2008	DBLP DOI BibTeX RDF
10	Shiann Shiun Jeng, Hsing-Chen Lin, Chen-Yu Wu	DDFS design using the equi-section division method for SDR transceiver.	PIMRC	2008	DBLP DOI BibTeX RDF
10	Ian Kuon, Jonathan Rose	Area and delay trade-offs in the circuit and architecture design of FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, FPGA, architecture
10	Hadi Parandeh-Afshar, Philip Brisk, Paolo Ienne	Improving Synthesis of Compressor Trees on FPGAs via Integer Linear Programming.	DATE	2008	DBLP DOI BibTeX RDF
10	Petr Mikusek, Vaclav Dvorak	On Lookup Table Cascade-Based Realizations of Arbiters.	DSD	2008	DBLP DOI BibTeX RDF
10	Tsutomu Sasao, Yukihiro Iguchi	On the Complexity of Error Detection Functions for Redundant Residue Number Systems.	DSD	2008	DBLP DOI BibTeX RDF
10	Scott Miller, Ambrose Chu, Mihai Sima, Michael McGuire	VLSI Implementation of a Cryptography-Oriented Reconfigurable Array.	DSD	2008	DBLP DOI BibTeX RDF
10	Yang Sun 0001, Joseph R. Cavallaro	Unified decoder architecture for LDPC/turbo codes.	SiPS	2008	DBLP DOI BibTeX RDF
10	Sylvain Guilley, Laurent Sauvage, Jean-Luc Danger, Philippe Hoogvorst	Area optimization of cryptographic co-processors implemented in dual-rail with precharge positive logic.	FPL	2008	DBLP DOI BibTeX RDF
10	Gang Zhou, Li Li 0027, Harald Michalik	Area optimization of bit parallel finite field multipliers with fast carry logic on FPGAS.	FPL	2008	DBLP DOI BibTeX RDF
10	Chiu-Wah Ng, Ngai Wong, Hayden Kwok-Hay So, Tung-Sang Ng	Direct sigma-delta modulated signal processing in FPGA.	FPL	2008	DBLP DOI BibTeX RDF
10	Hosung (Leo) Kim, John Lillis	A framework for layout-level logic restructuring.	ISPD	2008	DBLP DOI BibTeX RDF	logic resynthesis, timing optimization
10	Günter Knittel	Pipelined Bus-Invert Coding for FPGAs Driving High-Speed DDR-Channels.	ITNG	2008	DBLP DOI BibTeX RDF	Bus-Invert Coding, Dual-Data-Rate, FPGA
10	Inès Bousnina, Alex Stephenne, Sofiène Affes, Abdelaziz Samet	Performance of a New Low-Complexity Angular Spread Estimator in the Presence of Line-of-Sight.	WCNC	2008	DBLP DOI BibTeX RDF
10	Yu Hu 0002, Zhe Feng 0002, Lei He 0001, Rupak Majumdar	Robust FPGA resynthesis based on fault-tolerant Boolean matching.	ICCAD	2008	DBLP DOI BibTeX RDF
10	Ioannis Kouretas, Charalambos Basetas, Vassilis Paliouras	Low-power logarithmic number system addition/subtraction and their impact on digital filters.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli	ADAPTO: full-adder based reconfigurable architecture for bit level operations.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Roberto Muscedere, Karl Leboeuf	A dynamic address decode circuit for implementing range addressable look-up tables.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Bin Du, Zhou Shi-Sheng, Li Ni	Applications of Tetrahedral Interpolation in Color Conversion Model.	CSSE (4)	2008	DBLP DOI BibTeX RDF
10	Yi-Hua E. Yang, Weirong Jiang, Viktor K. Prasanna	Compact architecture for high-throughput regular expression matching on FPGA.	ANCS	2008	DBLP DOI BibTeX RDF	BRAM, FPGA, intrusion detection, finite state machine, regular expression, NFA
10	Jason Meyer, Fatih Kocan	Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
10	Máire McLoone, Ciaran McIvor	High-speed & Low Area Hardware Architectures of the Whirlpool Hash Function.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	hash function implementation, cryptography, whirlpool
10	Marco Bucci, Luca Giancane, Raimondo Luzzi, Alessandro Trifiletti	A Dynamic and Differential CMOS Lookup Table with Data-Independent Power Consumption for Cryptographic Applications on Chip Cards.	IEEE Trans. Dependable Secur. Comput.	2007	DBLP DOI BibTeX RDF	differential logic, dual rail logic, chip-cards, cryptography, differential power analysis, DPA, power analysis
10	Irwin O. Kennedy	Implementation of Low Frequency Finite State Machines Using the VIRTEX SRL16 Primitive.	FPL	2007	DBLP DOI BibTeX RDF
10	Jixiang Zhu, Yuanxiang Li 0001, Guoliang He, Xuewen Xia	An Intrinsic Evolvable Hardware Based on Multiplexer Module Array.	ICES	2007	DBLP DOI BibTeX RDF	intrinsic, FPGA, digital, multiplexer
10	Yuan Zhang, Youren Wang, Shanshan Yang, Min Xie	Design of a Cell in Embryonic Systems with Improved Efficiency and Fault-Tolerance.	ICES	2007	DBLP DOI BibTeX RDF	Embryonic systems, Two-level self-repair, Extended hamming code, Fault tolerance of configuration memory, Cellular arrays
10	Yu Hu 0002, Satyaki Das, Steven Trimberger, Lei He 0001	Design, synthesis and evaluation of heterogeneous FPGA with mixed LUTs and macro-gates.	ICCAD	2007	DBLP DOI BibTeX RDF
10	Jing-Ming Guo, Jen-Ho Chen	Watermarking in Halftone Images with Kernels-Alternated Error Diffusion and Haar Wavelet Transform.	ICME	2007	DBLP DOI BibTeX RDF
10	Yukihiro Iguchi, Tsutomu Sasao, Munehiro Matsuura	On Designs of Radix Converters Using Arithmetic Decompositions--Binary to Decimal Converters--.	ISMVL	2007	DBLP DOI BibTeX RDF
10	Sayed Hafizur Rahman, Asif Iqbal Ahmed, Otmane Aït Mohamed	Analysis and Performance Evaluation of a Digital Carrier Synchronizer for Modem Applications.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Sai Mohan Kilambi, Behrouz Nowrouzian	A Diversity Controlled Genetic Algorithm for Optimization of FRM Digital Filters over DBNS Multiplier Coefficient Space.	ISCAS	2007	DBLP DOI BibTeX RDF
10	Abdulah Abdulah Zadeh	High Speed Modular Divider Based on GCD Algorithm.	ICICS	2007	DBLP DOI BibTeX RDF	GCD algorithm, Radix four, Finite Field, ECC
10	Andy Yan, Steven J. E. Wilton	Product-Term-Based Synthesizable Embedded Programmable Logic Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
10	Soheil Ghiasi, Elaheh Bozorgzadeh, Po-Kuan Huang, Roozbeh Jafari, Majid Sarrafzadeh	A Unified Theory of Timing Budget Management.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
10	Rohit Kumar 0001, Ying-Jui Chen, Soontorn Oraintara, Kevin Amaratunga	Lapped unimodular transforms: lifting factorization and structural regularity.	IEEE Trans. Signal Process.	2006	DBLP DOI BibTeX RDF
10	Mohammad Tehranipoor, Reza M. Rad	Fine-grained island style architecture for molecular electronic devices.	FPGA	2006	DBLP DOI BibTeX RDF
10	Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali	Testing embedded RAM modules in SRAM-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
10	Jianhua Liu, Michael Chang, Chung-Kuan Cheng	An iterative division algorithm for FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, low power, high performance, division
10	Ren Huang, Soo-Ik Chae	Implementation of an OpenVG Rasterizer with Configurable Anti-Aliasing and Multi-Window Scissoring.	CIT	2006	DBLP DOI BibTeX RDF
10	Shin Hasegawa, Hui Wang 0054, Daming Wei	An Efficient Algorithm for Real-time Catheter Tip Detection in a Virtual Reality of Electrophysiology Study.	CIT	2006	DBLP DOI BibTeX RDF
10	Shinobu Nagayama, Tsutomu Sasao, Jon T. Butler	Programmable numerical function generators based on quadratic approximation: architecture and synthesis method.	ASP-DAC	2006	DBLP DOI BibTeX RDF
10	Evangelia Kassapaki, Pavlos M. Mattheakis, Christos P. Sotiriou	Actual-Delay Circuits on FPGA: Trading-Off Luts for Speed.	FPL	2006	DBLP DOI BibTeX RDF
10	Kazutoshi Kobayashi, Manabu Kotani, Kazuya Katsuki, Y. Takatsukasa, K. Ogata, Yuuri Sugihara, Hidetoshi Onodera	A Yield and Speed Enhancement Technique Using Reconfigurable Devices Against Within-Die Variations on the Nanometer Regime.	FPL	2006	DBLP DOI BibTeX RDF
10	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design.	FPL	2006	DBLP DOI BibTeX RDF
10	Somsubhra Mondal, Seda Ogrenci Memik	Power Optimization Techniques for SRAM-Based FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
10	Leandro Möller, Rafael Soares, Ewerson Carvalho, Ismael Grehs, Ney Calazans, Fernando Moraes 0001	Infrastructure for dynamic reconfigurable systems: choices and trade-offs.	SBCCI	2006	DBLP DOI BibTeX RDF	reconfigurable architectures, NoCs, configuration controllers
10	Alastair M. Smith, George A. Constantinides, Peter Y. K. Cheung	A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design.	FCCM	2006	DBLP DOI BibTeX RDF
10	Zhe-Ming Lu, Hao Luo 0001, Jeng-Shyang Pan 0001	Reversible Watermarking for Error Diffused Halftone Images Using Statistical Features.	IWDW	2006	DBLP DOI BibTeX RDF	statistical features, reversible watermarking, halftone image
10	P. Kenterlis, Nektarios Kranitis, Antonis M. Paschalis, Dimitris Gizopoulos, Mihalis Psarakis	A Low-Cost SEU Fault Emulation Platform for SRAM-Based FPGAs.	IOLTS	2006	DBLP DOI BibTeX RDF
10	Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001	An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs.	VLSI Design	2006	DBLP DOI BibTeX RDF
10	Palkesh Jain, D. Vinay Kumar, J. M. Vasi, Mahesh B. Patil	Evaluation of Non-Quasi-Static Effects during SEU in Deep-Submicron MOS Devices and Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
10	Zhanfeng Zhao, Zhiquan Zhou, Haiyan Yu, Xiaolin Qiao	New Methods for QDDFS with Millions' Compression Ratio.	APCCAS	2006	DBLP DOI BibTeX RDF
10	Gaoqi He, Zhigeng Pan, Christophe Quarre, Mingmin Zhang, Huijun Xu	Multi-stroke Freehand Text Entry Method Using OpenVG and Its Application on Mobile Devices.	Edutainment	2006	DBLP DOI BibTeX RDF	Multi-stroke, hardware accelerated APIs, segmentation, recognition, text entry, OpenVG
10	Anh Dinh, Xiao Hu	A hardware-efficient technique to implement a trellis code modulation decoder.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
10	Carlos Álvarez 0001, Jesús Corbal, Mateo Valero	Fuzzy Memoization for Floating-Point Multimedia Applications.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Low-power design, real-time and embedded systems, special-purpose and application-based systems
10	Shrutisagar Chandrasekaran, Abbes Amira	An area efficient low power inner product computation for discrete orthogonal transforms.	ICIP (3)	2005	DBLP DOI BibTeX RDF
10	Li Zhang, Haizhou Ai, Shengjun Xin, Chang Huang, Shuichiro Tsukiji, Shihong Lao	Robust face alignment based on local texture classifiers.	ICIP (2)	2005	DBLP DOI BibTeX RDF
10	Hyun Wook Ok, Seong-Deok Lee, Wonhee Choe, Du-Sik Park, Chang-Yeong Kim	Color processing for multi-primary display devices.	ICIP (3)	2005	DBLP DOI BibTeX RDF
10	Siobhán Launders, Colin Doyle, Wesley Cooper	Switching-Activity Directed Clustering Algorithm for Low Net-Power Implementation of FPGAs.	PATMOS	2005	DBLP DOI BibTeX RDF
10	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs.	IPDPS	2005	DBLP DOI BibTeX RDF
10	Andres Upegui, Eduardo Sanchez	Evolving Hardware by Dynamically Reconfiguring Xilinx FPGAs.	ICES	2005	DBLP DOI BibTeX RDF
10	Jing-Ming Guo	Robust Watermarking with Kernels-Alternated Error Diffusion and Weighted Lookup Table in Halftone Images.	ISM	2005	DBLP DOI BibTeX RDF
10	Chris Sullivan, Alex Wilson, Stephen P. G. Chappell	Deterministic Hardware Synthesis for Compiling High-Level Descriptions to Heterogeneous Reconfigurable Architectures.	HICSS	2005	DBLP DOI BibTeX RDF
10	Gian Carlo Cardarilli, Salvatore Pontarelli, Marco Re, Adelio Salsano	FPGA oriented design of parity sharing RS codecs.	DFT	2005	DBLP DOI BibTeX RDF
10	Tsutomu Sasao, Munehiro Matsuura	BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition.	DAC	2005	DBLP DOI BibTeX RDF	code converter, BDD, cascade, characteristic function, incompletely specified function
10	Chang Huang, Bo Wu 0001, Haizhou Ai, Shihong Lao	Omni-directional face detection based on real adaboost.	ICIP	2004	DBLP DOI BibTeX RDF
10	A. Manoj Kumar, B. Jayaram 0002, V. Kamakoti 0001	SHAPER: synthesis for hybrid FPGA architectures containing PLA elements using reconvergence analysis.	FPGA	2004	DBLP DOI BibTeX RDF
10	André DeHon, Michael J. Wilson	Nanowire-based sublithographic programmable logic arrays.	FPGA	2004	DBLP DOI BibTeX RDF	sublithographic architecture, programmable logic arrays, nanowires
10	A. Manoj Kumar, Jayaram Bobba, V. Kamakoti 0001	MemMap: Technology Mapping Algorithm for Area Reduction in FPGAs with Embedded Memory Arrays Using Reconvergence Analysis.	DATE	2004	DBLP DOI BibTeX RDF
10	Wonpil Yu, YunKoo Chung, Jung Soh	Vignetting Distortion Correction Method for High Quality Digital Imaging.	ICPR (3)	2004	DBLP DOI BibTeX RDF
10	Chang Huang, Haizhou Ai, Bo Wu 0001, Shihong Lao	Boosting Nested Cascade Detector for Multi-View Face Detection.	ICPR (2)	2004	DBLP DOI BibTeX RDF
10	R. Manimegalai, A. Manoj Kumar, B. Jayaram 0002, V. Kamakoti 0001	MemMap-pd: Performance Driven Technology Mapping Algorithm for FPGAs with Embedded Memory Blocks.	FPL	2004	DBLP DOI BibTeX RDF
10	Marcos Martínez Peiró, Francisco José Ballester-Merelo, Guillermo Payá Vayá, Ricardo José Colom-Palero, Rafael Gadea Gironés, J. Belenguer	FPGA Custom DSP for ECG Signal Analysis and Compression.	FPL	2004	DBLP DOI BibTeX RDF
10	Michael D. Hutton, Jay Schleicher, David M. Lewis, Bruce Pedersen, Richard Yuan, Sinan Kaptanoglu, Gregg Baeckler, Boris Ratchev, Ketan Padalia, Mark Bourgeault, Andy Lee, Henry Kim, Rahul Saini	Improving FPGA Performance and Area Using an Adaptive Logic Module.	FPL	2004	DBLP DOI BibTeX RDF
10	Rajarshi Mukherjee, Seda Ogrenci Memik	Power-Driven Design Partitioning.	FPL	2004	DBLP DOI BibTeX RDF
10	Rajarshi Mukherjee, Seda Ogrenci Memik	Power Management for FPGAs: Power-Driven Design Partitioning.	FCCM	2004	DBLP DOI BibTeX RDF
10	Bo Wu 0001, Haizhou Ai, Chang Huang, Shihong Lao	Fast Rotation Invariant Multi-View Face Detection Based on Real Adaboost.	FGR	2004	DBLP DOI BibTeX RDF
10	Tsutomu Sasao, Munehiro Matsuura	A method to decompose multiple-output logic functions.	DAC	2004	DBLP DOI BibTeX RDF	FPGA, BDD, cascade, characteristic function
10	Javier Ramírez 0001, Uwe Meyer-Bäse, Fred J. Taylor, Antonio García 0001, Antonio Lloris-Ruíz	Design and Implementation of High-Performance RNS Wavelet Processors Using Custom IC Technologies.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	RNS arithmetic, custom integrated circuit, field-programmable logic devices, discrete wavelet transform
10	Javier Ramírez 0001, Antonio García 0001, Uwe Meyer-Bäse, Fred J. Taylor, Antonio Lloris-Ruíz	Implementation of RNS-Based Distributed Arithmetic Discrete Wavelet Transform Architectures Using Field-Programmable Logic.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	field-programmable logic, digital signal processing, discrete wavelet transform, residue number system, distributed arithmetic
10	Michael G. Wrighton, André DeHon	Hardware-assisted simulated annealing with application for fast FPGA placement.	FPGA	2003	DBLP DOI BibTeX RDF	field-programmable gate arrays, simulated annealing, placement, reconfigurable computing, design automation
10	Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose	Automatic transistor and physical design of FPGA tiles from an architectural specification.	FPGA	2003	DBLP DOI BibTeX RDF	FPGA, programmable logic, PLD, automatic layout
10	Randy Huang, John Wawrzynek, André DeHon	Stochastic, spatial routing for hypergraphs, trees, and meshes.	FPGA	2003	DBLP DOI BibTeX RDF	spatial routing, FPGA, reconfigurable computing, detail routing
10	Om Prakash Gangwal, Johan G. W. M. Janssen, Selliah Rathnam, Erwin B. Bellers, Marc Duranton	Understanding Video Pixel Processing Applications for Flexible Implementations.	DSD	2003	DBLP DOI BibTeX RDF
10	Ehsan Atoofian, Zainalabedin Navabi	A BIST Architecture for FPGA Look-Up Table Testing Reduces Reconfigurations.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
10	J. Soares Augusto, Carlos Beltrán Almeida, H. C. Campos Neto	A Modular Reconfigurable Architecture for Efficient Fault Simulation in Digital Circuits.	FPL	2003	DBLP DOI BibTeX RDF
10	Chetan Patel, Anthony Cozzie, Herman Schmit, Lawrence T. Pileggi	An architectural exploration of via patterned gate arrays.	ISPD	2003	DBLP DOI BibTeX RDF	VPGA, lookup table, interconnect architectures, gate array
10	Seok-Bum Ko, Jien-Chung Lo	A Novel Technology Mapping Method for AND/XOR Expressions.	ISMVL	2003	DBLP DOI BibTeX RDF
10	Siew Kei Lam, Devendra K. Chaudhaiy, Thambipillai Srikanthan	Low cost logarithmic techniques for high-precision computations.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
10	Michael A. Soderstrand	CSD multipliers for FPGA DSP applications.	ISCAS (5)	2003	DBLP DOI BibTeX RDF