Search results for "SRAM"

Hits ?▲	Authors	Title	Venue	Year	Link
11	Mukku Pavan Kumar, Rohit Lorenzo	A Soft Error Upset Recovery SRAM Cell for Aerospace and Military Applications.	TENCON	2023	DBLP DOI BibTeX RDF
11	Shunqin Cai, Liukai Xu, Dengfeng Wang, Zhi Li, Liang Chang, Yanan Sun 0003	High Energy-Efficient Approximate In-SRAM Computing with Bit-Wise Compressor Configuration and Data-Aware Weight Remapping Method for Neural Network Acceleration.	ICTA	2023	DBLP DOI BibTeX RDF
11	Vo Minh Huan	Dual Power Gating 8-Transistor SRAM Design For Low Power Applications.	ICSSE	2023	DBLP DOI BibTeX RDF
11	Jonghyun Oh, Chuan-Tung Lin, Mingoo Seok	D6CIM: 60.4-TOPS/W, 1.46-TOPS/mm2, 1005-Kb/mm2 Digital 6T-SRAM-Based Compute-in-Memory Macro Supporting 1-to-8b Fixed-Point Arithmetic in 28-nm CMOS.	ESSCIRC	2023	DBLP DOI BibTeX RDF
11	Weijie Jiang, Pouya Houshmand, Marian Verhelst, Wim Dehaene	A 16nm 128kB high-density fully digital In Memory Compute macro with reverse SRAM pre-charge achieving 0.36TOPs/mm2, 256kB/mm2 and 23. 8TOPs/W.	ESSCIRC	2023	DBLP DOI BibTeX RDF
11	Rob A. Damsteegt, Ramon W. J. Overwater, Masoud Babaie, Fabio Sebastiano	A Benchmark of Cryo-CMOS 40-nm Embedded SRAM/DRAMs for Quantum Computing.	ESSCIRC	2023	DBLP DOI BibTeX RDF
11	Dewei Wang, Jonghyun Oh, Gregory K. Chen, Phil C. Knag, Ram K. Krishnamurthy, Mingoo Seok	microASR: 32-μW Real-Time Automatic Speech Recognition Chip featuring a Bio-Inspired Neuron Model and Digital SRAM-based Compute-In-Memory Hardware.	ESSCIRC	2023	DBLP DOI BibTeX RDF
11	Qibang Zang, Wang Ling Goh, Yi Sheng Chong, Anh Tuan Do	4b/4b/8b Precision Charge-Domain 8T-SRAM Based CiM for CNN Processing.	AICAS	2023	DBLP DOI BibTeX RDF
11	Runxi Wang, Xinfei Guo	A Hierarchically Reconfigurable SRAM-Based Compute-in-Memory Macro for Edge Computing.	AICAS	2023	DBLP DOI BibTeX RDF
11	Anjunyi Fan, Bo Hu, Zhonghua Jin, Haiyue Han, Yaojun Zhang, Yue Yang, Yuchao Yang, Bonan Yan, Ru Huang	Live Demonstration: SRAM Compute-In-Memory Based Visual & Aural Recognition System.	AICAS	2023	DBLP DOI BibTeX RDF
11	Thanh-Dat Nguyen, Minh-Son Le, Thi-Nhan Pham, Ik-Joon Chang	TRIO: a Novel 10T Ternary SRAM Cell for Area-Efficient In-memory Computing of Ternary Neural Networks.	AICAS	2023	DBLP DOI BibTeX RDF
11	Ryotaro Ohara, Masaya Kabuto, Masakazu Taichi, Atsushi Fukunaga, Yuto Yasuda, Riku Hamabe, Shintaro Izumi, Hiroshi Kawaguchi 0001	A 1W8R 20T SRAM Codebook for 20% Energy Reduction in Mixed-Precision Deep-Learning Inference Processor System.	AICAS	2023	DBLP DOI BibTeX RDF
11	Haoxiang Zhou, Haiqiao Hong, Dingbang Liu, Hang Liu, Yu Xia, Kai Li, Jun Liu, Shaobo Luo, Wei Mao 0002, Hao Yu 0001	RISC-V based Fully-Parallel SRAM Computing-in-Memory Accelerator with High Hardware Utilization and Data Reuse Rate.	AICAS	2023	DBLP DOI BibTeX RDF
11	Youyao Liu, Haihao Wang, Shihao Gai, Qifei Shi	Design of Multimode In-Memory Computing Architecture Based on SRAM.	ICNC-FSKD	2023	DBLP DOI BibTeX RDF
11	Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li, Hidehiro Fujiwara, Hung-Jen Liao, Tsung-Yung Jonathan Chang	3.7-GHz Multi-Bank High-Current Single-Port Cache SRAM with 0.5V-1.4V Wide Voltage Range Operation in 3nm FinFET for HPC Applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
11	Yumito Aoyagi, Makoto Yabuuchi, Tomotaka Tanaka, Yuichiro Ishii, Yoshiaki Osada, Takaaki Nakazato, Koji Nii, Isabel Wang, Yu-Hao Hsu, Hong-Chen Cheng, Hung-Jen Liao, Tsung-Yung Jonathan Chang	A 3-nm 27.6-Mbit/mm2 Self-timed SRAM Enabling 0.48 - 1.2 V Wide Operating Range with Far-end Pre-charge and Weak-Bit Tracking.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
11	Jonathan Chang, Yen-Huei Chen, Gary Chan, Kuo-Cheng Lin, Po-Sheng Wang, Yangsyu Lin, Sevic Chen, Peijiun Lin, Ching-Wei Wu, Chih-Yu Lin, Yi-Hsin Nien, Hidehiro Fujiwara, Atul Katoch, Robin Lee, Hung-Jen Liao, Jhon-Jhy Liaw, Shien-Yang Michael Wu, Quincy Li	A 3nm 256Mb SRAM in FinFET Technology with New Array Banking Architecture and Write-Assist Circuitry Scheme for High-Density and Low-VMIN Applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
11	Nick Zhang, Young Suk Kim, Peter Hsu, Samsoo Kim, Derek Tao, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li, Tsung-Yung Jonathan Chang	A 4.24GHz 128X256 SRAM Operating Double Pump Read Write Same Cycle in 5nm Technology.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
11	Gajanan Jedhe, Chetan Deshpande, Sushil Kumar, Cheng-Xin Xue, Zijie Guo, Ritesh Garg, Kim Soon Jway, En-Jui Chang, Jenwei Liang, Zhe Wan, Zhenhao Pan	A 12nm 137 TOPS/W Digital Compute-In-Memory using Foundry 8T SRAM Bitcell supporting 16 Kernel Weight Sets for AI Edge Applications.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
11	Jeongkyun Kim, Byungho Yook, Taemin Choi, Kyuwon Choi, Chanho Lee, Yunrong Li, Youngo Lee, Seok Yun, Changhoon Do, Hoyoung Tang, Inhak Lee, Dongwook Seo, Sangyeop Baeck	A 4.0GHz UHS Pseudo Two-port SRAM with BL Charge Time Reduction and Flying Word-Line for HPC Applications in 4nm FinFET Technology.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
11	Kenta Suzuki, Keizo Hiraga, Kazuhiro Bessho, Kimiyoshi Usami, Taku Umebayashi	A 40 nm 2 kb MTJ-Based Non-Volatile SRAM Macro with Novel Data-Aware Store Architecture for Normally Off Computing.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
11	Wei-Xiang You, Cheng-Yin Wang, Yih Wang, Tsung-Yung Jonathan Chang, Szuya Sandy Liao	Write-enhanced Single-ended 11T SRAM Enabling Single Bitcell Reconfigurable Compute-in-Memory Employing Complementary FETs.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
11	Joydeep Basu, Sachin Taneja, Viveka Konandur Rajanna, Tianqi Wang, Massimo Alioto	ECC-Less Multi-Level SRAM Physically Unclonable Function and 127% PUF-to-Memory Capacity Ratio with No Bitcell Modification in 28nm.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
11	Andrés Santana-Andreo, Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández 0001	A detailed, cell-by-cell look into the effects of aging on an SRAM PUF using a specialized test array.	SMACD	2023	DBLP DOI BibTeX RDF
11	Yanfang Liu, Guohao Dai, Yuanqing Cheng, Wang Kang 0001, Wei W. Xing	OPT: Optimal Proposal Transfer for Efficient Yield Optimization for Analog and SRAM Circuits.	ICCAD	2023	DBLP DOI BibTeX RDF
11	Syed Farah Naz, Mansi Chawla, Ambika Prasad Shah	Leakage Power Attack and Half Select Issue Resilient Split 8T SRAM Cell.	NEWCAS	2023	DBLP DOI BibTeX RDF
11	Vasundhara Damodaran, Ziyu Liu, Jae-Sun Seo, Arindam Sanyal	A Delta-Sigma Based SRAM Compute-in-Memory Macro for Human Activity Recognition.	BioCAS	2023	DBLP DOI BibTeX RDF
11	Yifei Li, Jian Chen, Yuqi Wang, Zihan Yin, Hongyu Chen, Yajun Ha	A 40nm 0.35V 25MHz Half-Select Disturb-Free Bitinterleaving 10T SRAM With Data-Aware Write-Path.	CICC	2023	DBLP DOI BibTeX RDF
11	Yong-Jun Jo, Boon Peng Yap, Dong-Hyun Yoon, Hyunjoon Kim, Yuanjin Zheng, Tony Tae-Hyoung Kim	DenseCIM: Binary Weighted-Capacitor SRAM Computation-In-Memory with Column-by-Column Dynamic Range Calibration SAR ADC.	CICC	2023	DBLP DOI BibTeX RDF
11	Peiyu Chen, Meng Wu, Wentao Zhao, Jiajia Cui, Zhixuan Wang, Yadong Zhang, Qijun Wang, Jiayoon Ru, Linxiao Shen, Tianyu Jia, Yufei Ma 0002, Le Ye, Ru Huang	A 22nm Delta-Sigma Computing-In-Memory (Δ∑CIM) SRAM Macro with Near-Zero-Mean Outputs and LSB-First ADCs Achieving 21.38TOPS/W for 8b-MAC Edge AI Processing.	ISSCC	2023	DBLP DOI BibTeX RDF
11	Giuseppe Desoli, Nitin Chawla, Thomas Boesch, Manui Avodhyawasi, Harsh Rawat, Hitesh Chawla, VS Abhijith, Paolo Zambotti, Akhilesh Sharma, Carmine Cappetta, Michele Rossi, Antonio De Vita, Francesca Girardi	A 40-310TOPS/W SRAM-Based All-Digital Up to 4b In-Memory Computing Multi-Tiled NN Accelerator in FD-SOI 18nm for Deep-Learning Edge Applications.	ISSCC	2023	DBLP DOI BibTeX RDF
11	Muya Chang, Ashwin Sanjay Lele, Samuel D. Spetalnick, Brian Crafton, Shota Konno, Zishen Wan, Ashwin Bhat, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury	A 73.53TOPS/W 14.74TOPS Heterogeneous RRAM In-Memory and SRAM Near-Memory SoC for Hybrid Frame and Event-Based Target Tracking.	ISSCC	2023	DBLP DOI BibTeX RDF
11	Ping-Chun Wu, Jian-Wei Su, Li-Yang Hong, Jin-Sheng Ren, Chih-Han Chien, Ho-Yu Chen, Chao-En Ke, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Wei-Chung Lo, Shih-Chieh Chang, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Meng-Fan Chang	A 22nm 832Kb Hybrid-Domain Floating-Point SRAM In-Memory-Compute Macro with 16.2-70.2TFLOPS/W for High-Accuracy AI-Edge Devices.	ISSCC	2023	DBLP DOI BibTeX RDF
11	Haruki Mori, Wei-Chang Zhao, Cheng-En Lee, Chia-Fu Lee, Yu-Hao Hsu, Chao-Kai Chuang, Takeshi Hashizume, Hao-Chun Tung, Yao-Yi Liu, Shin-Rung Wu, Kerem Akarvardar, Tan-Li Chou, Hidehiro Fujiwara, Yih Wang, Yu-Der Chih, Yen-Huei Chen, Hung-Jen Liao, Tsung-Yung Jonathan Chang	A 4nm 6163-TOPS/W/b $\mathbf{4790-TOPS/mm^{2}/b}$ SRAM Based Digital-Computing-in-Memory Macro Supporting Bit-Width Flexibility and Simultaneous MAC and Weight Update.	ISSCC	2023	DBLP DOI BibTeX RDF
11	Bo Wang, Chen Xue, Zhongyuan Feng, Zhaoyang Zhang, Han Liu, Lizheng Ren, Xiang Li, Anran Yin, Tianzhu Xiong, Yeyang Xue, Shengnan He, Yuyao Kong, Yongliang Zhou, An Guo, Xin Si, Jun Yang 0006	A 28nm Horizontal-Weight-Shift and Vertical-feature-Shift-Based Separate-WL 6T-SRAM Computation-in-Memory Unit-Macro for Edge Depthwise Neural-Networks.	ISSCC	2023	DBLP DOI BibTeX RDF
11	An Guo, Xin Si, Xi Chen, Fangyuan Dong, Xingyu Pu, Dongqi Li, Yongliang Zhou, Lizheng Ren, Yeyang Xue, Xueshan Dong, Hui Gao, Yiran Zhang, Jingmin Zhang, Yuyao Kong, Tianzhu Xiong, Bo Wang, Hao Cai, Weiwei Shan, Jun Yang 0006	A 28nm 64-kb 31.6-TFLOPS/W Digital-Domain Floating-Point-Computing-Unit and Double-Bit 6T-SRAM Computing-in-Memory Macro for Floating-Point CNNs.	ISSCC	2023	DBLP DOI BibTeX RDF
11	Yifan He, Haikang Diao, Chen Tang, Wenbin Jia, Xiyuan Tang, Yuan Wang 0001, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu	A 28nm 38-to-102-TOPS/W 8b Multiply-Less Approximate Digital SRAM Compute-In-Memory Macro for Neural-Network Inference.	ISSCC	2023	DBLP DOI BibTeX RDF
11	Niraj Kumar Singh, Ravi Shankar, Suraj Verma, Manodipan Sahoo	Design of low-power and high-performance 10 nm SRAM using Electrostatically doped TMD TFET.	ISDCS	2023	DBLP DOI BibTeX RDF
11	Madhava Sarma Vemuri, Umamaheswara Rao Tida	Small Footprint 6T-SRAM Design with MIV-Transistor Utilization in M3D-IC Technology.	ICCD	2023	DBLP DOI BibTeX RDF
11	Dhandeep Challagundla, Ignatius Bezzam, Biprangshu Saha, Riadul Islam	Resonant Compute-In-Memory (rCIM) 10T SRAM Macro for Boolean Logic.	ICCD	2023	DBLP DOI BibTeX RDF
11	Waqas Gul, Maitham Shams, Dhamin Al-Khalili	FinFET 6T-SRAM Compute-in-Memory Targeting Low Power Neural Networks Operations.	ISCAS	2023	DBLP DOI BibTeX RDF
11	Yangzhan Mai, Mingyu Wang, Chuanghao Zhang, Baiqing Zhong, Zhiyi Yu	A 1.97 TFLOPS/W Configurable SRAM-Based Floating-Point Computation-in-Memory Macro for Energy-Efficient AI Chips.	ISCAS	2023	DBLP DOI BibTeX RDF
11	Qibang Zang, Wang Ling Goh, Lu Lu 0013, Chengshuo Yu, Junjie Mu, Tony Tae-Hyoung Kim, Bongjin Kim, Dongrui Li, Anh Tuan Do	282-to-607 TOPS/W, 7T-SRAM Based CiM with Reconfigurable Column SAR ADC for Neural Network Processing.	ISCAS	2023	DBLP DOI BibTeX RDF
11	Om Prakash 0007, Rodion Novkin, Virinchi Roy Surabhi, Prashanth Krishnamurthy, Ramesh Karri, Farshad Khorrami, Hussam Amrouch	Comprehensive Reliability Analysis of 22nm FDSOI SRAM from Device Physics to Deep Learning.	ISCAS	2023	DBLP DOI BibTeX RDF
11	Seong-Beom Kim, Aarthy Mani, Leong Xu Heng Victor, Yuanjin Zheng, Anh Tuan Do	Stability Analysis of 6T SRAM at Deep Cryogenic Temperature for Quantum Computing Applications.	ISCAS	2023	DBLP DOI BibTeX RDF
11	Mohit Kumar Gupta 0001, Pieter Weckx, Manu Perumkunnil Komalan, Julien Ryckaert	Impact of interconnects enhancement on SRAM design beyond 5nm technology node.	ISCAS	2023	DBLP DOI BibTeX RDF
11	Zilin Wang, Hongyang Luo, ZeYang Peng, Xingchen Chao, Yajuan He	An 8T SRAM Based Digital Compute-In-Memory Macro For Multiply-And-Accumulate Accelerating.	ISCAS	2023	DBLP DOI BibTeX RDF
11	Ginés Doménech-Asensi, Ramón Ruiz Merino, Juan Zapata-Pérez, José Ángel Díaz-Madrid	A 12T SRAM in-Memory Computing differential current architecture for CNN implementations.	ISCAS	2023	DBLP DOI BibTeX RDF
11	Jesse Cirimelli-Low, Muhammad Hadir Khan, Samuel Crow, Amogh Lonkar, Bugra Onal, Andrew D. Zonenberg, Matthew R. Guthaus	SRAM Design with OpenRAM in SkyWater 130nm.	ISCAS	2023	DBLP DOI BibTeX RDF
11	Ashwin Sanjay Lele, Muya Chang, Samuel Spetalnick, Yan Fang, Brian Crafton, Shota Konno, Arijit Raychowdhury	Live Demonstration: Hybrid RRAM and SRAM SoC for Fused Frame and Event Target Tracking.	ISCAS	2023	DBLP DOI BibTeX RDF
11	Prokash Ghosh, Yogesh Gholap, Virendra Singh	On-Chip SRAM Disclosure Attack Prevention Technique for SoC.	IOLTS	2023	DBLP DOI BibTeX RDF
11	Yunus Emre Aslan, Florian Cacho, T. Kumar, D. K. Janardan, A. Kumar, F. Giner, M. Faurichon, Lorena Anghel	Minimum SRAM Retention Voltage: Insight about optimizing Power Efficiency across Temperature Profile, Process Variation and Aging.	IOLTS	2023	DBLP DOI BibTeX RDF
11	Hao-Chiao Hong, Chien-Hung Chen, Yu-Wun Chen	Parametric Faults in Computing-in-Memory Applications of a 4kb Read-Decoupled 8T SRAM Array in 40nm CMOS.	ITC-Asia	2023	DBLP DOI BibTeX RDF
11	Aibin Yan, Jing Xiang, Zhengfeng Huang, Tianming Ni, Jie Cui 0004, Patrick Girard 0001, Xiaoqing Wen	Design of A Highly Reliable and Low-Power SRAM With Double-Node Upset Recovery for Safety-critical Applications.	ITC-Asia	2023	DBLP DOI BibTeX RDF
11	Vita Pi-Ho Hu	Energy-Efficient SRAM with Emerging Technologies.	ICICDT	2023	DBLP DOI BibTeX RDF
11	Md. Abdullah-Al Kaiser, Edwin Tieu, Ajey P. Jacob, Akhilesh R. Jaiswal	A Context-Switching/Dual-Context ROM Augmented RAM using Standard 8T SRAM.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
11	Yanjun Li, Chunshan Zu, Bingqian Wang, Zhenhua Zhu, Yaojun Zhang, Ran Duan, Bing Li 0017, Bonan Yan	SRAM-Based Processing-In-Memory Design with Kullback-Leibler Divergence-Based Dynamic Precision Quantization.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
11	Debabrata Mondal, Syed Farah Naz, Ambika Prasad Shah	Radiation Hardened and Leakage Power Attack Resilient 12T SRAM Cell for Secure Nuclear Environments.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
11	Aibin Yan, Yang Chang, Jing Xiang, Hao Luo, Jie Cui 0004, Zhengfeng Huang, Tianming Ni, Xiaoqing Wen	Two Highly Reliable and High-Speed SRAM Cells for Safety-Critical Applications.	ACM Great Lakes Symposium on VLSI	2023	DBLP DOI BibTeX RDF
11	Renjie Wei, Kaifeng Wang, Zhixuan Wang, Libo Yang, Fangxing Zhang, Yongqin Wu, Ye Ren, Le Ye, Lining Zhang, Weihai Bu, Ru Huang, Qianqian Huang	A Novel TFET-MOSFET Hybrid SRAM for Ultra-Low-Power Applications.	ASICON	2023	DBLP DOI BibTeX RDF
11	Yuchao Zhang, Zihao Xuan, Yi Kang	A 28nm 15.09nJ/inference Neuromorphic Processor with SRAM-Based Charge Domain in-Memory-Computing.	ASICON	2023	DBLP DOI BibTeX RDF
11	Julian Dreyer, Ralf Tönjes, Nils Aschenbruck	ESPuF - Enabling SRAM PUFs on Commodity Hardware.	ICSPCS	2023	DBLP DOI BibTeX RDF
11	Devender Pal Singh, Priyanka Yadav, Menka Yadav	A 2-bit Multiplication Operation using Si-SiGe-Si Channel FinFET 8T-SRAM Cell.	iSES	2023	DBLP DOI BibTeX RDF
11	Akshat Raj Patil, Abin T. S. Vattoly, Pooran Singh	Assist Techniques for Radiation Hardened SRAM in Space Applications.	iSES	2023	DBLP DOI BibTeX RDF
11	Zhenlin Pei, Mahta Mayahinia, Hsiao-Hsuan Liu, Mehdi B. Tahoori, Shairfe Muhammad Salahuddin, Francky Catthoor, Zsolt Tokei, Chenyun Pan	Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access.	ISQED	2023	DBLP DOI BibTeX RDF
11	Jun Yin, Mircea R. Stan	A Low Power SRAM with Fully Dynamic Leakage Suppression for IoT Nodes.	ISQED	2023	DBLP DOI BibTeX RDF
11	Vidya A. Chhabria, Sachin S. Sapatnekar	Analysis of Pattern-dependent Rapid Thermal Annealing Effects on SRAM Design.	ISQED	2023	DBLP DOI BibTeX RDF
11	Shurun Li, Jie Liang, Liuyang Zhang	An Automatic Offset Compensation Sense Amplifier Featuring High Readout Reliability for SRAM.	ISOCC	2023	DBLP DOI BibTeX RDF
11	Mallemoggala Abhiram, Ball Mukund Mani Tripathi	Performance Evaluation of 9T and 6T SRAM Cells at 7nm Technology.	ICCCNT	2023	DBLP DOI BibTeX RDF
11	Saloni Bansal, V. K. Tomar	10T SRAM cell Analysis for improved Read and Write Noise Margin.	ICCCNT	2023	DBLP DOI BibTeX RDF
11	Deepak Mittal	Design a Gated PMOS Spillage Reduction Approach for CMOS SRAM Cell in 90nm Technology Node.	ICCCNT	2023	DBLP DOI BibTeX RDF
11	Deepak Mittal	SRAM Cell Leakage Reduction Methodologies for Low Leakage Cache Memories.	ICCCNT	2023	DBLP DOI BibTeX RDF
11	Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch	5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing.	DRC	2023	DBLP DOI BibTeX RDF
11	Young-Eun Choi, Woo-Seok Kim, Myoung Kim, Min-Woo Ryu, Kyung Rok Kim	Low Power and High Density Ternary-SRAM for Always-on Applications.	DRC	2023	DBLP DOI BibTeX RDF
11	Umeshwarnath Surendranathan, Horace Wilson, Biswajit Ray	Technology scaling effects on SRAM-PUF reliability under ionizing radiation.	DRC	2023	DBLP DOI BibTeX RDF
11	Umme Rani Irin, Sajib Barua, Md Minhajul Azmir, Tasnuva Hassan, Dewan Mohammed	Process Variation's Effect on Various Threshold Voltage Assignments in 6T SRAM Designs Using 12nm FinFET Technology.	CCWC	2023	DBLP DOI BibTeX RDF
11	Luk Burchard, Max Xiaohang Zhao, Johannes Langguth, Aydin Buluç, Giulia Guidi	Space Efficient Sequence Alignment for SRAM-Based Computing: X-Drop on the Graphcore IPU.	SC	2023	DBLP DOI BibTeX RDF
11	Varun Kohli, Muhammad Naveed Aman, Biplab Sikdar 0001	SRAM and Generative Network-based Physical Fingerprinting for Trust Management in the Internet of Things.	DSC	2023	DBLP DOI BibTeX RDF
11	Noopur Srivastava, Anil Kumar Rajput, Manisha Pattanaik, Gaurav Kaushal	An Energy-Efficient and Robust 10T SRAM Based in-Memory Computing Architecture.	VLSID	2023	DBLP DOI BibTeX RDF
11	Rupesh D. Kadhao, Siddharth R. K., Nithin Kumar Y. B., Vasantha M. H., Devesh Dwivedi	A 2.5 GHz, 1-Kb SRAM with Auxiliary Circuit Assisted Sense Amplifier in 65-nm CMOS Process.	VLSID	2023	DBLP DOI BibTeX RDF
11	Mohd Sakib Ansari S, Kavitha S, Bhupendra Singh Reniwal, Santosh Kumar Vishvakarma	Design of Radiation Hardened 12T SRAM with Enhanced Reliability and Read/Write Latency for Space Application.	VLSID	2023	DBLP DOI BibTeX RDF
11	Vinay Kumar, Vijay Sahu, Ambar Khanda, Sudhir Kumar	Dynamic Keeper for 1R1W 8T-SRAM to Enable Read Operation at 150c till 0.5v in 5nm FinFET.	VLSID	2023	DBLP DOI BibTeX RDF
11	Carmelo Felicetti, Antonino Rullo, Domenico Saccà	Security of IoT Devices with PUF-Based ID Tags: Preventing Hardware Substitution by Combining SRAM Cells Pattern Signature and ML Techniques.	DASC/PiCom/CBDCom/CyberSciTech	2023	DBLP DOI BibTeX RDF
11	Xin Zhang, Vishal Sharma, Yuncheng Lu, Yong-Jun Jo, Tony Tae-Hyoung Kim	A 400MHz 249.1TOPS/W 64Kb Fully-Reconfigurable SRAM-Based Digital Compute-in-Memory Macro for Accelerating CNNs.	A-SSCC	2023	DBLP DOI BibTeX RDF
11	Jingyao Zhang 0002, Mohsen Imani, Elaheh Sadredini	BP-NTT: Fast and Compact in-SRAM Number Theoretic Transform with Bit-Parallel Modular Multiplication.	DAC	2023	DBLP DOI BibTeX RDF
11	Yanfang Liu, Guohao Dai, Wei W. Xing	Seeking the Yield Barrier: High-Dimensional SRAM Evaluation Through Optimal Manifold.	DAC	2023	DBLP DOI BibTeX RDF
11	Sai Shubham, Shubham Pandit, Kailash Prasad, Joycee Mekie	PVC-RAM:Process Variation Aware Charge Domain In-Memory Computing 6T-SRAM for DNNs.	DAC	2023	DBLP DOI BibTeX RDF
11	Changhun Han, Hoon Sung Chwa, Kilho Lee, Sangeun Oh	SPET: Transparent SRAM Allocation and Model Partitioning for Real-time DNN Tasks on Edge TPU.	DAC	2023	DBLP DOI BibTeX RDF
11	Yun-Chen Lo, Ren-Shuo Liu	Morphable CIM: Improving Operation Intensity and Depthwise Capability for SRAM-CIM Architecture.	DAC	2023	DBLP DOI BibTeX RDF
11	Yan Ding 0004, Chubo Liu, Mingxing Duan, Wanli Chang 0001, Keqin Li 0001, Kenli Li 0001	HAIMA: A Hybrid SRAM and DRAM Accelerator-in-Memory Architecture for Transformer.	DAC	2023	DBLP DOI BibTeX RDF
11	Chengshuo Yu, Taegeun Yoo, Kevin Tshun Chuan Chai, Tony Tae-Hyoung Kim, Bongjin Kim	A 65-nm 8T SRAM Compute-in-Memory Macro With Column ADCs for Processing Neural Networks.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
11	Jian-Wei Su, Xin Si, Yen-Chi Chou, Ting-Wei Chang, Wei-Hsing Huang, Yung-Ning Tu, Ruhui Liu, Pei-Jung Lu, Ta-Wei Liu, Jing-Hong Wang, Yen-Lin Chung, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu 0009, Hongwu Jiang, Shanshi Huang, Sih-Han Li, Shyh-Shyuan Sheu, Chih-I Wu, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Shimeng Yu, Meng-Fan Chang	Two-Way Transpose Multibit 6T SRAM Computing-in-Memory Macro for Inference-Training AI Edge Chips.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
11	Taejoong Song, Hoonki Kim, Woojin Rim, Hakchul Jung, Changnam Park, Inhak Lee, Sanghoon Baek, Jonghoon Jung	A 3-nm Gate-All-Around SRAM Featuring an Adaptive Dual-Bitline and an Adaptive Cell-Power Assist Circuit.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
11	Keonhee Cho, Heekyung Choi, In Jun Jung, Ji Sang Oh, Tae Woo Oh, Ki-Ryong Kim, Giseok Kim, Taemin Choi, Changsu Sim, Taejoong Song, Seong-Ook Jung	SRAM Write- and Performance-Assist Cells for Reducing Interconnect Resistance Effects Increased With Technology Scaling.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
11	Jiacong Sun, Hao Guo, Geng Li, Hailong Jiao	An Ultra-Low-Voltage Bit-Interleaved Synthesizable 13T SRAM Circuit.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
11	Andrés Santana-Andreo, Pablo Saraza-Canflanca, Héctor Carrasco-Lopez, Piedad Brox, Rafael Castro-López, Elisenda Roca, Francisco V. Fernández 0001	A DRV-based bit selection method for SRAM PUF key generation and its impact on ECCs.	Integr.	2022	DBLP DOI BibTeX RDF
11	Jani Babu Shaik, Sonal Singhal, Siona Menezes Picardo, Nilesh Goel	Impact of various NBTI distributions on SRAM performance for FinFET technology.	Integr.	2022	DBLP DOI BibTeX RDF
11	Raghav Shekhar, Chaudhry Indra Kumar	Design of highly reliable radiation hardened 10T SRAM cell for low voltage applications.	Integr.	2022	DBLP DOI BibTeX RDF
11	Panagiotis Chatziantoniou, Antonis Tsigkanos, Dimitris Theodoropoulos, Nektarios Kranitis, Antonis M. Paschalis	An Efficient Architecture and High-Throughput Implementation of CCSDS-123.0-B-2 Hybrid Entropy Coder Targeting Space-Grade SRAM FPGA Technology.	IEEE Trans. Aerosp. Electron. Syst.	2022	DBLP DOI BibTeX RDF
11	K. Gavaskar, M. Sankara Narayanan, M. Sreenidhi Nachammal, K. Vignesh	Design and comparative analysis of SRAM array using low leakage controlled transistor technique with improved delay.	J. Ambient Intell. Humaniz. Comput.	2022	DBLP DOI BibTeX RDF