Search results for "self-test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
11	Andrzej Krasniewski	Application-Dependent Testing of FPGA Delay Faults.	EUROMICRO	1999	DBLP DOI BibTeX RDF
11	Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung	Self-Measurement of Combinatorial Circuit Delays in FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	FPGA, Testing, configuration, delay measurement
11	Yun-Che Wen	Test scheme for switched-capacitor circuits by digital analyses.	DDECS	2009	DBLP DOI BibTeX RDF
11	Brendan Mullane, Vincent O'Brien, Ciaran MacNamee, Thomas Fleischmann	An SOC platform for ADC test and measurement.	DDECS	2009	DBLP DOI BibTeX RDF
11	Chunhua Yao, Kewal K. Saluja, Abhishek A. Sinkar	WOR-BIST: A Complete Test Solution for Designs Meeting Power, Area and Performance Requirements.	VLSI Design	2009	DBLP DOI BibTeX RDF
11	Haralampos-G. D. Stratigopoulos, Jeanne Tongbong, Salvador Mir	A General Method to Evaluate RF BIST Techniques Based on Non-parametric Density Estimation.	DATE	2008	DBLP DOI BibTeX RDF
11	Dong Xiang, Mingjing Chen, Hideo Fujiwara	Using Weighted Scan Enable Signals to Improve Test Effectiveness of Scan-Based BIST.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Random testability, scan enable signal, weighted random testing, scan-based BIST
11	Rani S. Ghaida, Payman Zarkesh-Ha	Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model.	DFT	2007	DBLP DOI BibTeX RDF
11	Daniela De Venuto, Leonardo Reyneri	Analysis and experimental results of an FPGA-based strategy for fast production test of high resolution ADCs.	ISQED	2006	DBLP DOI BibTeX RDF
11	Luís Rolíndez, Salvador Mir, Ahcène Bounceur, Jean-Louis Carbonéro	A SNDR BIST for Sigma-Delta Analogue-to-Digital Converters.	VTS	2006	DBLP DOI BibTeX RDF
11	Swarup Bhunia, Hamid Mahmoodi-Meimand, Debjyoti Ghosh, Saibal Mukhopadhyay, Kaushik Roy 0001	Low-power scan design using first-level supply gating.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
11	Milos Krstic, Eckhard Grass	BIST Technique for GALS Systems.	DSD	2005	DBLP DOI BibTeX RDF
11	Ernesto Sánchez 0001, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	Automatic generation of test sets for SBST of microprocessor IP cores.	SBCCI	2005	DBLP DOI BibTeX RDF	FPGA, hardware accelerator, automatic test generation, pipelined architectures, microprocessor test, test programs
11	Mohammed Y. Niamat, Surya S. Hejeebu, Mansoor Alam	A BIST Approach for Testing FPGAs Using JBITS.	FCCM	2005	DBLP DOI BibTeX RDF
11	Beatriz Olleta, Hanjun Jiang, Degang Chen 0001, Randall L. Geiger	A segmented thermometer coded DAC with deterministic dynamic element matching for high resolution ADC test.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
11	Jiann-Chyi Rau, Ying-Fu Ho, Po-Han Wu	A novel reseeding mechanism for pseudo-random testing of VLSI circuits.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
11	Kirti Joshi, Eric W. MacDonald	Reduction of Instantaneous Power by Ripple Scan Clocking.	VTS	2005	DBLP DOI BibTeX RDF
11	Swarup Bhunia, Hamid Mahmoodi-Meimand, Saibal Mukhopadhyay, Debjyoti Ghosh, Kaushik Roy 0001	A Novel Low-Power Scan Design Technique Using Supply Gating.	ICCD	2004	DBLP DOI BibTeX RDF
11	Zhongjun Yu, Degang Chen 0001, Randall L. Geiger	Accurate testing of ADC's spectral performance using imprecise sinusoidal excitations.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
11	Selim Sermet Akbay, Abhijit Chatterjee	Feature Extraction Based Built-In Alternate Test of RF Components Using a Noise Reference.	VTS	2004	DBLP DOI BibTeX RDF
11	Gang Zeng, Hideo Ito	Hybrid BIST for System-on-a-Chip Using an Embedded FPGA Core.	VTS	2004	DBLP DOI BibTeX RDF
11	Heinz Mattes, Claus Dworski, Sebastian Sattler	Controlled Sine Wave Fitting for ADC Test.	ITC	2004	DBLP DOI BibTeX RDF
11	Omar I. Khan, Michael L. Bushnell	Spectral Analysis for Statistical Response Compaction During Built-In Self-Testing.	ITC	2004	DBLP DOI BibTeX RDF
11	Yi Zhao, Sujit Dey	Fault-coverage analysis techniques of crosstalk in chip interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
11	Chunsheng Liu, Krishnendu Chakrabarty	Failing vector identification based on overlapping intervals of test vectors in a scan-BIST environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
11	Jeongjin Roh, Jacob A. Abraham	A comprehensive signature analysis scheme for oscillation-test.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
11	Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan	Multimode scan: Test per clock BIST for IP cores.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	SoC, BIST, scan, digital testing
11	Debjyoti Ghosh, Swarup Bhunia, Kaushik Roy 0001	Multiple Scan Chain Design Technique for Power Reduction during Test Application in BIST.	DFT	2003	DBLP DOI BibTeX RDF
11	Adam B. Kinsman, Jonathan I. Hewitt, Nicola Nicolici	Embedded Compact Deterministic Test for IP-Protected Cores.	DFT	2003	DBLP DOI BibTeX RDF
11	Peter Wohl, Leendert M. Huisman	Analysis and Design of Optimal Combinational Compactors.	VTS	2003	DBLP DOI BibTeX RDF
11	Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang 0008	Double-Tree Scan: A Novel Low-Power Scan-Path Architecture.	ITC	2003	DBLP DOI BibTeX RDF
11	Dong Xiang, Hideo Fujiwara	Handling the pin overhead problem of DFTs for high-quality and at-speed tests.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
11	Christian Galke, Matthias Pflanz, Heinrich Theodor Vierhaus	A Test Processor Concept for Systems-on-a-Chip.	ICCD	2002	DBLP DOI BibTeX RDF
11	Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici	Low Power Mixed-Mode BIST Based on Mask Pattern Generation Using Dual LFSR Re-Seeding.	ICCD	2002	DBLP DOI BibTeX RDF
11	Robert Bailey, A. Metayer, B. Svrcek, Nandu Tendolkar, E. Wolf, Eric Fiene, Mike Alexander, Rick Woltenberg, Rajesh Raina	Test Methodology for Motorola's High Performance e500 Core Based on PowerPC Instruction Set Architecture.	ITC	2002	DBLP DOI BibTeX RDF
11	Nur A. Touba, Edward J. McCluskey	Bit-fixing in pseudorandom sequences for scan BIST.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
11	Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian	Switching activity generation with automated BIST synthesis forperformance testing of interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
11	Peter Bukovjan, Laurent Ducerf-Bourbon, Meryem Marzouki	Cost/Quality Trade-off in Synthesis for BIST.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	DFT reuse, BIST, synthesis for testability, testability analysis
11	Ching-Hong Tsai, Cheng-Wen Wu	Processor-programmable memory BIST for bus-connected embedded memories.	ASP-DAC	2001	DBLP DOI BibTeX RDF
11	Tobias Schüle, Albrecht P. Stroele	Test Scheduling for Minimal Energy Consumption under Power Constraints.	VTS	2001	DBLP DOI BibTeX RDF
11	Han Bin Kim, Dong Sam Ha, Takeshi Takahashi 0003, Takahiro J. Yamaguchi	A new approach to built-in self-testable datapath synthesis based on integer linear programming.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
11	Xiaodong Zhang 0010, Wenlei Shan, Kaushik Roy 0001	Low-power weighted random pattern testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
11	Jacob Savir	Distributed BIST Architecture to Combat Delay Faults.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	BIST, LFSR, delay test, MISR, LSSD, SRL
11	Patrick Girard 0001	Low Power Testing of VLSI Circuits: Problems and Solutions.	ISQED	2000	DBLP DOI BibTeX RDF	Test, Low Power, ATPG, BIST, Low Energy
11	Jin Ding, David Moloney, Xiaojun Wang 0001	Aliasing-Free Space and Time Compactions with Limited Overhead.	ISQED	2000	DBLP DOI BibTeX RDF
11	Yuejian Wu, Saman Adham	Scan-based BIST fault diagnosis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
11	Hafizur Rahaman 0001, Debesh K. Das, Bhargab B. Bhattacharya	An Adaptive BIST to Detect Multiple Stuck-Open Faults in CMOS circuits.	ASP-DAC	1999	DBLP DOI BibTeX RDF
11	Patrick Girard 0001, Loïs Guiller, Christian Landrault, Serge Pravossoudovitch	Circuit Partitioning for Low Power BIST Design with Minimized Peak Power Consumption.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	BIST Design, Test, Low-power Design, Energy Consumption
11	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST.	VTS	1999	DBLP DOI BibTeX RDF
11	Paulo F. Flores, José C. Costa, Horácio C. Neto, José Monteiro 0001, João Marques-Silva 0001	Assignment and Reordering of Incompletely Specified Pattern Sequences Targetting Minimum Power Dissipation.	VLSI Design	1999	DBLP DOI BibTeX RDF
11	Nilanjan Mukherjee 0001, Tapan J. Chakraborty, Sudipta Bhawmik	A BIST scheme for the detection of path-delay faults.	ITC	1998	DBLP DOI BibTeX RDF
11	Huan-Chih Tsai, Sudipta Bhawmik, Kwang-Ting Cheng	An almost full-scan BIST solution-higher fault coverage and shorter test application time.	ITC	1998	DBLP DOI BibTeX RDF
11	Jacob Savir	Delay Test Generation: A Hardware Perspective.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	transition test, skewed-load delay test, shift dependency, cellular automata, linear feedback shift register, delay test, pseudo-random test
11	Chih-Ang Chen, Sandeep K. Gupta	Design of efficient BIST test pattern generators for delay testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
11	Ting-Ting Y. Lin, Huoy-Yu Liou	A New Framework for Designing: Built-in Test Multichip Modules with Pipelined Test Strategy.	IEEE Des. Test Comput.	1993	DBLP DOI BibTeX RDF
10	Ben Liu, Hejie Chen, Wei He	Wiki-based collaborative learning: incorporating self-assessment tasks.	Int. Sym. Wikis	2008	DBLP DOI BibTeX RDF	item model, wiki-based collaborative learning, formative assessment, computer assisted assessment
10	S. Habermann, René Kothe, Heinrich Theodor Vierhaus	Built-in Self Repair by Reconfiguration of FPGAs.	IOLTS	2006	DBLP DOI BibTeX RDF
10	Radek Dobias, Hana Kubátová	FPGA Based Design of the Railway's Interlocking Equipments.	DSD	2004	DBLP DOI BibTeX RDF
10	Jaeki Yoo, Edward Lee, Earl E. Swartzlander Jr.	A self-testing method for the pipelined A/D converter.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
10	Flavius Opritoiu, Mircea Vladutiu, Mihai Udrescu, Lucian Prodan	Round-level concurrent error detection applied to Advanced Encryption Standard.	DDECS	2009	DBLP DOI BibTeX RDF
10	Tianjia Sun, Li Guo 0004	One New In-Operation Self-Testability Mechanism Designed for SoC Microchips following IEEE STD 1500.	ICPP Workshops	2007	DBLP DOI BibTeX RDF
10	Liyang Lai, Janak H. Patel, Thomas Rinderknecht, Wu-Tung Cheng	Logic BIST with Scan Chain Segmentation.	ITC	2004	DBLP DOI BibTeX RDF
10	Manoj Singh Gaur, Mark Zwolinski	Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique.	VLSI Design	2004	DBLP DOI BibTeX RDF
10	Benoit Nadeau-Dostie, Dwayne Burek, Abu S. M. Hassan	ScanBist: A Multifrequency Scan-Based BIST Method.	IEEE Des. Test Comput.	1994	DBLP DOI BibTeX RDF
10	Bernhard Eschermann, Hans-Joachim Wunderlich	Optimized synthesis techniques for testable sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
9	Bin Zhou, Yizheng Ye, Zhao-lin Li, Xin-chun Wu, Rui Ke	A new low power test pattern generator using a variable-length ring counter.	ISQED	2009	DBLP DOI BibTeX RDF
9	Ioannis Voyiatzis, Antonis M. Paschalis, Dimitris Gizopoulos, Constantin Halatsis, Frosso S. Makri, Miltiadis Hatzimihail	An Input Vector Monitoring Concurrent BIST Architecture Based on a Precomputed Test Set.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF
9	Jayawant Kakade, Dimitrios Kagaris, Dhiraj K. Pradhan	Evaluation of Generalized LFSRs as Test Pattern Generators in Two-Dimensional Scan Designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
9	Waleed K. Al-Assadi, Sindhu Kakarla	A BIST Technique for Crosstalk Noise Detection in FPGAs.	DFT	2008	DBLP DOI BibTeX RDF
9	Byoungho Kim, Nash Khouzam, Jacob A. Abraham	Efficient Loopback Test for Aperture Jitter in Embedded Mixed-Signal Circuits.	VTS	2008	DBLP DOI BibTeX RDF	Loopback Test, Aperture Jitter, Digital-to-Analog Converter, Analog-to-Digital Converter, ADC, Mixed-Signal Testing, DAC
9	Salvador Manich, Lucas Garcia-Deiros, Joan Figueras	Minimizing Test Time in Arithmetic Test-Pattern Generators With Constrained Memory Resources.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
9	Jayawant Kakade, Dimitrios Kagaris	Minimization of Linear Dependencies Through the Use of Phase Shifters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
9	Petr Fiser	Pseudo-Random Pattern Generator Design for Column-Matching BIST.	DSD	2007	DBLP DOI BibTeX RDF
9	Letícia Maria Veiras Bolzani, Edgar E. Sánchez, Matteo Sonza Reorda	A software-based methodology for the generation of peripheral test sets based on high-level descriptions.	SBCCI	2007	DBLP DOI BibTeX RDF	RT-level test metrics, code coverage metrics, gate-level test metrics, test block, fault coverage, SoC testing
9	Nan-Cheng Lai, Sying-Jyan Wang, Y.-H. Fu	Low-Power BIST With a Smoother and Scan-Chain Reorder Under Optimal Cluster Size.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
9	Seongmoon Wang, Sandeep K. Gupta 0001	LT-RTPG: a new test-per-scan BIST TPG for low switching activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
9	Paolo Bernardi, Ernesto Sánchez 0001, Massimiliano Schillaci, Giovanni Squillero, Matteo Sonza Reorda	An effective technique for minimizing the cost of processor software-based diagnosis in SoCs.	DATE	2006	DBLP DOI BibTeX RDF
9	Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur	Pseudorandom functional BIST for linear and nonlinear MEMS.	DATE	2006	DBLP DOI BibTeX RDF
9	Hsieh-Hung Hsieh, Liang-Hung Lu	Integrated CMOS Power Sensors for RF BIST Applications.	VTS	2006	DBLP DOI BibTeX RDF
9	Maria Da Gloria Flores, Marcelo Negreiros, Luigi Carro, Altamiro Amadeu Susin, Felipe R. Clayton, Cristiano Benevento	Low Cost BIST for Static and Dynamic Testing of ADCs.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	ADC BIST, noise based testing, mixed-signal test
9	Paolo Bernardi, Ernesto Sánchez 0001, Massimiliano Schillaci, Matteo Sonza Reorda, Giovanni Squillero	Diagnosing Faulty Functional Units in Processors by Using Automatically Generated Test Sets.	MTV	2005	DBLP DOI BibTeX RDF
9	Achraf Dhayni, Salvador Mir, Libor Rufer, Ahcène Bounceur	On-chip Pseudorandom Testing for Linear and Nonlinear MEMS.	VLSI-SoC	2005	DBLP DOI BibTeX RDF
9	Wenbo Liu, Hanqing Xing, Le Jin, Randall L. Geiger, Degang Chen 0001	A test strategy for time-to-digital converters using dynamic element matching and dithering.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
9	Jin-Fu Li 0001, Chou-Kun Lin	Modeling and Testing Comparison Faults for Ternary Content Addressable Memories.	VTS	2005	DBLP DOI BibTeX RDF
9	Abhijit Jas, C. V. Krishna, Nur A. Touba	Weighted pseudorandom hybrid BIST.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
9	Laurence Tianruo Yang, Jon C. Muzio	Testing Methodologies for Embedded Systems and Systems-on-Chip.	ICESS	2004	DBLP DOI BibTeX RDF
9	Liyang Lai, Thomas Rinderknecht, Wu-Tung Cheng, Janak H. Patel	Logic BIST Using Constrained Scan Cells.	VTS	2004	DBLP DOI BibTeX RDF
9	Subhasish Mitra, Steven S. Lumetta, Michael Mitzenmacher	X-Tolerant Signature Analysis.	ITC	2004	DBLP DOI BibTeX RDF
9	Bai Hong Fang, Nicola Nicolici	Power-Constrained Embedded Memory BIST Architecture.	DFT	2003	DBLP DOI BibTeX RDF
9	Le Jin, Kumar L. Parthasarathy, Turker Kuyel, Degang Chen 0001, Randall L. Geiger	Linearity Testing of Precision Analog-to-Digital Converters Using Stationary Nonlinear Inputs.	ITC	2003	DBLP DOI BibTeX RDF
9	George Bao	Challenges in Low Cost Test Approach for ARM9TM Core Based Mixed-Signal SoC DragonBallTM-MX1.	ITC	2003	DBLP DOI BibTeX RDF
9	C. P. Ravikumar, Nitin Kakkar, Saurabh Chopra	Mutual Testing based on Wavelet Transforms.	VLSI Design	2003	DBLP DOI BibTeX RDF	Mutual Testing, Discrete Wavelet Transform, At-Speed Testing
9	Wei Li 0023, Chaowen Yu, Sudhakar M. Reddy, Irith Pomeranz	A scan BIST generation method using a markov source and partial bit-fixing.	DAC	2003	DBLP DOI BibTeX RDF	testing, BIST, markov
9	Seongmoon Wang, Sandeep K. Gupta 0001	DS-LFSR: a BIST TPG for low switching activity.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
9	Aleksandra Rankov, Gaynor E. Taylor, John Webster	Robust Data Compression for Analogue Test Outputs.	IOLTW	2002	DBLP DOI BibTeX RDF
9	C. V. Krishna, Nur A. Touba	Reducing Test Dat Volume Using LFSR Reseeding with Seed Compression.	ITC	2002	DBLP DOI BibTeX RDF
9	Mike W. T. Wong, K. Y. Ko, Yim-Shu Lee	Analog and Mixed-Signal IP Cores Testing.	DELTA	2002	DBLP DOI BibTeX RDF	mixed-signal design, analog circuit testing, SOCs
9	Serge N. Demidenko, Ad J. van de Goor, S. Henderson, P. Knoppers	Simulation and Development of Short Transparent Tests for RAM.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
9	Kenichi Ichino, Takeshi Asakawa, Satoshi Fukumoto, Kazuhiko Iwasaki, Seiji Kajihara	Hybrid BIST Using Partially Rotational Scan.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
9	Xiaoling Sun, Jian Xu, Pieter M. Trouborst	Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules.	DFT	2001	DBLP DOI BibTeX RDF	configurable logic blocks, fault diagnosis, BIST, FPGA testing