Search results for "field-programmable"

Hits ?▲	Authors	Title	Venue	Year	Link
15	Sushil Chandra Jain, Anshul Kumar, Shashi Kumar	Hybrid Multi-FPGA Board Evaluation by Limiting Multi-Hop Routing.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
15	Charles E. Stroud, Jeremy Nall, Matthew Lashinsky, Miron Abramovici	BIST-Based Diagnosis of FPGA Interconnect.	ITC	2002	DBLP DOI BibTeX RDF
15	W. Shi, K. Kumar, Fabrizio Lombardi	On the Complexity of Switch Programming in Fault-Tolerant-Configurable Chips.	DFT	2000	DBLP DOI BibTeX RDF
15	Bharat P. Dave	CRUSADE: Hardware/Software Co-Synthesis of Dynamically Reconfigurable Heterogeneous Real-Time Distributed Embedded Systems.	DATE	1999	DBLP DOI BibTeX RDF
15	Akihiro Tsutsui, Toshiaki Miyazaki	ANT-on-YARDS: FPGA/MPU hybrid architecture for telecommunication data processing.	IEEE Trans. Very Large Scale Integr. Syst.	1998	DBLP DOI BibTeX RDF
15	David Marple	An MPGA-Like FPGA.	IEEE Des. Test Comput.	1992	DBLP DOI BibTeX RDF
15	Bernard Girau	Digital Hardware Implementation of 2D Compatible Neural Networks.	IJCNN (3)	2000	DBLP DOI BibTeX RDF
14	Jun Dong, Tongfei Wang, Yueming Deng, Runmin Wang	Adaptive wavelet transform defogging scheme for real-time video restoration with field programmable gate array implementation.	J. Electronic Imaging	2024	DBLP DOI BibTeX RDF
14	Yadongyang Zhu, Shuguang Zhao, Fudong Zhang, Wei Wei, Fa Zhao	Edge-Intelligence-Based Seismic Event Detection Using a Hardware-Efficient Neural Network With Field-Programmable Gate Array.	IEEE Internet Things J.	2024	DBLP DOI BibTeX RDF
14	George Higgins Hutchinson, Ethan Sifferman, Tinish Bhattacharya, Dmitri B. Strukov	FPIA: Field-Programmable Ising Arrays with In-Memory Computing.	CoRR	2024	DBLP DOI BibTeX RDF
14	Daniel Bochen Tan, Dolev Bluvstein, Mikhail D. Lukin, Jason Cong	Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors.	Quantum	2024	DBLP DOI BibTeX RDF
14	Jehyuk Jang, Jamie Judd	An Efficient SNARK for Field-Programmable and RAM Circuits.	IACR Cryptol. ePrint Arch.	2024	DBLP BibTeX RDF
14	Marc Majoral, Javier Arribas, Carles Fernández-Prades	Implementation of a High-Sensitivity Global Navigation Satellite System Receiver on a System-on-Chip Field-Programmable Gate Array Platform.	Sensors	2024	DBLP DOI BibTeX RDF
14	Marco Grossi	Efficient and Accurate Analog Voltage Measurement Using a Direct Sensor-to-Digital Port Interface for Microcontrollers and Field-Programmable Gate Arrays.	Sensors	2024	DBLP DOI BibTeX RDF
14	Gerardo De J. Martinez-Figueroa, Felipe Córcoles-López, Santiago Bogarra	Field Programmable Gate Array-Based Smart Switch to Avoid Inrush Current in PV Installations.	Sensors	2024	DBLP DOI BibTeX RDF
14	Mudasar Basha, Munuswamy Siva Kumar, Mangali Chinna Chinnaiah, Siew-Kei Lam, Thambipillai Srikanthan, Narambhatla Janardhan, Dodde Hari Krishna, Sanjay Dubey	Hardware Schemes for Smarter Indoor Robotics to Prevent the Backing Crash Framework Using Field Programmable Gate Array-Based Multi-Robots.	Sensors	2024	DBLP DOI BibTeX RDF
14	Yan Wang 0028, Peirui Liu, Dalin Li, Kangping Wang, Rui Zhang	An Image Histogram Equalization Acceleration Method for Field-Programmable Gate Arrays Based on a Two-Dimensional Configurable Pipeline.	Sensors	2024	DBLP DOI BibTeX RDF
14	Jorge Jiménez-Sánchez, Pedro Blanco-Carmona, Jose Maria Hinojo Montero, Francisco Rogelio Palomo, Rafael Luis Millán, Fernando Muñoz Chavero	Advanced System-on-Chip Field-Programmable-Gate-Array-Powered Data Acquisition System for Pixel Detectors.	Sensors	2024	DBLP DOI BibTeX RDF
14	Wen-Chung Tsai	Field-Programmable Gate Array-Based Implementation of Zero-Trust Stream Data Encryption for Enabling 6G-Narrowband Internet of Things Massive Device Access.	Sensors	2024	DBLP DOI BibTeX RDF
14	Bo Cui, Lingyun Wang, Guangxi Li, Xian Ren	Field Programmable Gate Array-Based Acceleration Algorithm Design for Dynamic Star Map Parallel Computing.	Algorithms	2024	DBLP DOI BibTeX RDF
14	Zhiru Zhang, Andrew Putnam (eds.)	Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2024, Monterey, CA, USA, March 3-5, 2024	FPGA	2024	DBLP DOI BibTeX RDF
14	Tomoya Ogawa, Ken Matsubara, Yasuhiko Taito, Tomoya Saito, Masayuki Izuna, Koichi Takeda, Yoshinobu Kaneda, Takahiro Shimoi, Hidenori Mitani, Takashi Ito, Takashi Kono	15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs.	ISSCC	2024	DBLP DOI BibTeX RDF
14	Mahdi Abbaszadeh, Dana L. How	From Topology to Realization in FPGA/VPR Routing.	FPGA	2024	DBLP DOI BibTeX RDF
14	Louis-Noël Pouchet, Emily Tucker, Niansong Zhang, Hongzheng Chen, Debjit Pal, Gabriel Rodríguez 0001, Zhiru Zhang	Formal Verification of Source-to-Source Transformations for HLS.	FPGA	2024	DBLP DOI BibTeX RDF
14	Shaoxian Xu, Sitong Lu, Zhiyuan Shao, Xiaofei Liao, Hai Jin 0001	MiCache: An MSHR-inclusive Non-blocking Cache Design for FPGAs.	FPGA	2024	DBLP DOI BibTeX RDF
14	Hongzheng Chen, Jiahao Zhang, Yixiao Du, Shaojie Xiang, Zichao Yue, Niansong Zhang, Yaohui Cai, Zhiru Zhang	A Comprehensive Evaluation of FPGA-Based Spatial Acceleration of LLMs.	FPGA	2024	DBLP DOI BibTeX RDF
14	Greg Stitt, Wesley Piard, Christopher Crary	Low-Latency, Line-Rate Variable-Length Field Parsing for 100+ Gb/s Ethernet.	FPGA	2024	DBLP DOI BibTeX RDF
14	Zhigang Wei, Aman Arora, Emily Shriver, Lizy Kurian John	Cross-FPGA Power Estimation from High Level Synthesis via Transfer-Learning.	FPGA	2024	DBLP DOI BibTeX RDF
14	Jiahui Xu, Lana Josipovic	Suppressing Spurious Dynamism of Dataflow Circuits via Latency and Occupancy Balancing.	FPGA	2024	DBLP DOI BibTeX RDF
14	Xiaoyu Niu, Yanjun Zhang, Yifan Zhang, Hongzheng Tian, Bo Yu 0014, Shaoshan Liu, Sitao Huang	Accelerating Autonomous Path Planning on FPGAs with Sparsity-Aware HW/SW Co-Optimizations.	FPGA	2024	DBLP DOI BibTeX RDF
14	Youwei Xiao, Zizhang Luo, Kexing Zhou, Yun Liang 0001	Cement: Streamlining FPGA Hardware Design with Cycle-Deterministic eHDL and Synthesis.	FPGA	2024	DBLP DOI BibTeX RDF
14	Dongjoon Park, André DeHon	REFINE: Runtime Execution Feedback for INcremental Evolution on FPGA Designs.	FPGA	2024	DBLP DOI BibTeX RDF
14	Shulin Zeng, Jun Liu, Guohao Dai, Xinhao Yang, Tianyu Fu 0004, Hongyi Wang, Wenheng Ma, Hanbo Sun, Shiyao Li, Zixiao Huang, Yadong Dai, Jintao Li, Zehao Wang, Ruoyu Zhang, Kairui Wen, Xuefei Ning, Yu Wang	FlightLLM: Efficient Large Language Model Inference with a Complete Mapping Flow on FPGAs.	FPGA	2024	DBLP DOI BibTeX RDF
14	Thore Gerlach, Stefan Knipp, David Biesner, Stelios Emmanouilidis, Klaus Hauber, Nico Piatkowski	FPGA-Placement via Quantum Annealing.	FPGA	2024	DBLP DOI BibTeX RDF
14	Timothy Sherwood	Security, Synapses, Sustainability, and Superconducting: A Look at Possible Futures for the FPGA.	FPGA	2024	DBLP DOI BibTeX RDF
14	Andy Ray, Benjamin Devlin, Fu Yong Quah, Rahul Yesantharao	Hardcaml: An OCaml Hardware Domain-Specific Language for Efficient and Robust Design.	FPGA	2024	DBLP DOI BibTeX RDF
14	Prabhat K. Gupta	My Fifteen Year Journey of Deploying FPGA Accelerated Solutions.	FPGA	2024	DBLP DOI BibTeX RDF
14	Hui Wei 0001, Jingyong Ye, Yutong Chen, Heng Wu	Design and Implementation of a Primary Visual Cortex Pathway Model Based on Opponent-process Theory.	FPGA	2024	DBLP DOI BibTeX RDF
14	Zhenyu Xu, Miaoxiang Yu, Jillian Cai, Saddam Gafsi, Judson Douglas Ryckman, Qing Yang 0001, Tao Wei	An FPGA-Enabled Framework for Rapid Automated Design of Photonic Integrated Circuits.	FPGA	2024	DBLP DOI BibTeX RDF
14	Will Lin, Yizhou Shan, Ryan Kosta, Arvind Krishnamurthy, Yiying Zhang 0005	SuperNIC: An FPGA-Based, Cloud-Oriented SmartNIC.	FPGA	2024	DBLP DOI BibTeX RDF
14	Qizhe Wu, Letian Zhao, Yuchen Gui, Huawen Liang, Xiaotian Wang, Xi Jin 0002	Efficient Message Passing Architecture for GCN Training on HBM-based FPGAs with Orthogonal Topology On-Chip Networks.	FPGA	2024	DBLP DOI BibTeX RDF
14	Muhammed Kawser Ahmed, Christophe Bobda	ISO-TENANT: Rethinking FPGA Power Distribution Network (PDN): A Hardware Based Solution for Remote Power Side Channel Attacks in FPGA.	FPGA	2024	DBLP DOI BibTeX RDF
14	Manoj B. Rajashekar, Xingyu Tian, Zhenman Fang	HiSpMV: Hybrid Row Distribution and Vector Buffering for Imbalanced SpMV Acceleration on FPGAs.	FPGA	2024	DBLP DOI BibTeX RDF
14	Geng Yang, Jie Lei 0001, Zhenman Fang, Jiaqing Zhang, Junrong Zhang, Weiying Xie, Yunsong Li	E4SA: An Ultra-Efficient Systolic Array Architecture for 4-Bit Convolutional Neural Networks.	FPGA	2024	DBLP DOI BibTeX RDF
14	Yan Chen, Kiyofumi Tanaka	A Flexible, Fast, Low Bandwidth Block-based Acceleration Architecture for CNN Inference on FPGAs.	FPGA	2024	DBLP DOI BibTeX RDF
14	Zifan He, Linghao Song, Robert F. Lucas, Jason Cong	LevelST: Stream-based Accelerator for Sparse Triangular Solver.	FPGA	2024	DBLP DOI BibTeX RDF
14	Xiaochen Hao, Hongbo Rong, Mingzhe Zhang, Ce Sun, Hong H. Jiang, Yun Liang 0001	POPA: Expressing High and Portable Performance across Spatial and Vector Architectures for Tensor Computations.	FPGA	2024	DBLP DOI BibTeX RDF
14	Sahand Kashani, Mahyar Emami, Keisuke Kamahori, Mohammad Sepehr Pourghannad, Ritik Raj, James R. Larus	A 475 MHz Manycore FPGA Accelerator for RTL Simulation.	FPGA	2024	DBLP DOI BibTeX RDF
14	Jinming Zhuang, Zhuoping Yang, Shixin Ji, Heng Huang, Alex K. Jones, Jingtong Hu, Yiyu Shi 0001, Peipei Zhou 0001	SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration.	FPGA	2024	DBLP DOI BibTeX RDF
14	Hassan Nassar, Philipp Machauer, Dennis R. E. Gnad, Lars Bauer, Mehdi B. Tahoori, Jörg Henkel	Covert-Hammer: Coordinating Power-Hammering on Multi-tenant FPGAs via Covert Channels.	FPGA	2024	DBLP DOI BibTeX RDF
14	Yiyue Jiang, Andrius Vaicaitis, John Dooley, Miriam Leeser	Efficient Neural Networks on the Edge with FPGAs by Optimizing an Adaptive Activation Function.	FPGA	2024	DBLP DOI BibTeX RDF
14	Martin Langhammer, George A. Constantinides	A Statically and Dynamically Scalable Soft GPGPU.	FPGA	2024	DBLP DOI BibTeX RDF
14	Andy Ray, Benjamin Devlin, Fu Yong Quah, Rahul Yesantharao	Hardcaml MSM: A High-Performance Split CPU-FPGA Multi-Scalar Multiplication Engine.	FPGA	2024	DBLP DOI BibTeX RDF
14	Yizhao Gao, Baoheng Zhang, Yuhao Ding, Hayden Kwok-Hay So	A Composable Dynamic Sparse Dataflow Architecture for Efficient Event-based Vision Processing on FPGA.	FPGA	2024	DBLP DOI BibTeX RDF
14	Mark Klaisoongnoen, Nick Brown 0002, Tim Dykes, Jessica R. Jones, Utz-Uwe Haus	Evaluating Versal AI Engines for Option Price Discovery in Market Risk Analysis.	FPGA	2024	DBLP DOI BibTeX RDF
14	Shengjun Xu, Wenlu Peng, Wenjin Huang, Qi Liu, Yihua Huang 0005	HR-GCN: An Efficient GCN Accelerator for Heterogeneous Graph Data and R-GCN Model.	FPGA	2024	DBLP DOI BibTeX RDF
14	Ayatallah Elakhras, Andrea Guerrieri, Lana Josipovic, Paolo Ienne	Survival of the Fastest: Enabling More Out-of-Order Execution in Dataflow Circuits.	FPGA	2024	DBLP DOI BibTeX RDF
14	Stéphane Pouget, Louis-Noël Pouchet, Jason Cong	Automatic Hardware Pragma Insertion in High-Level Synthesis: A Non-Linear Programming Approach.	FPGA	2024	DBLP DOI BibTeX RDF
14	Chunyou Su, Linfeng Du, Tingyuan Liang, Zhe Lin, Maolin Wang, Sharad Sinha, Wei Zhang 0012	GraFlex: Flexible Graph Processing on FPGAs through Customized Scalable Interconnection Network.	FPGA	2024	DBLP DOI BibTeX RDF
14	Ruifan Xu, Jin Luo, Yun Liang 0001	Hermes: Enhancing Extensibility in High-Level Synthesis through Multi-Level IRs.	FPGA	2024	DBLP DOI BibTeX RDF
14	Kai Qian, Zheng Liu, Yinqiu Liu, Haodong Lu 0001, Zexu Zhang, Ruiqiu Chen, Kun Wang 0005	AutoHammer: Breaking the Compilation Wall Between Deep Neural Network and Overlay-based FPGA Accelerator.	FPGA	2024	DBLP DOI BibTeX RDF
14	Daniel Gerlinghoff, Benjamin Chen Ming Choong, Rick Siow Mong Goh, Weng-Fai Wong, Tao Luo 0014	Table-Lookup MAC: Scalable Processing of Quantised Neural Networks in FPGA Soft Logic.	FPGA	2024	DBLP DOI BibTeX RDF
14	Andrea Guerrieri, Srijeet Guha, Lana Josipovic, Paolo Ienne	DynaRapid: From C to FPGA in a Few Seconds.	FPGA	2024	DBLP DOI BibTeX RDF
14	Zelin Wang, Guiyuan Zhu, Yunhai Liu, Yisong Chang, Ke Zhang 0017, Mingyu Chen 0001	XUNI: Virtual Machine Abstraction for Self-contained and Multi-tenant Cloud FPGAs.	FPGA	2024	DBLP DOI BibTeX RDF
14	Alireza Khataei, Kia Bazargan	CompressedLUT: An Open Source Tool for Lossless Compression of Lookup Tables for Function Evaluation and Beyond.	FPGA	2024	DBLP DOI BibTeX RDF
14	Shuo Ni, Xin Wei, Ning Zhang, He Chen	Algorithm-Hardware Co-Optimization and Deployment Method for Field-Programmable Gate-Array-Based Convolutional Neural Network Remote Sensing Image Processing.	Remote. Sens.	2023	DBLP DOI BibTeX RDF
14	Guiming Wu, Qianwen He, Jiali Jiang, Zhenxiang Zhang, Yunfeng Shi, Xin Long, Linquan Jiang, Shuangchen Li, Yuan Xie 0001, Changzheng Wei, Yuan Zhao, Ying Yan 0002, Hui Zhang 0002, Yinchao Zou	E-Booster: A Field-Programmable Gate Array-Based Accelerator for Secure Tree Boosting Using Additively Homomorphic Encryption.	IEEE Micro	2023	DBLP DOI BibTeX RDF
14	Atsutake Kosuge, Yao-Chung Hsu, Rei Sumikawa, Mototsugu Hamada, Tadahiro Kuroda, Tomoe Ishikawa	A 10.7-µJ/Frame 88% Accuracy CIFAR-10 Single-Chip Neuromorphic Field-Programmable Gate Array Processor Featuring Various Nonlinear Functions of Dendrites in the Human Cerebrum.	IEEE Micro	2023	DBLP DOI BibTeX RDF
14	Pankaj Singh, Rupali Singh	A sliced architecture using novel configurable logic modules in quantum dot cellular automata for application of field-programmable gate arrays.	J. Supercomput.	2023	DBLP DOI BibTeX RDF
14	Yusuke Matsuoka	Implementation of Various Chaotic Spiking Oscillators Based on Field Programmable Analog Array.	IEICE Trans. Fundam. Electron. Commun. Comput. Sci.	2023	DBLP DOI BibTeX RDF
14	Shaan Sengupta, Matthew L. Johnston	A SiPM-Based Gamma Spectrometer With Field-Programmable Energy Binning for Data-Efficient Isotope Analysis.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
14	Ionel Zagan, Vasile Gheorghita Gaitan	Soft-core processor integration based on different instruction set architectures and field programmable gate array custom datapath implementation.	PeerJ Comput. Sci.	2023	DBLP DOI BibTeX RDF
14	Sundarapandian Vaidyanathan, Khaled Benkouider, Brisbane Ovilla-Martinez, Esteban Tlelo-Cuautle, Aceng Sambas, P. Darwin	A new 4-D hyperchaotic two-scroll system with hidden attractor and its field-programmable gate array implementation.	Int. J. Circuit Theory Appl.	2023	DBLP DOI BibTeX RDF
14	Viswanadham Baby Koti Lakshmi Aruna, Chitra Ekambaram, Mididoddi Padmaja	Field programmable gate array implementation of an adaptive filtering based noise reduction and enhanced compression technique for healthcare applications.	Trans. Emerg. Telecommun. Technol.	2023	DBLP DOI BibTeX RDF
14	Hanrui Wang 0002, Bochen Tan, Pengyu Liu, Yilian Liu, Jiaqi Gu, Jason Cong, Song Han 0003	Q-Pilot: Field Programmable Quantum Array Compilation with Flying Ancillas.	CoRR	2023	DBLP DOI BibTeX RDF
14	Thomas Jagielski, Rajit Manohar, Jaijeet Roychowdhury	FPIM: Field-Programmable Ising Machines for Solving SAT.	CoRR	2023	DBLP DOI BibTeX RDF
14	Hanrui Wang 0002, Pengyu Liu, Bochen Tan, Yilian Liu, Jiaqi Gu, David Z. Pan, Jason Cong, Umut A. Acar, Song Han 0003	FPQA-C: A Compilation Framework for Field Programmable Qubit Array.	CoRR	2023	DBLP DOI BibTeX RDF
14	Paritosh Meihar, Rowtu Srinu, Sandip Lashkare, Ajay Kumar Singh, Halid Mulaosmanovic, Veeresh Deshpande, Stefan Dünkel, Sven Beyer, Udayan Ganguly	Ferroelectric MirrorBit-Integrated Field-Programmable Memory Array for TCAM, Storage, and In-Memory Computing Applications.	CoRR	2023	DBLP DOI BibTeX RDF
14	Daniel Bochen Tan, Dolev Bluvstein, Mikhail D. Lukin, Jason Cong	Compiling Quantum Circuits for Dynamically Field-Programmable Neutral Atoms Array Processors.	CoRR	2023	DBLP DOI BibTeX RDF
14	Frances Cleary, Witawas Srisa-an, David C. Henshall, Sasitharan Balasubramaniam	Dynamic Field Programmable Logic-Driven Soft Exosuit.	CoRR	2023	DBLP DOI BibTeX RDF
14	Saber Krim, Mohamed Faouzi Mimouni	Design and Xilinx Virtex-field-programmable gate array for hardware in the loop of sensorless second-order sliding mode control and model reference adaptive system-sliding mode observer for direct torque control of induction motor drive.	J. Syst. Control. Eng.	2023	DBLP DOI BibTeX RDF
14	Priyadarshini B. Indira, Reddy D. Krishna	Adaptive octopus deep transfer learning based epileptic seizure classification on field programmable gate arrays.	Evol. Syst.	2023	DBLP DOI BibTeX RDF
14	Marc Majoral, Carles Fernández-Prades, Javier Arribas	A Flexible System-on-Chip Field-Programmable Gate Array Architecture for Prototyping Experimental Global Navigation Satellite System Receivers.	Sensors	2023	DBLP DOI BibTeX RDF
14	M. N. Sharada Guptha, M. N. Eshwarappa	Optimized Deep Learning-Based Fully Resolution Convolution Neural Network for Breast Tumour Segmentation on Field Programmable Gate Array.	Comput. methods Biomech. Biomed. Eng. Imaging Vis.	2023	DBLP DOI BibTeX RDF
14	Silas Bartel, Matthias Korch	Generation of logic designs for efficiently solving ordinary differential equations on field programmable gate arrays.	Softw. Pract. Exp.	2023	DBLP DOI BibTeX RDF
14	Paolo Ienne, Zhiru Zhang (eds.)	Proceedings of the 2023 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2023, Monterey, CA, USA, February 12-14, 2023	FPGA	2023	DBLP DOI BibTeX RDF
14	Trevor C. Smith, Sergey Edward Lyshevski	Field-Programmable Gate Array Control of DC-DC Switching Regulators: Design and Implementation of Controllers.	ACC	2023	DBLP DOI BibTeX RDF
14	Nele Mentens, Leonel Sousa, Pedro Trancoso, Nikela Papadopoulou, Ioannis Sourdis (eds.)	33rd International Conference on Field-Programmable Logic and Applications, FPL 2023, Gothenburg, Sweden, September 4-8, 2023	FPL	2023	DBLP DOI BibTeX RDF
14		31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2023, Marina Del Rey, CA, USA, May 8-11, 2023	FCCM	2023	DBLP DOI BibTeX RDF
14		International Conference on Field Programmable Technology, ICFPT 2023, Yokohama, Japan, December 12-14, 2023	ICFPT	2023	DBLP DOI BibTeX RDF
14	Minoru Watanabe	Radiation-hardened triple-modular redundant field programmable gate array with a two-phase clock.	ISCAS	2023	DBLP DOI BibTeX RDF
14	T. P. Abdul Rahoof, Vivek Chaturvedi, Muhammad Shafique 0001	FastCaps: A Design Methodology for Accelerating Capsule Network on Field Programmable Gate Arrays.	IJCNN	2023	DBLP DOI BibTeX RDF
14	Saman P. Amarasinghe	Compiler Support for Structured Data.	FPGA	2023	DBLP DOI BibTeX RDF
14	Wole Jaiyeoba, Nima Elyasi, Changho Choi, Kevin Skadron	ACTS: A Near-Memory FPGA Graph Processing Framework.	FPGA	2023	DBLP DOI BibTeX RDF
14	Jiahui Xu, Emmet Murphy, Jordi Cortadella, Lana Josipovic	Eliminating Excessive Dynamism of Dataflow Circuits Using Model Checking.	FPGA	2023	DBLP DOI BibTeX RDF
14	Kan Shi, Shuoxiang Xu, Yuhan Diao, David Boland, Yungang Bao	ENCORE: Efficient Architecture Verification Framework with FPGA Acceleration.	FPGA	2023	DBLP DOI BibTeX RDF
14	Tim Oberschulte, Jakob Marten, Holger Blume	Fault Detection on Multi COTS FPGA Systems for Physics Experiments on the International Space Station.	FPGA	2023	DBLP DOI BibTeX RDF
14	Linus Y. Wong, Jialiang Zhang, Jing Jane Li	DONGLE: Direct FPGA-Orchestrated NVMe Storage for HLS.	FPGA	2023	DBLP DOI BibTeX RDF
14	Shashwat Shrivastava, Stefan Nikolic 0001, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic	Mitigating the Last-Mile Bottleneck: A Two-Step Approach For Faster Commercial FPGA Routing.	FPGA	2023	DBLP DOI BibTeX RDF
14	Michael Lo, Young-kyu Choi, Weikang Qiao, Mau-Chung Frank Chang, Jason Cong	HMLib: Efficient Data Transfer for HLS Using Host Memory.	FPGA	2023	DBLP DOI BibTeX RDF