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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3961 occurrences of 1777 keywords
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Results
Found 46124 publication records. Showing 46122 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Philippe Coussy, Emmanuel Casseau, Pierre Bomel, Adel Baganne, Eric Martin 0001 |
A formal method for hardware IP design and integration under I/O and timing constraints. |
ACM Trans. Embed. Comput. Syst. |
2006 |
DBLP DOI BibTeX RDF |
IP design and integration, communication interface unit, constrained synthesis, digital signal processing and multimedia applications, SoC |
19 | Qi Huang, Xiaoping Chen, Bingfeng Wang, Ronghai Cai, Kaiyu Qin |
The Concept of Computing on Chip (CoC) for Electric Power System Application. |
PARELEC |
2006 |
DBLP DOI BibTeX RDF |
CoC, VLSI, SOC, Power System, Transient Simulation |
19 | Jianjun Guo, Kui Dai, Zhiying Wang 0003 |
A Heterogeneous Multi-core Processor Architecture for High Performance Computing. |
Asia-Pacific Computer Systems Architecture Conference |
2006 |
DBLP DOI BibTeX RDF |
TTA, SoC, heterogeneous, multi-core |
19 | Thinh M. Le, Xiaohua Tian, B. L. Ho, J. Nankoo, Yong Lian 0001 |
System-on-Chip Design Methodology for a Statistical Coder. |
IEEE International Workshop on Rapid System Prototyping |
2006 |
DBLP DOI BibTeX RDF |
statistical coder, SoC, design methodology, CABAC |
19 | Sung Bum Pan, Daesung Moon, Kichul Kim, Yongwha Chung |
A VLSI Implementation of Minutiae Extraction for Secure Fingerprint Authentication. |
CIS |
2006 |
DBLP DOI BibTeX RDF |
fingerprint authentication, minutiae extraction, VLSI, SoC |
19 | Kuei-Chung Chang, Jih-Sheng Shen, Tien-Fu Chen |
Evaluation and design trade-offs between circuit-switched and packet-switched NOCs for application-specific SOCs. |
DAC |
2006 |
DBLP DOI BibTeX RDF |
application-specific designs, low-power, NOC, SOC |
19 | Takanori Kyogoku, Junpei Inoue, Hidenari Nakashima, Takumi Uezono, Kenichi Okada, Kazuya Masu |
Wire Length Distribution Model Considering Core Utilization for System on Chip. |
ISVLSI |
2005 |
DBLP DOI BibTeX RDF |
Wire Length Distribution, core utilization, layout-area allocation, SoC |
19 | Charlie Johnson, Jeff Welser |
Future processors: flexible and modular. |
CODES+ISSS |
2005 |
DBLP DOI BibTeX RDF |
multiprocessor, SoC, accelerators |
19 | Andrew Morton, Wayne M. Loucks |
A hardware/software kernel for system on chip designs. |
SAC |
2004 |
DBLP DOI BibTeX RDF |
operating systems, SoC, hardware/software codesign |
19 | Reiner W. Hartenstein |
The digital divide of computing. |
Conf. Computing Frontiers |
2004 |
DBLP DOI BibTeX RDF |
morphware, performance, SoC, reconfigurable computing |
19 | Adit D. Singh, Markus Seuring, Michael Gössel, Egor S. Sogomonyan |
Multimode scan: Test per clock BIST for IP cores. |
ACM Trans. Design Autom. Electr. Syst. |
2003 |
DBLP DOI BibTeX RDF |
SoC, BIST, scan, digital testing |
19 | Ki Won Lee |
Low power requirements for future digital life style. |
ISLPED |
2003 |
DBLP DOI BibTeX RDF |
digital life style, portable power sources, software architecture, components, SOC |
19 | Atsushi Sakai, Takashi Yamada, Yoshifumi Matsushita, Hiroto Yasuura |
Routing methodology for minimizing 1nterconnect energy dissipation. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
routing, SoC, analysis, crosstalk, energy dissipation |
19 | Sunjaya Djaja, Glenn H. Chapman, Desmond Y. H. Cheung, Yves Audet |
Implementation and Testing of Fault-Tolerant Photodiode-Based Active Pixel Sensor (APS). |
DFT |
2003 |
DBLP DOI BibTeX RDF |
photodiode APS, fault-tolerance, redundancy, SOC, CMOS image sensor, active pixel sensor |
19 | Ahmed Amine Jerraya, Sungjoo Yoo, Aimen Bouchhima, Gabriela Nicolescu |
Validation in a Component-Based Design Flow for Multicore SoCs. |
ISSS |
2002 |
DBLP DOI BibTeX RDF |
validation, SoC, abstraction levels, component-based design, cosimulation |
19 | Alex K. Jones, Debabrata Bagchi, Satrajit Pal, Xiaoyong Tang, Alok N. Choudhary, Prithviraj Banerjee |
PACT HDL: a C compiler targeting ASICs and FPGAs with power and performance optimizations. |
CASES |
2002 |
DBLP DOI BibTeX RDF |
FPGA, low-power, compiler, SoC, synthesis, pipelining, VHDL, IP, ASIC, high-performance, FSM, Verilog, HDL, levelization |
19 | Wu-Tung Cheng |
Current status and future trend on CAD tools for VLSI testing Wu-Tung Cheng. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
test logic, deep Sub-Micron technologies, scan-based ATPG, test application cost, test development, VLSI, CAD, logic testing, built-in self test, system on chip, SoC, automatic test pattern generation, automatic test pattern generation, ATPG, BIST, VLSI design, integrated circuit design, circuit CAD, VLSI testing, embedded memories, test quality, integrated circuit economics |
18 | Ahsan Shabbir, Sander Stuijk, Akash Kumar 0001, Bart D. Theelen, Bart Mesman, Henk Corporaal |
A predictable communication assist. |
Conf. Computing Frontiers |
2010 |
DBLP DOI BibTeX RDF |
fpga's, communication, predictable, dma, ca, mp-soc |
18 | Yong Chen 0003, Zhengzhi Wang |
A Neural Network Architecture for Perceptual Grouping, Attention Modulation and Boundary-Surface Interaction. |
ISICA |
2009 |
DBLP DOI BibTeX RDF |
attention modulation, boundary-surface interaction, SOC filtering, complementary computing, perceptual grouping |
18 | Pradip A. Thaker |
Holistic verification: myth or magic bullet? |
DAC |
2009 |
DBLP DOI BibTeX RDF |
SoC verification, mixed-signal verification, power management verification, emulation |
18 | Manuel A. Mosquera, Ignacio García-Jurado, M. Gloria Fiestras-Janeiro |
A note on coalitional manipulation and centralized inventory management. |
Ann. Oper. Res. |
2008 |
DBLP DOI BibTeX RDF |
Centralized multi-agent inventory cost situations, Inventory games, Coalitional manipulation, SOC-rule |
18 | Hans G. Kerkhoff, Jarkko J. M. Huijts |
Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications. |
DELTA |
2008 |
DBLP DOI BibTeX RDF |
reconfigurable multi-processor-cores SoC, embedded system test, dependable SoCs, ATPG, Design-for-Test, self-repair |
18 | Zhen Zhang, Alain Greiner, Sami Taktak |
A reconfigurable routing algorithm for a fault-tolerant 2D-Mesh Network-on-Chip. |
DAC |
2008 |
DBLP DOI BibTeX RDF |
2D-Mesh NoC, DSPIN, MP2-SoC, fault-tolerant, reconfiguration, routing algorithm |
18 | Mike P. Papazoglou, Paolo Traverso, Schahram Dustdar, Frank Leymann |
Service-Oriented Computing: State of the Art and Research Challenges. |
Computer |
2007 |
DBLP DOI BibTeX RDF |
SOC paradigm, Web services, service orientation, enterprise services |
18 | Antoine Fraboulet, Tanguy Risset |
Master Interface for On-chip Hardware Accelerator Burst Communications. |
J. VLSI Signal Process. |
2007 |
DBLP DOI BibTeX RDF |
SoC simulation, system on chip, high level synthesis, interface generation |
18 | Grant Martin |
Making a List...Checking it Twice. |
IEEE Des. Test Comput. |
2007 |
DBLP DOI BibTeX RDF |
methodology manual, low power, SoC design, IC design |
18 | Kwang-Ting (Tim) Cheng |
Cocktail approach to functional verification. |
IEEE Des. Test Comput. |
2007 |
DBLP DOI BibTeX RDF |
validation, functional verification, multiprocessor SoC, SiP, BISR |
18 | Letícia Maria Veiras Bolzani, Edgar E. Sánchez, Matteo Sonza Reorda |
A software-based methodology for the generation of peripheral test sets based on high-level descriptions. |
SBCCI |
2007 |
DBLP DOI BibTeX RDF |
RT-level test metrics, code coverage metrics, gate-level test metrics, test block, fault coverage, SoC testing |
18 | Jaehoon Song, Hyunbean Yi, Juhee Han, Sungju Park |
An Efficient Link Controller for Test Access to IP Core-Based Embedded System Chips. |
Asia-Pacific Computer Systems Architecture Conference |
2007 |
DBLP DOI BibTeX RDF |
Embedded System, Wrapper, Boundary Scan, Test Access Mechanism, SoC Testing |
18 | Ali El Kateeb, Lubna Al Azzawi |
Low Cost HIV Testing System for Tele-Health Applications. |
AINA Workshops (2) |
2007 |
DBLP DOI BibTeX RDF |
HIV kits, HIV screening, Field programmable gate array (FPGA), System-on-chip (SOC) |
18 | Paolo Bernardi, Letícia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas 0001, Massimo Violante |
A New Hybrid Fault Detection Technique for Systems-on-a-Chip. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
SoC dependability, transient fault detection, infrastructure IP |
18 | Marius Bonaciu, Aimen Bouchhima, Mohamed-Wassim Youssef, Xi Chen, Wander O. Cesário, Ahmed Amine Jerraya |
High-level architecture exploration for MPEG4 encoder with custom parameters. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
multiprocessors SOC architecture, customization, video encoder, architecture exploration, MPEG4 |
18 | Sang-Hyun Park, Hoon Choi, Sang-Han Lee, Taejoo Chang |
The High-Speed Packet Cipher System Suitable for Small Sized Data. |
IWSEC |
2006 |
DBLP DOI BibTeX RDF |
Packet Cipher, SoC(System on Chip), Cryptographic module, Security API |
18 | Enrico Formenti, Benoît Masson, Theophilos Pisokas |
On Symmetric Sandpiles. |
ACRI |
2006 |
DBLP DOI BibTeX RDF |
SOC systems, sandpiles, fixed point dynamics, discrete dynamical systems |
18 | Yinhe Han 0001, Xiaowei Li 0001, Huawei Li 0001, Anshuman Chandra |
Test Resource Partitioning Based on Efficient Response Compaction for Test Time and Tester Channels Reduction. |
J. Comput. Sci. Technol. |
2005 |
DBLP DOI BibTeX RDF |
test resource partitioning (TRP), error cancellation, System-on-a-Chip (SoC), diagnose, response compaction |
18 | Hoonmo Yang, Moonkey Lee |
Embedded Processor Validation Environment Using a Cycle-Accurate Retargetable Instruction-Set Simulator. |
J. Supercomput. |
2005 |
DBLP DOI BibTeX RDF |
cycle-accurate, validation, system-on-chip (SoC), architecture description language (ADL), retargetable, instruction-set simulator |
18 | |
DATC Newsletter. |
IEEE Des. Test Comput. |
2005 |
DBLP DOI BibTeX RDF |
disruptive technology, sustaining technology, digital synthesis, EDA, SoC design, Design Automation Conference |
18 | Julien Denoulet, Ghilès Mostafaoui, Lionel Lacassagne, Alain Mérigot |
Implementing Motion Markov Detection on General Purpose Processor and Associative Mesh. |
CAMP |
2005 |
DBLP DOI BibTeX RDF |
Vision-SoC, associative nets model, Markov Random Field, SIMD, motion detection |
18 | John Wei, Chris Rowen |
Implementing low-power configurable processors: practical options and tradeoffs. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
PVT (process, voltage, temperature), configurable embedded processor, dynamic power efficiency, scaled VDD, low-power, leakage power, SOC (system on chip), dynamic power |
18 | Philippe Royannez, Hugh Mair, Franck Dahan, Mike Wagner, Mark Streeter, Laurent Bouetel, Joel Blasquez, H. Clasen, G. Semino, Julie Dong, D. Scott, B. Pitts, Claudine Raibaut, Uming Ko |
A design platform for 90-nm leakage reduction techniques. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
leakage power management, wireless application processor, SoC design |
18 | Érika F. Cota, Luigi Carro, Marcelo Lubaszewski, Alex Orailoglu |
Searching for Global Test Costs Optimization in Core-Based Systems. |
J. Electron. Test. |
2004 |
DBLP DOI BibTeX RDF |
design space exploration, design for test, SOC testing, embedded cores testing |
18 | Érika F. Cota, Luigi Carro, Marcelo Lubaszewski |
Reusing an on-chip network for the test of core-based systems. |
ACM Trans. Design Autom. Electr. Syst. |
2004 |
DBLP DOI BibTeX RDF |
TAM and wrapper design, test reuse, network-on-chip, test scheduling, SoC test, Core-based test |
18 | Antoine Fraboulet, Tanguy Risset |
Efficient On-Chip Communications for Data-Flow IPs. |
ASAP |
2004 |
DBLP DOI BibTeX RDF |
SoC simulation, system on chip, High level synthesis, interface generation |
18 | Christian Berthet |
Going mobile: the next horizon for multi-million gate designs in the semi-conductor industry. |
DAC |
2002 |
DBLP DOI BibTeX RDF |
SoC design, HW/SW co-design |
18 | Tek Jau Tan, Chung-Len Lee |
Socillator Test: A Delay Test Scheme for Embedded ICs in the Boundary-Scan Environment. |
VTS |
2001 |
DBLP DOI BibTeX RDF |
Oscillation test, Delay testing, System test, SOC testing, Embedded testing |
18 | Kuen-Jong Lee, Cheng-I Huang |
A hierarchical test control architecture for core based design. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
hierarchical test control architecture, SOC design, IEEE P1500 Working Group, test standard, IEEE 1149.1 cores, parallel testing capabilities, hierarchical test control mechanism, deeply embedded cores, hierarchical test access, integrated circuit testing, design for testability, automatic testing, application specific integrated circuits, IEEE standards, test architecture, core based design |
17 | Cheng-Hong Li, Luca P. Carloni |
Leveraging Local Intracore Information to Increase Global Performance in Block-Based Design of Systems-on-Chip. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Fei Zhang 0002, Guangjun Liu, Lijin Fang |
Battery state estimation using Unscented Kalman Filter. |
ICRA |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Yu-Wei Yang, Katherine Shu-Min Li |
Temperature-aware dynamic frequency and voltage scaling for reliability and yield enhancement. |
ASP-DAC |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Andreas Hansson 0001, Kees Goossens |
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models. |
CODES+ISSS |
2009 |
DBLP DOI BibTeX RDF |
system on chip, network on chip, programming model, protocol stack |
17 | Ali Ahmadinia, Tughrul Arslan, Hernando Fernandez-Canque |
Optimization of Reconfigurable Multi-core SOCs for Multi-standard Applications. |
KES (2) |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Youssef Benabboud, Alberto Bosio, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel, Laroussi Bouzaida, Isabelle Izaute |
A case study on logic diagnosis for System-on-Chip. |
ISQED |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Sören Sonntag, Wenjian Wang |
Area and power consumption estimations at system level with SystemQ 2.0. |
SimuTools |
2009 |
DBLP DOI BibTeX RDF |
SystemQ, area and power estimation, modeling, synthesis, electronic system level |
17 | Tom Borgstrom, Eshel Haritan, Ron Wilson, David Abada, Andrew Dauman, Ramesh Chandra, Olivier Mielo, Chuck Cruse, Achim Nohl |
System prototypes: virtual, hardware or hybrid? |
DAC |
2009 |
DBLP DOI BibTeX RDF |
SystemC TLM, hardware/software co-verification, rapid prototype, embedded software, virtual prototype, virtual platform, system validation, FPGA prototype, system prototype |
17 | Mydhili K. Nair, Shishir M. Kakaraddi, Keerthi M. Ramanarayan, V. Gopalakrishna |
Agent with Rule Engine: The "Glue' for Web Service Oriented Computing Applied to Network Management. |
IEEE SCC |
2009 |
DBLP DOI BibTeX RDF |
|
17 | Ozgur Sinanoglu |
Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations. |
J. Electron. Test. |
2008 |
DBLP DOI BibTeX RDF |
Test power reduction, Scan power reduction, Serial transformations, Scan chain modification, Design for testability, Core-based testing |
17 | Iyad Al Khatib, Francesco Poletti, Davide Bertozzi, Luca Benini, Mohamed Bechara, Hasan Khalifeh, Axel Jantsch, Rustam Nabiev |
A multiprocessor system-on-chip for real-time biomedical monitoring and analysis: ECG prototype architectural design space exploration. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
hardware space exploration, embedded system design, Multiprocessor system-on-chip, real time analysis, electrocardiogram algorithms |
17 | Milos Drutarovský, Michal Varchola |
Cryptographic System on a Chip based on Actel ARM7 Soft-Core with Embedded True Random Number Generator. |
DDECS |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Antonio Deledda, Claudio Mucci, Arseni Vitkovski, Philippe Bonnot 0001, Arnaud Grasset, Philippe Millet, Matthias Kühnle, Florian Ries, Michael Hübner 0001, Jürgen Becker 0001, Massimo Coppola, Lorenzo Pieralisi, Riccardo Locatelli, Giuseppe Maruccia, Fabio Campi, Tommaso DeMarco |
Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor. |
DATE |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Hai Yu, Fan Xiaoya |
Mitigating Soft Errors in System-on-Chip Design. |
ICYCS |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Roman Belter, Rolf Kluge |
Towards Distributed Management of Service-Oriented Computing Infrastructures. |
COMPSAC |
2008 |
DBLP DOI BibTeX RDF |
Management infrastructure, Service management, Service lifecycle |
17 | Imran Rafiq Quadri, Samy Meftali, Jean-Luc Dekeyser |
MARTE based modeling approach for Partial Dynamic Reconfigurable FPGAs. |
ESTIMedia |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Adedoyin Maria Thompson, Bernd Porr, Christoph Kolodziejski, Florentin Wörgötter |
Second Order Conditioning in the Sub-cortical Nuclei of the Limbic System. |
SAB |
2008 |
DBLP DOI BibTeX RDF |
Dopamine, three factor ISO Learning, Conditioning, Hebbian learning |
17 | Jindong Liu, Harry R. Erwin, Stefan Wermter, Mahmoud Elsaid |
A Biologically Inspired Spiking Neural Network for Sound Localisation by the Inferior Colliculus. |
ICANN (2) |
2008 |
DBLP DOI BibTeX RDF |
|
17 | Rupsa Chakraborty, Dipanwita Roy Chowdhury |
coreBIST: A Cellular Automata Based Core for Self Testing System-on-Chips. |
ACRI |
2008 |
DBLP DOI BibTeX RDF |
Response-Analyzer, Built-in self-test, System-on-Chip, Cellular Automata, Test-Pattern-Generator |
17 | Roman Belter |
Towards a Service Management System in Virtualized Infrastructures. |
IEEE SCC (2) |
2008 |
DBLP DOI BibTeX RDF |
Management infrastructure, Web service, Service-oriented Computing, Service Management, Service lifecycle |
17 | Daniel Singer |
Linearly ordered semigroups for fuzzy set theory. |
Ann. Math. Artif. Intell. |
2007 |
DBLP DOI BibTeX RDF |
Mathematics Subject Classifications (2000) 03E04, 03E72, 03G25, 06B30, 22A15, 18B40, 03G10, 06F05, 06B35 |
17 | Donghyun Kim, Kwanho Kim, Joo-Young Kim 0001, Seungjin Lee 0001, Hoi-Jun Yoo |
Solutions for Real Chip Implementation Issues of NoC and Their Application to Memory-Centric NoC. |
NOCS |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Dam Sunwoo, Hassan Al-Sukhni, Jim Holt, Derek Chiou |
Early Models for System-Level Power Estimation. |
MTV |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Andreas Hansson 0001, Martijn Coenen, Kees Goossens |
Undisrupted quality-of-service during reconfiguration of multiple applications in networks on chip. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Ozgur Sinanoglu, Tsvetomir Petrov |
A non-intrusive isolation approach for soft cores. |
DATE |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Fawnizu Azmadi Hussin, Tomokazu Yoneda, Alex Orailoglu, Hideo Fujiwara |
Core-Based Testing of Multiprocessor System-on-Chips Utilizing Hierarchical Functional Buses. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Bradley R. Quinton, Steven J. E. Wilton |
Embedded Programmable Logic Core Enhancements for System Bus Interfaces. |
FPL |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Andreas Hansson 0001, Martijn Coenen, Kees Goossens |
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip. |
CODES+ISSS |
2007 |
DBLP DOI BibTeX RDF |
quality-of-service, system-on-chip, network-on-chip, time-division-multiplexing |
17 | Grzegorz M. Wójcik, Wieslaw A. Kaminski, Piotr Matejanka |
Self-organised Criticality in a Model of the Rat Somatosensory Cortex. |
PaCT |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Soo Ho Chang, Hyun Jung La, Jeong Seop Bae, Won Young Jeon, Soo Dong Kim |
Design of a Dynamic Composition Handler for ESB-based Services. |
ICEBE |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Mikko Raatikainen, Katrine Jokinen, Paavo Kotinurmi, Varvana Myllärniemi |
Service Composition Using Product Configuration Technology. |
ICEBE |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Chih-Da Chien, Chih-Wei Wang, Chiun-Chau Lin, Tien-Wei Hsieh, Yuan-Hwa Chu, Jiun-In Guo |
A Low Latency Memory Controller for Video Coding Systems. |
ICME |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Sam Chung, Joseph Byung Chul An, Sergio Davalos |
Service-Oriented Software Reengineering: SoSR. |
HICSS |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Matthieu Tuna, Mounir Benabdenbi, Alain Greiner |
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester. |
VTS |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Dan Luo 0001, Longbing Cao, Jiarui Ni, Li Liu 0033 |
Building Agent Service Oriented Multi-Agent Systems. |
KES-AMSTA |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Jacob A. Abraham, Daniel G. Saab |
Tutorial T4A: Formal Verification Techniques and Tools for Complex Designs. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Nikhil Bansal 0003, Kanishka Lahiri, Anand Raghunathan |
Automatic Power Modeling of Infrastructure IP for System-on-Chip Power Analysis. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Puranjoy Bhattacharya |
Tutorial IND1A: NeXperia - A Versatile Configurable Platform for Home and Mobile Computing. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Subhomoy Chattopadhyay, Rakesh Patel |
Tutorial T3: Low Power Design Techniques for Nanometer Design Processes - 65nm and Smaller. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir |
STEFAL: A System Level Temperature- and Floorplan-Aware Leakage Power Estimator for SoCs. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Sandeep Jain, Jais Abraham, Srinivas Kumar Vooka, Sumant Kale, Amit Dutta, Rubin A. Parekhji |
Enhancements in Deterministic BIST Implementations for Improving Test of Complex SOCs. |
VLSI Design |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Francine Bacchini, Daniel D. Gajski, Laurent Maillet-Contoz, Haruhisa Kashiwagi, Jack Donovan, Tommi Mäkeläinen, Jack Greenbaum, Rishiyur S. Nikhil |
TLM: Crossing Over From Buzz To Adoption. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Fabricio B. Goncalves, Carlo E. T. Oliveira, Izalmo Silva, Luiz G. L. Moura, Felipe Maia Galvão França |
A Software Architecture for the Provisioning of Mobile Services in Peer-to-Peer Environments. |
ICIW |
2007 |
DBLP DOI BibTeX RDF |
|
17 | Andrew B. T. Hopkins, Klaus D. McDonald-Maier |
Debug Support Strategy for Systems-on-Chips with Multiple Processor Cores. |
IEEE Trans. Computers |
2006 |
DBLP DOI BibTeX RDF |
multiprocessor systems, System architectures, real-time and embedded systems, debugging aids, integration and modeling |
17 | Noah Bamford, Rekha Bangalore, Eric Chapman, Hector Chavez, Rajeev Dasari, Yinfang Lin, Edgar Jimenez |
Challenges in System on Chip Verification. |
MTV |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Jianmin Zhang, Ming Yan 0003, Sikun Li |
Debug Support for Scalable System-on-Chip. |
MTV |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Xiaoyu Ruan, Rajendra S. Katti |
An Efficient Data-Independent Technique for Compressing Test Vectors in Systems-on-a-Chip. |
ISVLSI |
2006 |
DBLP DOI BibTeX RDF |
|
17 | D. Shaver |
Next generation architectures can dramatically reduce the 4G deployment cycle. |
DATE |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Muhammad Waseem, Ludovic Apvrille, Rabéa Ameur-Boulifa, Sophie Coudert, Renaud Pacalet |
Abstract Application Modeling for System Design Space Exploration. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Ari Kulmala, Timo D. Hämäläinen, Marko Hännikäinen |
Comparison of GALS and Synchronous Architectures with MPEG-4 Video Encoder on Multiprocessor System-on-Chip FPGA. |
DSD |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Mrinmoy Ghosh, Emre Özer 0001, Stuart Biles, Hsien-Hsin S. Lee |
Efficient System-on-Chip Energy Management with a Segmented Bloom Filter. |
ARCS |
2006 |
DBLP DOI BibTeX RDF |
|
17 | Masafumi Onouchi, Tetsuya Yamada, Kimihiro Morikawa, Isamu Mochizuki, Hidetoshi Sekine |
A system-level power-estimation methodology based on IP-level modeling, power-level adjustment, and power accumulation. |
ASP-DAC |
2006 |
DBLP DOI BibTeX RDF |
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17 | Balasubramanian Sethuraman |
Novel Methodologies for Performance & Power Efficient Reconfigurable Networks-on-Chip. |
FPL |
2006 |
DBLP DOI BibTeX RDF |
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17 | Fabio Campi, Paolo Zoffoli, Claudio Mucci, Massimo Bocchi, Antonio Deledda, Mario de Dominicis, Arseni Vitkovski |
A stream register file unit for reconfigurable processors. |
ISCAS |
2006 |
DBLP DOI BibTeX RDF |
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