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GrowBag graphs for keyword ? (Num. hits/coverage)
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Results
Found 3882 publication records. Showing 3880 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
11 | Sangsu Jeong, Jeongwoo Park, Dongsuk Jeon |
A 28nm 1.644TFLOPS/W Floating-Point Computation SRAM Macro with Variable Precision for Deep Neural Network Inference and Training. |
ESSCIRC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Manoj Sharma, Apar Gupta, Vishal Goyal |
SRAM Design Issues and Effective Panacea at Different CMOS Technology Nodes. |
FRUCT |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Sangwoo Jung, Jaehyun Lee, Huiseong Noh, Jong-Hyeok Yoon, Jaeha Kung |
DualPIM: A Dual-Precision and Low-Power CNN Inference Engine Using SRAM- and eDRAM-based Processing-in-Memory Arrays. |
AICAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Xiaomeng Wang, Xuejiao Liu, Xianghong Hu, Xiaopeng Zhong, Xizi Chen, Yu Liu 0007, Patrick Kong, Fengshi Tian, Chi-Ying Tsui |
TAC-RAM: A 65nm 4Kb SRAM Computing-in-Memory Design with 57.55 TOPS/W supporting Multibit Matrix-Vector Multiplication for Binarized Neural Network. |
AICAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Belal Iqbal, Anuj Grover, Harsh Rawat |
A Process and Data Variations Tolerant Capacitive Coupled 10T1C SRAM for In-Memory Compute (IMC) in Deep Neural Network Accelerators. |
AICAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Hyunchul Park, Kyeongho Lee, Jongsun Park 0001 |
A 10T SRAM Compute-In-Memory Macro with Analog MAC Operation and Time Domain Conversion. |
AICAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Chia-Yu Hsieh, Shih-Ting Lin, Zhaofang Li, Chih-Cheng Lu, Meng-Fan Chang, Kea-Tiong Tang |
MARSv2: Multicore and Programmable Reconstruction Architecture SRAM CIM-Based Accelerator with Lightweight Network. |
AICAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Rajiv V. Joshi, John Timmerwilke, Kevin Tien, Mark Yeck, Sudipto Chakraborty |
A 0.31V Vmin Cryogenic SRAM in 14 nm FinFET for Quantum Computing. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Nail Etkin Can Akkaya, Gary Chan, Hung-Jen Liao, Yih Wang, Jonathan Chang |
A 135.6Tbps/W 2R2W SRAM with 12T Logic Bit-cell with Vmin Down to 335mV Targeted for Machine-Learning Applications in 6nm FinFET CMOS Technology. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Hechen Wang, Renzhi Liu, Richard Dorrance, Deepak Dasalukunte, Xiaosen Liu, Dan Lake, Brent R. Carlton, May Wu |
A 32.2 TOPS/W SRAM Compute-in-Memory Macro Employing a Linear 8-bit C-2C Ladder for Charge Domain Computation in 22nm for Edge Inference. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Chia-Fu Lee, Cheng-Han Lu, Cheng-En Lee, Haruki Mori, Hidehiro Fujiwara, Yi-Chun Shih, Tan-Li Chou, Yu-Der Chih, Tsung-Yung Jonathan Chang |
A 12nm 121-TOPS/W 41.6-TOPS/mm2 All Digital Full Precision SRAM-based Compute-in-Memory with Configurable Bit-width For AI Edge Applications. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Daniel H. Morris, Huichu Liu, Tony F. Wu, Huseyin Ekin Sumbul, Elnaz Ansari, Alexandre Barachant, Jonathan Reid, Edith Beigné |
Co-Optimization of SRAM Circuits with Sequential Access Patterns in a 7nm SoC Achieving 58% Memory Energy Reduction for AR Applications. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Inhak Lee, Dongwook Seo, Yunrong Li, Mijoung Kim, Sangyeop Baeck |
4nm Voltage Auto-Tracking SRAM Pulse Generator with Fully RC Optimized Row Auto-Tracking Write Assist Circuits. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Yusung Kim 0002, Clifford Ong, Anandkumar Mahadevan Pillai, Harish Jagadeesh, Gwanghyeon Baek, Iqbal Rajwani, Zheng Guo, Eric Karl |
Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Keonhee Cho, Giseok Kim, Ji Sang Oh, Ki-Ryong Kim, Changsu Sim, Younmee Bae, Mijung Kim, Sangyeop Baeck, Taejoong Song, Seong-Ook Jung |
A 14-nm Low Voltage SRAM with Charge-Recycling and Charge Self-Saving Techniques for Low-Power Applications. |
VLSI Technology and Circuits |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Julen Gomez-Cornejo, Igor Villalta, Itxaso Aranzabal, Iraide Lopez, Aitzol Zuloaga |
Data content scrubbing approach for SRAM based FPGA designs. |
ISIE |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Jingyao Zhang 0002, Elaheh Sadredini |
Inhale: Enabling High-Performance and Energy-Efficient In-SRAM Cryptographic Hash for IoT. |
ICCAD |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Kyeongho Lee, Joonhyung Kim, Jongsun Park 0001 |
Low-Cost 7T-SRAM Compute-in-Memory Design Based on Bit-Line Charge-Sharing Based Analog-to-Digital Conversion. |
ICCAD |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Kota Shiba, Mitsuji Okada, Atsutake Kosuge, Mototsugu Hamada, Tadahiro Kuroda |
Polyomino: A 3D-SRAM-Centric Architecture for Randomly Pruned Matrix Multiplication with Simple Rearrangement Algorithm and x0.37 Compression Format. |
NEWCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Zhiyu Chen 0003, Qing Jin, Zhanghao Yu, Yanzhi Wang, Kaiyuan Yang 0001 |
DCT-RAM: A Driver-Free Process-In-Memory 8T SRAM Macro with Multi-Bit Charge-Domain Computation and Time-Domain Quantization. |
CICC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | R. Mathur, M. Kumar, Vivek Asthana, S. Aggarwal, S. Gupta, D. Wanjul, A. Baradia, S. Thota, P. Jain, B. Zheng, A. Cubeta, S. Thyagarajan, A. Chen, Y. K. Chong |
5GHz SRAM for High-Performance Compute Platform in 5nm CMOS. |
CICC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Avishek Biswas, Hetul Sanghvi, Mahesh Mehendale, G. Preet |
An area-efficient 6T-SRAM based Compute-In-Memory architecture with reconfigurable SAR ADCs for energy-efficient deep neural networks in edge ML applications. |
CICC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Edward Jongyoon Choi, Injun Choi, Chanhee Jeon, Gichan Yun, Donghyeon Yi, Sohmyung Ha, Ik-Joon Chang, Minkyu Je |
A 133.6TOPS/W Compute-In-Memory SRAM Macro with Fully Parallel One-Step Multi-Bit Computation. |
CICC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Bo Zhang, Jyotishman Saikia, Jian Meng, Dewei Wang, Soonwan Kwon, Sungmeen Myung, Hyunsoo Kim, Sang Joon Kim, Jae-sun Seo, Mingoo Seok |
A 177 TOPS/W, Capacitor-based In-Memory Computing SRAM Macro with Stepwise-Charging/Discharging DACs and Sparsity-Optimized Bitcells for 4-Bit Deep Convolutional Neural Networks. |
CICC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | A. Philippe, Lorenzo Ciampolini, M. Gerbaud, M. Ramirez-Corrales, Valentin Egloff, Bastien Giraud, Jean-Philippe Noël |
An Automated Design Methodology for Computational SRAM Dedicated to Highly Data-Centric Applications: Invited Paper. |
SLIP |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Bonan Yan, Jeng-Long Hsu, Pang-Cheng Yu, Chia-Chi Lee, Yaojun Zhang, Wenshuo Yue, Guoqiang Mei, Yuchao Yang, Yue Yang, Hai Li 0001, Yiran Chen 0001, Ru Huang |
A 1.041-Mb/mm2 27.38-TOPS/W Signed-INT8 Dynamic-Logic-Based ADC-less SRAM Compute-in-Memory Macro in 28nm with Reconfigurable Bitwise Operation for AI and Embedded Applications. |
ISSCC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Muya Chang, Samuel D. Spetalnick, Brian Crafton, Win-San Khwa, Yu-Der Chih, Meng-Fan Chang, Arijit Raychowdhury |
A 40nm 60.64TOPS/W ECC-Capable Compute-in-Memory/Digital 2.25MB/768KB RRAM/SRAM System with Embedded Cortex M3 Microprocessor for Edge Recommendation Systems. |
ISSCC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Ping-Chun Wu, Jian-Wei Su, Yen-Lin Chung, Li-Yang Hong, Jin-Sheng Ren, Fu-Chun Chang, Yuan Wu 0009, Ho-Yu Chen, Chen-Hsun Lin, Hsu-Ming Hsiao, Sih-Han Li, Shyh-Shyuan Sheu, Shih-Chieh Chang, Wei-Chung Lo, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chih-I Wu, Meng-Fan Chang |
A 28nm 1Mb Time-Domain Computing-in-Memory 6T-SRAM Macro with a 6.6ns Latency, 1241GOPS and 37.01TOPS/W for 8b-MAC Operations for Edge-AI Devices. |
ISSCC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Yihan Zhang 0002, Chang Xue, Xiao Wang, Tianyi Liu, Jihang Gao, Peiyu Chen, Jinguang Liu, Linan Sun, Linxiao Shen, Jiayoon Ru, Le Ye, Ru Huang |
Single-Mode CMOS 6T-SRAM Macros With Keeper-Loading-Free Peripherals and Row-Separate Dynamic Body Bias Achieving 2.53fW/bit Leakage for AIoT Sensing Platforms. |
ISSCC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Joonhyung Kim, Kyeongho Lee, Jongsun Park 0001 |
A Charge Domain P-8T SRAM Compute-In-Memory with Low-Cost DAC/ADC Operation for 4-bit Input Processing. |
ISLPED |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Jingyao Zhang 0002, Hoda Naghibijouybari, Elaheh Sadredini |
Sealer: In-SRAM AES for High-Performance and Low-Overhead Memory Encryption. |
ISLPED |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Pramod Kumar Bharti, Joycee Mekie |
RHSCC-16T: Radiation Hardened Sextuple Cross Coupled Robust SRAM Design for Radiation Prone Environments. |
ICCD |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Nanbing Pan, Xiaoxin Cui, Xin Qiao, Kanglin Xiao, Qingyu Guo, Yuan Wang 0001 |
A 28nm 64Kb SRAM based Inference-Training Tri-Mode Computing-in-Memory Macro. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Shu-Hung Kuo, Tian-Sheuan Chang |
PSCNN: A 885.86 TOPS/W Programmable SRAM-based Computing-In-Memory Processor for Keyword Spotting. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Pramod Kumar Bharti, Saurabh Jain, Kamlesh R. Pillai, Sagar Varma Sayyaparaju, Gurpreet S. Kalsi, Joycee Mekie, Sreenivas Subramoney |
Compute-In-Memory Using 6T SRAM for a Wide Variety of Workloads. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Kanglin Xiao, Xiaoxin Cui, Xin Qiao, Nanbing Pan, Xin'an Wang, Yuan Wang 0001 |
A Computing-in-Memory SRAM Macro Based on Fully-Capacitive-Coupling With Hierarchical Capacity Attenuator for 4-b MAC Operation. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Óscar Pereira-Rial, Daniel García-Lesta, Víctor M. Brea 0001, Paula López 0001, Diego Cabello |
Design of a 5-bit Signed SRAM-based In-Memory Computing Cell for Deep Learning Models. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Dinesh Kushwaha, Aditya Sharma, Neha Gupta, Ritik Raj, Ashish Joshi, Jwalant Mishra, Rajat Kohli, Sandeep Miryala, Rajiv V. Joshi, Sudeb Dasgupta, Anand Bulusu |
A 65nm Compute-In-Memory 7T SRAM Macro Supporting 4-bit Multiply and Accumulate Operation by Employing Charge Sharing. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Jianfeng Wang, Nuo Xiu, Juejian Wu, Yiming Chen, Yanan Sun 0003, Huazhong Yang, Vijaykrishnan Narayanan, Sumitha George, Xueqing Li |
An 8T/Cell FeFET-Based Nonvolatile SRAM with Improved Density and Sub-fJ Backup and Restore Energy. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Bo Wang, Chen Xue, Han Liu, Xiang Li, Anran Yin, Zhongyuan Feng, Yuyao Kong, Tianzhu Xiong, Haiming Hsu, Yongliang Zhou, An Guo, Yufei Wang, Jun Yang 0006, Xin Si |
SNNIM: A 10T-SRAM based Spiking-Neural-Network-In-Memory architecture with capacitance computation. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Yuzong Chen, Junjie Mu, Hyunjoon Kim, Lu Lu 0013, Tony Tae-Hyoung Kim |
A Reconfigurable 8T SRAM Macro for Bit-Parallel Searching and Computing In-Memory. |
ISCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Shiva Reddy, Ralph Gerard B. Sangalang, Chua-Chin Wang |
Sub-0.2 pJ/Access Schmitt Trigger Based 1-kb 8T SRAM Implemented Using 40-nm CMOS Process. |
ICICDT |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Víctor H. Champac, Hector Villacorta, Roberto Gómez-Fuentes, Fabian Vargas 0001, Jaume Segura 0001 |
Failure Probability due to Radiation-induced Effects in FinFET SRAM Cells under Process Variations. |
LATS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Aibin Yan, Zhihui He, Jing Xiang, Jie Cui 0004, Yong Zhou, Zhengfeng Huang, Patrick Girard 0001, Xiaoqing Wen |
Two 0.8 V, Highly Reliable RHBD 10T and 12T SRAM Cells for Aerospace Applications. |
ACM Great Lakes Symposium on VLSI |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Wanqian Li, Yinhe Han 0001, Xiaoming Chen 0003 |
Energy-Efficient In-SRAM Accumulation for CMOS-based CNN Accelerators. |
ACM Great Lakes Symposium on VLSI |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Semiu A. Olowogemo, Hao Qiu, Bor-Tyng Lin, William H. Robinson, Daniel B. Limbrick |
Model-Based Analysis of Single-Event Upset (SEU) Vulnerability of 6T SRAM Using FinFET Technologies. |
DFT |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Venu Birudu, Siva Sankar Yellampalli, Ramesh Vaddi |
Design and Exploration of Negative Capacitance FETs for Energy Efficient SRAM based In-Memory XNOR/Input and Weight Product Operation for Deep Neural Networks. |
iSES |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Nanda Deep Vallamchetty, Manish Goswami, Kavindra Kandpal |
A 14 nm Single-Ended Schmitt Trigger SRAM Cell for Improved SNM & Delay. |
iSES |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Joonhyung Kim, Jongsun Park 0001 |
The Quantitative Comparisons of Analog and Digital SRAM Compute-In-Memories for Deep Neural Network Applications. |
ISOCC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Qibang Zang, Wang Ling Goh, Fei Li 0015, Lu Lu 0013, Anh Tuan Do |
Temperature Compensation on SRAM-Based Computation in Memory Array. |
ISOCC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Yoojeong Yang, Dain Chon, Woong Choi |
Hiding Precharge Operation For Improved SRAM Cycle Time. |
ISOCC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Hyeyeong Lee, Joonhyung Kim, Jongsun Park 0001 |
SRAM Bit-line Boosting Circuit for Low Latency and Timing Aware Read Operation. |
ISOCC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Hyunchul Park, Jongsun Park 0001 |
Bit-Line Decoupled SRAM for Reducing Read Delays in Near Threshold Voltage Operations. |
ISOCC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Jihyung Jung, Youngmin Kim |
A High-Performance, Low-Power 8-Bit Full-Adder Using 8+T Differential SRAM for Computation-inMemory. |
ISOCC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Chuan-Han Cheng, Shih-Hsu Huang, Jin-Fu Li 0001 |
Design and Dataflow for Multibit SRAM-Based MAC Operations. |
ISOCC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Sanghyun Lee, Youngmin Kim |
Low Power Ternary XNOR using 10T SRAM for In-Memory Computing. |
ISOCC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Jiyoung Lee, Youngmin Kim |
Hybrid Assistive Circuit of SRAM for Improving Read and Write Noise Margin in 3nm CMOS. |
ISOCC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Yu-Guang Chen, Chi-Hsu Wang, Ing-Chao Lin |
An Aging Detection and Tolerance Framework for 8T SRAM Dot Product CIM Engine. |
ISOCC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Deepak Mittal |
Performance Analysis of Various CMOS SRAM Cells. |
ICCCNT |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Yuan Lou, Lijun Zhang, Yuling Yan, Lijun Ma, Zhongda Zhang |
Two-stage Pipelined SRAM Design Based on 14nm FinFET Process. |
EITCE |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Trishna Rajkumar, Johnny Öberg |
AnoDe: A Log-based Self-Supervised Framework to Detect Scrubber Failures in SRAM-FPGA. |
PRDC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Neelam Surana, Pramod Kumar Bharti, Bachu Varun Tej, Joycee Mekie |
Mixed-8T: Energy-Efficient Configurable Mixed-VT SRAM Design Techniques for Neural Networks. |
VLSID |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Kedar Janardan Dhori, Promod Kumar, Christophe Lecocq, Pascal Urard, Olivier Callen, Florian Cacho, Maryline Parra, Prashant Pandey, Daniel Noblet |
40nm Ultra-low Leakage SRAM with Embedded Sub-threshold Analog Closed Loop System for Efficient Source Biasing of the Memory Array in Retention Mode. |
VLSID |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Chandan Kumar, Rahul Kumar, Anuj Grover, Shouri Chatterjee, Kedar Janardan Dhori, Harsh Rawat |
Retention Problem Free High Density 4T SRAM cell with Adaptive Body Bias in 18nm FD-SOI. |
VLSID |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Abdel Alheyasat, Gabriel Torrens, Sebastia Bota, Bartomeu Alorda |
SRAM-cells Reproducibility Metrics for Physical Unclonable Function Applications. |
DCIS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | S. Kavitha, Santosh Kumar Vishvakarma, Bhupendra Singh Reniwal |
An Approach Towards Analog In-Memory Computing for Energy-Efficient Adder in SRAM Array. |
VDAT |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Pramod Kumar Bharti, Joycee Mekie |
RTQCC-14T: Radiation Tolerant Quadruple Cross Coupled Robust SRAM Design for Radiation Prone Environments. |
VDAT |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Jinwoo Choi 0003, Jaeyeon Kim, Chaemin Lim, Suhyun Lee, Jinho Lee, Dokyung Song, Youngsok Kim |
GuardiaNN: Fast and Secure On-Device Inference in TrustZone Using Embedded SRAM and Cryptographic Hardware. |
Middleware |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Jubayer Mahmod, Matthew Hicks |
Invisible bits: hiding secret messages in SRAM's analog domain. |
ASPLOS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Jubayer Mahmod, Matthew Hicks |
SRAM has no chill: exploiting power domain separation to steal on-chip secrets. |
ASPLOS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Xinshun Ning, Hongyong Yang, Mengdi Zhang, Yanji Wang, Ye Zhao, Shushan Qiao |
Multi-type SRAM Test Structure with an Improved March LR Algorithm. |
APCCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Yongliang Zhou, Zuo Cheng, Han Liu, Tianzhu Xiong, Bo Wang |
A 22-nm FDSOI 8T SRAM Based Time-Domain CIM for Energy-Efficient DNN Accelerators. |
APCCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Xudong Wang, Geng Li, Jiacong Sun, Huanjie Fan, Yong Chen, Hailong Jiao |
Ternary In-Memory MAC Accelerator With Dual-6T SRAM Cell for Deep Neural Networks. |
APCCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Srikrishna Vasudev, Kartickraj K, Anuj Grover |
Up to 13.7% Increase in Throughput of RISC V SoC Using Timing Speculative Razor SRAM. |
APCCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Liao-Chuan Chen, Zhaofang Li, Yi-Jhen Lin, Kuan-Pei Lee, Kea-Tiong Tang |
A 1.93TOPS/W Deep Learning Processor with a Reconfigurable Processing Element Array Based on SRAM Access Optimization. |
APCCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Leyi Chen, Junxian He, Jianyi Yu, Haibing Wang, Jing Lu, Liyuan Liu, Nanjian Wu, Cong Shi 0003, Min Tian |
An 8-T Processing-in-Memory SRAM Cell-Based Pixel-Parallel Array Processor for Vision Chips. |
APCCAS |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Liukai Xu, Songyuan Liu, Zhi Li, Dengfeng Wang, Yiming Chen, Yanan Sun 0003, Xueqing Li, Weifeng He, Shi Xu |
CREAM: computing in ReRAM-assisted energy and area-efficient SRAM for neural network acceleration. |
DAC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Nameun Kang, Hyungjun Kim, Hyunmyung Oh, Jae-Joon Kim |
TAIM: ternary activation in-memory computing hardware with 6T SRAM array. |
DAC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Yuquan He, Songyun Qu, Gangliang Lin, Cheng Liu 0008, Lei Zhang 0008, Ying Wang 0001 |
Processing-in-SRAM acceleration for ultra-low power visual 3D perception. |
DAC |
2022 |
DBLP DOI BibTeX RDF |
|
11 | Zhiting Lin, Honglan Zhan, Zhongwei Chen, Chunyu Peng, Xiulong Wu, Wenjuan Lu, Qiang Zhao 0007, Xuan Li, Junning Chen |
Cascade Current Mirror to Improve Linearity and Consistency in SRAM In-Memory Computing. |
IEEE J. Solid State Circuits |
2021 |
DBLP DOI BibTeX RDF |
|
11 | Hyunjoon Kim, Taegeun Yoo, Tony Tae-Hyoung Kim, Bongjin Kim |
Colonnade: A Reconfigurable SRAM-Based Digital Bit-Serial Compute-In-Memory Macro for Processing Neural Networks. |
IEEE J. Solid State Circuits |
2021 |
DBLP DOI BibTeX RDF |
|
11 | Tsung-Yung Jonathan Chang, Yen-Huei Chen, Wei-Min Chan, Hank Cheng, Po-Sheng Wang, Yangsyu Lin, Hidehiro Fujiwara, Robin Lee, Hung-Jen Liao, Ping-Wei Wang, Geoffrey Yeap, Quincy Li |
A 5-nm 135-Mb SRAM in EUV and High-Mobility Channel FinFET Technology With Metal Coupling and Charge-Sharing Write-Assist Circuitry Schemes for High-Density and Low-VMIN Applications. |
IEEE J. Solid State Circuits |
2021 |
DBLP DOI BibTeX RDF |
|
11 | Xin Si, Yung-Ning Tu, Wei-Hsing Huang, Jian-Wei Su, Pei-Jung Lu, Jing-Hong Wang, Ta-Wei Liu, Ssu-Yen Wu, Ruhui Liu, Yen-Chi Chou, Yen-Lin Chung, William Shih, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Nan-Chun Lien, Wei-Chiang Shih, Yajuan He, Qiang Li 0021, Meng-Fan Chang |
A Local Computing Cell and 6T SRAM-Based Computing-in-Memory Macro With 8-b MAC Operation for Edge AI Chips. |
IEEE J. Solid State Circuits |
2021 |
DBLP DOI BibTeX RDF |
|
11 | Mahmut E. Sinangil, Burak Erbagci, Rawan Naous, Kerem Akarvardar, Dar Sun, Win-San Khwa, Hung-Jen Liao, Yih Wang, Jonathan Chang |
A 7-nm Compute-in-Memory SRAM Macro Supporting Multi-Bit Input, Weight and Output and Achieving 351 TOPS/W and 372.4 GOPS. |
IEEE J. Solid State Circuits |
2021 |
DBLP DOI BibTeX RDF |
|
11 | David Bol, Maxime Schramme, Ludovic Moreau, Pengcheng Xu 0002, Rémi Dekimpe, Roghayeh Saeidi, Thomas Haine, Charlotte Frenkel, Denis Flandre |
SleepRunner: A 28-nm FDSOI ULP Cortex-M0 MCU With ULL SRAM and UFBR PVT Compensation for 2.6-3.6-μW/DMIPS 40-80-MHz Active Mode and 131-nW/kB Fully Retentive Deep-Sleep Mode. |
IEEE J. Solid State Circuits |
2021 |
DBLP DOI BibTeX RDF |
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11 | Zhiting Lin, Zhiyong Zhu, Honglan Zhan, Chunyu Peng, Xiulong Wu, Yuan Yao, Jianchao Niu, Junning Chen |
Two-Direction In-Memory Computing Based on 10T SRAM With Horizontal and Vertical Decoupled Read Ports. |
IEEE J. Solid State Circuits |
2021 |
DBLP DOI BibTeX RDF |
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11 | Saurabh Jain, Longyang Lin, Massimo Alioto |
±CIM SRAM for Signed In-Memory Broad-Purpose Computing From DSP to Neural Processing. |
IEEE J. Solid State Circuits |
2021 |
DBLP DOI BibTeX RDF |
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11 | Kunyang Liu, Xinpeng Chen, Hongliang Pu, Hirofumi Shinohara |
A 0.5-V Hybrid SRAM Physically Unclonable Function Using Hot Carrier Injection Burn-In for Stability Reinforcement. |
IEEE J. Solid State Circuits |
2021 |
DBLP DOI BibTeX RDF |
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11 | Zhiyu Chen 0003, Zhanghao Yu, Qing Jin, Yan He 0002, Jingyu Wang 0003, Sheng Lin 0001, Dai Li, Yanzhi Wang, Kaiyuan Yang 0001 |
CAP-RAM: A Charge-Domain In-Memory Computing 6T-SRAM for Accurate and Precision-Programmable CNN Inference. |
IEEE J. Solid State Circuits |
2021 |
DBLP DOI BibTeX RDF |
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11 | Neha Sharma, Rajeevan Chandel |
Variation tolerant and stability simulation of low power SRAM cell analysis using FGMOS. |
Int. J. Model. Simul. Sci. Comput. |
2021 |
DBLP DOI BibTeX RDF |
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11 | Swagata Mandal, Amlan Chakrabarti, Srinivasu Bodapati |
Clustered Error Resilient SRAM-Based Reconfigurable Computing Platform. |
IEEE Trans. Aerosp. Electron. Syst. |
2021 |
DBLP DOI BibTeX RDF |
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11 | Mohammad Mohammadinodoushan, Bertrand Cambou, Fatemeh Afghah, Christopher Robert Philabaum, Ian Burke |
Reliable, Secure, and Efficient Hardware Implementation of Password Manager System Using SRAM PUF. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
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11 | Gidong Baek, Hanwool Jeong |
High-Density SRAM Read Access Yield Estimation Methodology. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
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11 | Ji Sang Oh, Juhyun Park, Keonhee Cho, Tae Woo Oh, Seong-Ook Jung |
Differential Read/Write 7T SRAM With Bit-Interleaved Structure for Near-Threshold Operation. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
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11 | Yoav Weizman, Robert Giterman, Oron Chertkow, Maoz Wicentowski, Itamar Levi, Ilan Sever, Ishai Kehati, Osnat Keren, Alexander Fish |
Low-Cost Side-Channel Secure Standard 6T-SRAM-Based Memory With a 1% Area and Less Than 5% Latency and Power Overheads. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
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11 | Van Truong Nguyen, Jie-Seok Kim, Jong-Wook Lee |
10T SRAM Computing-in-Memory Macros for Binary and Multibit MAC Operation of DNN Edge Processors. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
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11 | Ki-Ryong Kim, Tae Woo Oh, Seong-Ook Jung |
Bitline Charge Sharing Suppressed Bitline and Cell Supply Collapse Assists for Energy-Efficient 6T SRAM. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
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11 | Seungbum Baek, Guk-Hyeon Yu, Jaewoo Kim, Chi Trung Ngo, Jason Kamran Eshraghian, Jong-Phil Hong |
A Reconfigurable SRAM Based CMOS PUF With Challenge to Response Pairs. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
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11 | Liang Pang, Shan Shen, Mengyun Yao |
A Spline-High Dimensional Model Representation for SRAM Yield Estimation in High Sigma and High Dimensional Scenarios. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
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11 | Junjong Lee, Jun-Sik Yoon, Jinsu Jeong, Seunghwan Lee, Sanguk Lee, Rock-Hyun Baek |
Monolithic 3D 6T-SRAM Based on Newly Designed Gate and Source/Drain Bottom Contact Schemes. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
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