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GrowBag graphs for keyword ? (Num. hits/coverage)
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Found 246 publication records. Showing 246 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
122 | Yiran Chen 0001, Hai Li 0001, Xiaobin Wang, Wenzhong Zhu, Wei Xu 0021, Tong Zhang 0002 |
Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 1-6, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
STT-RAM, emerging memory, spintronic |
98 | Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili |
An energy efficient cache design using spin torque transfer (STT) RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010, pp. 389-394, 2010, ACM, 978-1-4503-0146-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
(STT)RAM, memory technologies, cache design |
45 | Yuanhui Ni, Weiwen Chen, Lei Wang, Keni Qiu |
面向MLC STT-RAM的寄存器分配策略优化研究 (Optimization of Register Allocation Strategy for MLC STT-RAM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
计算机科学 ![In: 计算机科学 45(6A), pp. 562-567, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
|
43 | Hyunwoo Park, Hyun So, Hyukjun Lee |
Application specific cache design using STT-RAM based block-RAM for FPGA-based soft processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 15(10), pp. 20180330, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
43 | Wujie Wen, Yaojun Zhang, Yiran Chen 0001, Yu Wang 0002, Yuan Xie 0001 |
PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 33(11), pp. 1644-1656, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
43 | Tiefei Zhang, Tianzhou Chen, Jianzhong Wu, Youtian Qu |
A Selective Read-before-Write Scheme for Energy-Aware Spin Torque Transfer RAM (STT-RAM) Cache Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Circuits Syst. Comput. ![In: J. Circuits Syst. Comput. 22(5), 2013. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
43 | Wujie Wen, Yaojun Zhang, Yiran Chen 0001, Yu Wang 0002, Yuan Xie 0001 |
PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: The 49th Annual Design Automation Conference 2012, DAC '12, San Francisco, CA, USA, June 3-7, 2012, pp. 1191-1196, 2012, ACM, 978-1-4503-1199-1. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
43 | Wei Xu 0021, Hongbin Sun 0001, Xiaobin Wang, Yiran Chen 0001, Tong Zhang 0002 |
Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 19(3), pp. 483-493, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
43 | Anurag Nigam, Clinton Wills Smullen IV, Vidyabhushan Mohan, Eugene Chen, Sudhanva Gurumurthi, Mircea R. Stan |
Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2011 International Symposium on Low Power Electronics and Design, 2011, Fukuoka, Japan, August 1-3, 2011, pp. 121-126, 2011, IEEE/ACM, 978-1-61284-660-6. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP BibTeX RDF |
|
43 | Yiran Chen 0001, Xiaobin Wang, Hai Li 0001, Haiwen Xi, Yuan Yan, Wenzhong Zhu |
Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 18(12), pp. 1724-1734, 2010. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
29 | Saeed Seyedfaraji, Markus Bichl, Asad Aftab, Semeen Rehman |
HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 12, pp. 16598-16609, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
29 | Saeed Seyedfaraji, Markus Bichl, Asad Aftab, Semeen Rehman |
HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2401.14888, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
29 | Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal, José María Llabería |
Reuse Detector: Improving the Management of STT-RAM SLLCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2402.00533, 2024. The full citation details ...](Pics/full.jpeg) |
2024 |
DBLP DOI BibTeX RDF |
|
29 | SatyaJaswanth Badri, Mukesh Saini, Neeraj Goel |
Efficient placement and migration policies for an STT-RAM based hybrid L1 cache for intermittently powered systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Autom. Embed. Syst. ![In: Des. Autom. Embed. Syst. 27(4), pp. 303-331, December 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
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29 | Sheel Sindhu Manohar, Hemangee K. Kapoor |
CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 42(2), pp. 411-422, February 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
29 | Jinzhi Lai, Jueping Cai, Jie Chu |
A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Electron. Express ![In: IEICE Electron. Express 20(2), pp. 20220078, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
29 | Gwangeun Byeon, Seongwook Kim, Seokin Hong |
Improving Performance and Energy-efficiency of DNN Accelerators with STT-RAM Buffers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISOCC ![In: 20th International SoC Design Conference, ISOCC 2023, Jeju, Republic of Korea, October 25-28, 2023, pp. 207-208, 2023, IEEE, 979-8-3503-2703-8. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
29 | Saeed Seyedfaraji, Javad Talafy Daryani, Mohamed M. Sabry Aly, Semeen Rehman |
EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 10, pp. 82144-82155, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
29 | An Yang, Yanfeng Jiang |
Leakage-Current-Canceling Current-Sampling Sense Amplifier for Deep Submicrometer STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 69(9), pp. 3874-3878, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
29 | Jen-Wei Hsieh, Yueh-Ting Hou, Tai-Chieh Chang |
Alternative Encoding: A Two-Step Transition Reduction Scheme for MLC STT-RAM Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 41(8), pp. 2753-2757, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
29 | Sheel Sindhu Manohar, Sparsh Mittal, Hemangee K. Kapoor |
CORIDOR: Using COherence and TempoRal LocalIty to Mitigate Read Disurbance ErrOR in STT-RAM Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 21(1), pp. 2:1-2:24, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
29 | Saeed Seyedfaraji, Javad Talafy, Mohamed M. Sabry, Semeen Rehman |
EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2208.07838, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
29 | Dhruv Gajaria, Tosiron Adegbija |
Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Future Gener. Comput. Syst. ![In: Future Gener. Comput. Syst. 136, pp. 231-240, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
29 | Yogesh Kumar, S. Sivakumar, John Jose |
ENDURA : Enhancing Durability of Multi Level Cell STT-RAM based Non Volatile Memory Last Level Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, VLSI-SoC 2022, Patras, Greece, October 3-5, 2022, pp. 1-6, 2022, IEEE, 978-1-6654-9005-4. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
29 | Dhruv Gajaria, Kevin Antony Gomez, Tosiron Adegbija |
A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: IEEE 40th International Conference on Computer Design, ICCD 2022, Olympic Valley, CA, USA, October 23-26, 2022, pp. 685-692, 2022, IEEE, 978-1-6654-6186-3. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
29 | Arindam Sarkar, Newton Singh, Varun Venkitaraman, Virendra Singh |
DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 20(1), pp. 62-65, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
29 | Xiaoxiao Liu 0001, Mengjie Mao, Xiuyuan Bi, Hai Helen Li, Yiran Chen 0001 |
Exploring Applications of STT-RAM in GPU Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 68(1), pp. 238-249, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
29 | Sara Choi, Hong Keun Ahn, Byungkyu Song, Seung-Hyuk Kang, Seong-Ook Jung |
Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 68(6), pp. 2481-2493, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
29 | Jen-Wei Hsieh, Yi-Yu Liu, Hung-Tse Lee, Tai Chang |
TSE: Two-Step Elimination for MLC STT-RAM Last-Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 70(9), pp. 1498-1510, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
29 | Fateme S. Hosseini, Chengmo Yang |
A Compile-Time Framework for Tolerating Read Disturbance in STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 40(8), pp. 1545-1558, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
29 | Yao-Hung Huang, Jen-Wei Hsieh |
Read/Write Disturbance-Aware Design for MLC STT-RAM-based Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 27th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications, RTCSA 2021, Houston, TX, USA, August 18-20, 2021, pp. 11-20, 2021, IEEE, 978-1-6654-4188-9. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
29 | Sukarn Agarwal, Shounak Chakraborty 0001 |
ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 32nd IEEE International Conference on Application-specific Systems, Architectures and Processors, ASAP 2021, Virtual Conference, USA, July 7-9, 2021, pp. 171-174, 2021, IEEE, 978-1-6654-2701-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
29 | Mayank Baranwal, Udbhav Chugh, Shivang Dalal, Sukarn Agarwal, Hemangee K. Kapoor |
DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 22nd International Symposium on Quality Electronic Design, ISQED 2021, Santa Clara, CA, USA, April 7-9, 2021, pp. 469-475, 2021, IEEE, 978-1-7281-7641-3. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
29 | Muhammad Avais Qureshi, Jungwoo Park, Soontae Kim |
SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 28(6), pp. 1357-1370, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
29 | Elyas Khajekarimi, Kamal Jamshidi, Abbas Vafaei |
Integer linear programming model for allocation and migration of data blocks in the STT-RAM-based hybrid caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IET Comput. Digit. Tech. ![In: IET Comput. Digit. Tech. 14(3), pp. 97-106, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
29 | Masoomeh Jasemi, Shaahin Hessabi, Nader Bagherzadeh |
Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Electr. Eng. ![In: Comput. Electr. Eng. 86, pp. 106698, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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29 | Saeed Seyedfaraji, Amir M. Hajisadeghi, Javad Talafy, Hamid R. Zarandi |
DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microprocess. Microsystems ![In: Microprocess. Microsystems 73, pp. 102963, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
29 | Kyle Kuan, Tosiron Adegbija |
Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(6), pp. 1328-1339, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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29 | Quan Deng, Youtao Zhang, Zhenyu Zhao, Shuzheng Zhang, Minxuan Zhang, Jun Yang 0002 |
FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 39(10), pp. 2396-2409, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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29 | Masoomeh Jasemi, Shaahin Hessabi, Nader Bagherzadeh |
Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2001.08806, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
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29 | Shashank Suman, Hemangee K. Kapoor |
Reinforcement Learning Based Refresh Optimized Volatile STT-RAM Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2020 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2020, Limassol, Cyprus, July 6-8, 2020, pp. 222-227, 2020, IEEE, 978-1-7281-5775-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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29 | Shuo-Han Chen, Yu-Pei Liang, Yuan-Hao Chang 0001, Yun-Fei Liu, Chun-Feng Wu, Hsin-Wen Wei, Wei-Kuan Shih |
Reinforcing the energy efficiency of cyber-physical systems via direct and split cache consolidation on MLC STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: SAC '20: The 35th ACM/SIGAPP Symposium on Applied Computing, online event, [Brno, Czech Republic], March 30 - April 3, 2020, pp. 202-209, 2020, ACM, 978-1-4503-6866-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
29 | Ping Cheng, Jen-Wei Hsieh |
Early eviction and swapping for MLC STT-RAM-based LLC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: SAC '20: The 35th ACM/SIGAPP Symposium on Applied Computing, online event, [Brno, Czech Republic], March 30 - April 3, 2020, pp. 590-592, 2020, ACM, 978-1-4503-6866-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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29 | Shruti R. Kulkarni, Shihui Yin, Jae-sun Seo, Bipin Rajendran |
An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2020 Design, Automation & Test in Europe Conference & Exhibition, DATE 2020, Grenoble, France, March 9-13, 2020, pp. 1019-1024, 2020, IEEE, 978-3-9819263-4-7. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
29 | Jingjing Fu, Yu Liu |
A Comprehensive Performance Evaluation to GPGPU Applications under STT- RAM based Hybrid Cache Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBESC ![In: X Brazilian Symposium on Computing Systems Engineering, SBESC 2020, Florianopolis, Brazil, November 24-27, 2020, pp. 1-8, 2020, IEEE, 978-1-7281-8286-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
29 | Masayuki Sato 0001, Xue Hao, Kazuhiko Komatsu, Hiroaki Kobayashi |
Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
COOL CHIPS ![In: 2020 IEEE Symposium in Low-Power and High-Speed Chips, COOL CHIPS 2020, Kokubunji, Japan, April 15-17, 2020, pp. 1-3, 2020, IEEE, 978-1-7281-6347-5. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
29 | Binbin Liu, Fan Yang 0001, Dian Zhou, Xuan Zeng 0001 |
An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: IEEE International Symposium on Circuits and Systems, ISCAS 2020, Sevilla, Spain, October 10-21, 2020, pp. 1-4, 2020, IEEE, 978-1-7281-3320-1. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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29 | Jinbo Chen, Keren Liu, Xiaochen Guo, Patrick Girard 0001, Yuanqing Cheng |
DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 21st International Symposium on Quality Electronic Design, ISQED 2020, Santa Clara, CA, USA, March 25-26, 2020, pp. 408-414, 2020, IEEE, 978-1-7281-4207-4. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
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29 | Mimi Xie, Chen Pan, Youtao Zhang, Jingtong Hu, Yongpan Liu, Chun Jason Xue |
A Novel STT-RAM-Based Hybrid Cache for Intermittently Powered Processors in IoT Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 39(1), pp. 24-32, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Muhammad Avais Qureshi, Hyeonggyu Kim, Soontae Kim |
A Restore-Free Mode for MLC STT-RAM Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(6), pp. 1465-1469, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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29 | Fazal Hameed, Jerónimo Castrillón |
A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 27(10), pp. 2375-2386, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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29 | Fanfan Shen, Yanxiang He, Jun Zhang 0058, Chao Xu |
Periodic learning-based region selection for energy-efficient MLC STT-RAM cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 75(10), pp. 6220-6238, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Elyas Khajekarimi, Kamal Jamshidi, Abbas Vafaei |
Energy minimization in the STT-RAM-based high-capacity last-level caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 75(10), pp. 6831-6854, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Zahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, Seyed Ghassem Miremadi |
AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Emerg. Top. Comput. ![In: IEEE Trans. Emerg. Top. Comput. 7(3), pp. 481-492, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Lei Yang 0018, Weichen Liu, Nan Guan, Nikil D. Dutt |
Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM Based Router. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 68(8), pp. 1174-1189, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Kyle Kuan, Tosiron Adegbija |
HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 68(11), pp. 1623-1634, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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29 | Jungwoo Park, Myoungjun Lee, Soontae Kim, Minho Ju, Jeongkyu Hong |
MH Cache: A Mult Stephen Jarvisi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 16(3), pp. 26:1-26:26, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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29 | Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu 0002, Jianlei Yang 0001 |
Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Sustain. Comput. Informatics Syst. ![In: Sustain. Comput. Informatics Syst. 22, pp. 206-218, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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29 | Keni Qiu, Yujie Zhu, Yuanchao Xu 0002, Qirun Huo, Chun Jason Xue |
BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. J. ![In: Microelectron. J. 83, pp. 137-146, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Kyle Kuan, Tosiron Adegbija |
Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1904.09363, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
29 | Kyle Kuan, Tosiron Adegbija |
HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1905.07511, 2019. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
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29 | Fateme S. Hosseini, Chengmo Yang |
Compiler-Directed and Architecture-Independent Mitigation of Read Disturbance Errors in STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation & Test in Europe Conference & Exhibition, DATE 2019, Florence, Italy, March 25-29, 2019, pp. 222-227, 2019, IEEE, 978-3-9819263-2-3. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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29 | Shruti R. Kulkarni, Deepak Vinayak Kadetotad, Shihui Yin, Jae-Sun Seo, Bipin Rajendran |
Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECS ![In: 26th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2019, Genoa, Italy, November 27-29, 2019, pp. 438-441, 2019, IEEE, 978-1-7281-0996-1. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija |
SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IGSC ![In: Tenth International Green and Sustainable Computing Conference, IGSC 2019, Alexandria, VA, USA, October 21-24, 2019, pp. 1-7, 2019, IEEE, 978-1-7281-5416-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Dhruv Gajaria, Tosiron Adegbija |
ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMSYS ![In: Proceedings of the International Symposium on Memory Systems, MEMSYS 2019, Washington, DC, USA, September 30 - October 03, 2019., pp. 439-450, 2019, ACM, 978-1-4503-7206-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
29 | Puneet Saraf, Madhu Mutyam |
Endurance enhancement of write-optimized STT-RAM caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMSYS ![In: Proceedings of the International Symposium on Memory Systems, MEMSYS 2019, Washington, DC, USA, September 30 - October 03, 2019., pp. 101-113, 2019, ACM, 978-1-4503-7206-0. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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29 | Yu-Pei Liang, Tseng-Yi Chen, Yuan-Hao Chang 0001, Shuo-Han Chen, Pei-Yu Chen, Wei-Kuan Shih |
Rethinking Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with Asymmetric Write Energy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, ISLPED 2019, Lausanne, Switzerland, July 29-31, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-2954-9. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
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29 | Masayuki Sato 0001, Yoshiki Shoji, Zentaro Sakai, Ryusuke Egawa, Hiroaki Kobayashi |
An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Multi Scale Comput. Syst. ![In: IEEE Trans. Multi Scale Comput. Syst. 4(4), pp. 593-604, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Mohammad Taghi Teimoori, Alireza Ejlali |
An Instruction-Level Quality-Aware Method for Exploiting STT-RAM Read Approximation Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Embed. Syst. Lett. ![In: IEEE Embed. Syst. Lett. 10(2), pp. 41-44, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | He Zhang 0011, Wang Kang 0001, Youguang Zhang, Meng-Fan Chang, Weisheng Zhao |
A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 6, pp. 64250-64260, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Navid Khoshavi, Ronald F. DeMara |
Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 6, pp. 14576-14590, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Jaeyoung Park, Young Uk Yim |
Two-Phase Read Strategy for Low Energy Variation-Tolerant STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(12), pp. 2584-2590, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Fazal Hameed, Asif Ali Khan, Jerónimo Castrillón |
Performance and Energy-Efficient Design of STT-RAM Last-Level Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(6), pp. 1059-1072, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Shouyi Yin, Tianyi Lu, Zhicong Xie, Leibo Liu, Shaojun Wei |
Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 26(11), pp. 2345-2357, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Lan Gao, Rui Wang 0014, Yunlong Xu, Hailong Yang, Zhongzhi Luan, Depei Qian, Han Zhang, Jihong Cai |
SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 74(7), pp. 3388-3414, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Adnan Nasri, Mahmood Fathy, Ali Broumandnia |
An energy-efficient 3D-stacked STT-RAM cache architecture for cloud processors: the effect on emerging scale-out workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 74(4), pp. 1547-1561, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Zihao Liu, Mengjie Mao, Tao Liu 0023, Xue Wang, Wujie Wen, Yiran Chen 0001, Hai Li 0001, Danghui Wang, Yukui Pei, Ning Ge 0001 |
TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 37(10), pp. 1985-1998, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Bohua Li, Yukui Pei, Wujie Wen |
Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 14(1), pp. 10:1-10:20, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Yanna Zhu, Danghui Wang |
基于多级磁自旋存储器的Cache调度策略的设计 (Design of Cache Scheduling Policies Based on MLC STT-RAM). ![Search on Bibsonomy](Pics/bibsonomy.png) |
计算机科学 ![In: 计算机科学 45(6A), pp. 513-517, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP BibTeX RDF |
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29 | Taehui Na, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung |
Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 65-I(1), pp. 163-174, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Behzad Zeinali, Dimitrios Karsinos, Farshad Moradi |
Progressive Scaled STT-RAM for Approximate Computing in Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. II Express Briefs ![In: IEEE Trans. Circuits Syst. II Express Briefs 65-II(7), pp. 938-942, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal Arnal, José María Llabería |
Reuse Detector: Improving the Management of STT-RAM SLLCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. J. ![In: Comput. J. 61(6), pp. 856-880, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Rabab Bouziane, Erven Rohou, Abdoulaye Gamatié |
Energy-Efficient Memory Mappings based on Partial WCET Analysis and Multi-Retention Time STT-RAM. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTNS ![In: Proceedings of the 26th International Conference on Real-Time Networks and Systems, RTNS 2018, Chasseneuil-du-Poitou, France, October 10-12, 2018, pp. 148-158, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Zihao Liu, Tao Liu 0023, Jie Guo 0002, Nansong Wu, Wujie Wen |
An ECC-Free MLC STT-RAM Based Approximate Memory Design for Multimedia Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2018 IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2018, Hong Kong, China, July 8-11, 2018, pp. 142-147, 2018, IEEE Computer Society, 978-1-5386-7099-6. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
29 | Kyle Kuan, Tosiron Adegbija |
LARS: Logically adaptable retention time STT-RAM cache for embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2018 Design, Automation & Test in Europe Conference & Exhibition, DATE 2018, Dresden, Germany, March 19-23, 2018, pp. 461-466, 2018, IEEE, 978-3-9819263-0-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Saaed S. Faraji, Javad Talafy, Amir M. Hajisadeghi, Hamid R. Zarandi |
DUSTER: DUal Source Write TERmination Method for STT-RAM Memories. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: 21st Euromicro Conference on Digital System Design, DSD 2018, Prague, Czech Republic, August 29-31, 2018, pp. 182-189, 2018, IEEE Computer Society, 978-1-5386-7377-5. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Enes Eken, Ismail Bayram, Hai Helen Li, Yiran Chen 0001 |
Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: 23rd Asia and South Pacific Design Automation Conference, ASP-DAC 2018, Jeju, Korea (South), January 22-25, 2018, pp. 375-380, 2018, IEEE, 978-1-5090-0602-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Bhukya Krishna Priya, Sampath Kumar, B. Shameedha Begum, N. Ramasubramaniam |
Enhancing the lifetime of STT-RAM with MRU replacement algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RAIT ![In: 2018 4th International Conference on Recent Advances in Information Technology (RAIT), Dhanbad, India, March 15-17, 2018, pp. 1-6, 2018, IEEE, 978-1-5386-3038-9. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
29 | Hengyu Zhao, Jishen Zhao |
Leveraging MLC STT-RAM for energy-efficient CNN training. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MEMSYS ![In: Proceedings of the International Symposium on Memory Systems, MEMSYS 2018, Old Town Alexandria, VA, USA, October 01-04, 2018, pp. 279-290, 2018, ACM, 978-1-4503-6475-1. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
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29 | Sparsh Mittal, Jeffrey S. Vetter, Lei Jiang 0001 |
Addressing Read-Disturbance Issue in STT-RAM by Data Compression and Selective Duplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 16(2), pp. 94-98, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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29 | Yuanhui Ni, Zhiyao Gong, Weiwen Chen, Chengmo Yang, Keni Qiu |
State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2017, pp. 1030249:1-1030249:9, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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29 | Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li, Yiran Chen 0001 |
Giant Spin-Hall assisted STT-RAM and logic design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Integr. ![In: Integr. 58, pp. 253-261, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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29 | Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Helen Li |
Cross-Layer Optimization for Multilevel Cell STT-RAM Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(6), pp. 1807-1820, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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29 | Hooman Farkhani, Mohammad Tohidi, Ali Peiravi, Jens Kargaard Madsen, Farshad Moradi |
STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(2), pp. 476-487, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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29 | Hyeonggyu Kim, Soontae Kim, Jooheung Lee |
Write-Amount-Aware Management Policies for STT-RAM Caches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(4), pp. 1588-1592, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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29 | Lili Song, Ying Wang 0001, Yinhe Han 0001, Huawei Li 0001, Yuanqing Cheng, Xiaowei Li 0001 |
STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 25(4), pp. 1285-1296, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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29 | Xunchao Chen, Navid Khoshavi, Ronald F. DeMara, Jun Wang 0001, Dan Huang, Wujie Wen, Yiran Chen 0001 |
Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 66(5), pp. 786-798, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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29 | Zahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, Seyed Ghassem Miremadi |
An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 28(6), pp. 1564-1577, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
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29 | Yaojun Zhang, Bonan Yan, Xiaobin Wang, Yiran Chen 0001 |
Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 36(7), pp. 1181-1192, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
29 | Sparsh Mittal |
Mitigating Read-disturbance Errors in STT-RAM Caches by Using Data Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1711.06790, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP BibTeX RDF |
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