Search results for "ALUs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
75	Monica Alderighi, Sergio D'Angelo, Giacomo R. Sechi, Cecilia Metra	Achieving Fault-Tolerance by Shifted and Rotated Operands in TMR Non-Diverse ALUs.	DFT	2000	DBLP DOI BibTeX RDF
51	B. Hamdi, Hakim Bederr, Michael Nicolaidis	A tool for automatic generation of self-checking data paths.	VTS	1995	DBLP DOI BibTeX RDF	self-checking data paths, ALUs, shifters, double rail checkers, logic testing, built-in self test, microprocessors, adders, circuit CAD, multipliers, microcontrollers, register files, circuit design, CAD tools, automatic generation, automatic test software, dividers, circuit testing, parity checkers
51	Samiye Mete, Sevcan Fata, Merlinda Alus Tokat	Feelings, opinions and experiences of Turkish women with infertility: A qualitative study.	Health Informatics J.	2020	DBLP DOI BibTeX RDF
44	Brucek Khailany, William J. Dally, Scott Rixner, Ujval J. Kapasi, John D. Owens, Brian Towles	Exploring the VLSI Scalability of Stream Processors.	HPCA	2003	DBLP DOI BibTeX RDF
44	Seongbae Park, SangMin Shim, Soo-Mook Moon	Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed.	MICRO	1997	DBLP DOI BibTeX RDF	SPARC-based VLIW testbed, VLIW microprocessors, Very Long Instruction Word microprocessors, all-path speculation, gcc-generated optimized SPARC code, high-performance VLIW code, nongreedy enhanced pipeline scheduling, nonspeculative operations, profile-based all-path speculation, restricted speculative loads, scheduling compiler, speculative operations, trace-based speculation, performance, compiler, computer architecture, parallel machines, software pipelining, loop unrolling, renaming, memory disambiguation, copies, scheduling techniques
44	Pradip K. Jha, Nikil D. Dutt	High-level library mapping for arithmetic components.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
31	Seok Young Kim, Chang Hyun Kim, Won Joon Lee, Il Park 0001, Seon Wook Kim	Low-overhead inverted LUT design for bounded DNN activation functions on floating-point vector ALUs.	Microprocess. Microsystems	2022	DBLP DOI BibTeX RDF
31	Omer Subasi, Chun-Kai Chang, Mattan Erez, Sriram Krishnamoorthy	Characterizing the Impact of Soft Errors Affecting Floating-point ALUs using RTL-Ievel Fault Injection.	ICPP	2018	DBLP DOI BibTeX RDF
31	Alen Bardizbanyan, Per Larsson-Edefors	Exploring early and late ALUs for single-issue in-order pipelines.	ICCD	2015	DBLP DOI BibTeX RDF
31	Takahisa Wada, Shunichi Ishiwata, Katsuyuki Kimura, Keiri Nakanishi, Masato Sumiyoshi, Takashi Miyamori, Masaki Nakagawa	A VLIW Vector Media Coprocessor With Cascaded SIMD ALUs.	IEEE Trans. Very Large Scale Integr. Syst.	2009	DBLP DOI BibTeX RDF
31	Makoto Ozone, Tatsuo Hiramatsu, Katsunori Hirase, Kazuhisa Iizuka	Reconfigurable Processor LSI Based on ALU Array with Limitations of Connections of ALUs for Software Radio.	ITNG	2009	DBLP DOI BibTeX RDF	ALU array, software define radio, data flow graph, reconfigurable processor
31	Jaume Abella 0001, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González 0001	Fuse: A Technique to Anticipate Failures due to Degradation in ALUs.	IOLTS	2007	DBLP DOI BibTeX RDF
31	J. J. Rodriguez-Navarro	Comments on "Carry checking/parity prediction adders and ALUs".	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
31	Bhaskar Chatterjee, Manoj Sachdev, Ali Keshavarzi	A DFT Technique for Delay Fault Testability and Diagnostics in 32-Bit High Performance CMOS ALUs.	ITC	2004	DBLP DOI BibTeX RDF
31	Michael Nicolaidis	Carry checking/parity prediction adders and ALUs.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
31	Stevan Jay Anastasoff	The presence of old Alus in GC-rich regions of the human genome - a genetic algorithm perspective.	IEEE Congress on Evolutionary Computation	2002	DBLP DOI BibTeX RDF
31	Sanu K. Mathew, Ram K. Krishnamurthy, Mark A. Anders 0001, Rafael Rios, Kaizad R. Mistry, Krishnamurthy Soumyanath	Sub-500-ps 64-b ALUs in 0.18-μm SOI/bulk CMOS: design and scaling trends.	IEEE J. Solid State Circuits	2001	DBLP DOI BibTeX RDF
31	Mihalis Psarakis, Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Deterministic Built-In Self -Test for Shifters, Adders and ALUs in Datapaths.	LATW	2000	DBLP BibTeX RDF
31	Chua-Chin Wang, Sheng-Hua Chen, Shen-Fu Hsiao, Chuan-Lin Wu	Design and performance verification of ALUs for 64-bit 8-issue superscaler microprocessors using 0.25 um CMOS technology.	ICECS	1999	DBLP DOI BibTeX RDF
31	M. Shahkarami, Graham A. Jullien, William C. Miller	Designing FIR filters with enhanced Fermat ALUs.	ISCAS (3)	1999	DBLP DOI BibTeX RDF
31	James E. Phillips, Stamatis Vassiliadis	Proof of correctness of high-performance 3-1 interlock collapsing ALUs.	IBM J. Res. Dev.	1993	DBLP DOI BibTeX RDF
31	Michael Nicolaidis	Efficient Implementations of Self-Checking Adders and ALUs.	FTCS	1993	DBLP DOI BibTeX RDF
31	Martin S. Schmokler	Design of Large ALUs Using Multiple PLA Macros.	IBM J. Res. Dev.	1980	DBLP DOI BibTeX RDF
29	Juan Fernando Eusse Giraldo, Michael Hübner 0001, Ricardo Pezzuol Jacobi	BRICK: a multi-context expression grained reconfigurable architecture.	SBCCI	2009	DBLP DOI BibTeX RDF	validation, reconfigurable computing, MIMO, SystemC, co-simulation, coarse grain
29	Gayatri Mehta, Colin J. Ihrig, Alex K. Jones	Reducing energy by exploring heterogeneity in a coarse-grain fabric.	IPDPS	2008	DBLP DOI BibTeX RDF
29	Michael D. Powell, Ethan Schuchman, T. N. Vijaykumar	Balancing Resource Utilization to Mitigate Power Density in Processor Pipelines.	MICRO	2005	DBLP DOI BibTeX RDF
29	Angshuman Parashar, Sudhanva Gurumurthi, Anand Sivasubramaniam	A Complexity-Effective Approach to ALU Bandwidth Enhancement for Instruction-Level Temporal Redundancy.	ISCA	2004	DBLP DOI BibTeX RDF	Complexity-effective design, Temporal Redundancy, Instruction Reuse
29	Narasimhan Ramasubramanian, Ram Subramanian, Santosh Pande	Automatic Compilation of Loops to Exploit Operator Parallelism on Configurable Arithmetic Logic Units.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	operator parallelism, FPGAs, parallel computing, Compilers, loop transformation, reconfigurable systems
29	Ujval J. Kapasi, William J. Dally, Scott Rixner, John D. Owens, Brucek Khailany	The Imagine Stream Processor.	ICCD	2002	DBLP DOI BibTeX RDF
29	Ramadass Nagarajan, Karthikeyan Sankaralingam, Doug Burger, Stephen W. Keckler	A design space evaluation of grid processor architectures.	MICRO	2001	DBLP DOI BibTeX RDF
15	George L. Yuan, Ali Bakhoda, Tor M. Aamodt	Complexity effective memory access scheduling for many-core accelerator architectures.	MICRO	2009	DBLP DOI BibTeX RDF	graphics processors, on-chip interconnection networks, memory controller
15	Toshinori Sato, Shingo Watanabe	Uncriticality-directed scheduling for tackling variation and power challenges.	ISQED	2009	DBLP DOI BibTeX RDF
15	Byunghyun Jang, Synho Do, Homer H. Pien, David R. Kaeli	Architecture-aware optimization targeting multithreaded stream computing.	GPGPU	2009	DBLP DOI BibTeX RDF	Brook+, optimization, GPGPU
15	Sandro Bartolini, Irina Branovic, Roberto Giorgi, Enrico Martinelli	Effects of Instruction-Set Extensions on an Embedded Processor: A Case Study on Elliptic Curve Cryptography over GF(2m).	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Microprocessor/microcomputer applications, Performance Evaluation, Cryptography, Elliptic curves, Public key cryptosystems, Processor Architectures, Pipeline processors, Portable devices, Hardware/software interfaces, Instruction set design
15	Shang Ma, Jianhao Hu, Lin Zhang, Xiang Ling 0002	An efficient RNS parity checker for moduli set {2 n - 1, 2 n + 1, 22 n + 1} and its applications.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	number comparison, sign determination, overflow detection, VLSI, RNS, parity check
15	Bjorn De Sutter, Paul Coene, Tom Vander Aa, Bingfeng Mei	Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays.	LCTES	2008	DBLP DOI BibTeX RDF	register allocation, placement and routing, coarse-grained, reconfigurable arrays
15	Swaroop Ghosh, Kaushik Roy 0001	Exploring high-speed low-power hybrid arithmetic units at scaled supply and adaptive clock-stretching.	ASP-DAC	2008	DBLP DOI BibTeX RDF
15	Behnam Robatmili, Katherine E. Coons, Doug Burger, Kathryn S. McKinley	Register Bank Assignment for Spatially Partitioned Processors.	LCPC	2008	DBLP DOI BibTeX RDF
15	Yu Zhou, Hui Guo	Application Specific Low Power ALU Design.	EUC (1)	2008	DBLP DOI BibTeX RDF
15	Deepa Kannan, Aviral Shrivastava, Vipin Mohan, Sarvesh Bhardwaj, Sarma B. K. Vrudhula	Temperature and Process Variations Aware Power Gating of Functional Units.	VLSI Design	2008	DBLP DOI BibTeX RDF
15	Deepa Kannan, Aviral Shrivastava, Sarvesh Bhardwaj, Sarma B. K. Vrudhula	Power Reduction of Functional Units Considering Temperature and Process Variations.	VLSI Design	2008	DBLP DOI BibTeX RDF
15	Oscal T.-C. Chen, Li-Hsun Chen, Nai-Wei Lin, Chih-Chang Chen	Application-Specific Data Path for Highly Efficient Computation of Multistandard Video Codecs.	IEEE Trans. Circuits Syst. Video Technol.	2007	DBLP DOI BibTeX RDF
15	Anita Lungu, Daniel J. Sorin	Verification-Aware Microprocessor Design.	PACT	2007	DBLP DOI BibTeX RDF
15	Jayanth Gummaraju, Mattan Erez, Joel Coburn, Mendel Rosenblum, William J. Dally	Architectural Support for the Stream Execution Model on General-Purpose Processors.	PACT	2007	DBLP DOI BibTeX RDF
15	Awni Itradat, M. Omair Ahmad, Ali M. Shatnawi	Architectural Synthesis of DSP Applications with Dynamically Reconfigurable Functional Units.	ISCAS	2007	DBLP DOI BibTeX RDF
15	Swapnil Bahl	A Sharable Built-in Self-Repair for Semiconductor Memories with 2-D Redundancy Schema.	DFT	2007	DBLP DOI BibTeX RDF
15	Elias Mizan, Tileli Amimeur, Margarida F. Jacome	Self-Imposed Temporal Redundancy: An Efficient Technique to Enhance the Reliability of Pipelined Functional Units.	SBAC-PAD	2007	DBLP DOI BibTeX RDF
15	Jing Du 0002, Xuejun Yang, Guibin Wang, Tao Tang 0001, Kun Zeng	Architecture-Based Optimization for Mapping Scientific Applications to Imagine.	ISPA	2007	DBLP DOI BibTeX RDF	kernel partition, stream forming, scientific application, Imagine
15	Kunhyuk Kang, Keejong Kim, Ahmad E. Islam, Muhammad Ashraful Alam, Kaushik Roy 0001	Characterization and Estimation of Circuit Reliability Degradation under NBTI using On-Line IDDQ Measurement.	DAC	2007	DBLP DOI BibTeX RDF
15	Mladen Berekovic, Tim Niggemeier	A Scalable, Multi-thread, Multi-issue Array Processor Architecture for DSP Applications Based on Extended Tomasulo Scheme.	SAMOS	2006	DBLP DOI BibTeX RDF
15	Jelena Trajkovic, Mehrdad Reshadi, Bita Gorjiara, Daniel Gajski	A Graph Based Algorithm for Data Path Optimization in Custom Processors.	DSD	2006	DBLP DOI BibTeX RDF
15	Shiliang Hu, Ilhyun Kim, Mikko H. Lipasti, James E. Smith 0001	An approach for implementing efficient superscalar CISC processors.	HPCA	2006	DBLP DOI BibTeX RDF
15	Lih Wen Koh, Oliver Diessel	Functional Unit Chaining: A Runtime Adaptive Architecture for Reducing Bypass Delays.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF
15	Nan Wu 0003, Mei Wen, Ju Ren 0002, Yi He 0008, Chunyuan Zhang	Register Allocation on Stream Processor with Local Register File.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	local register file, spilling, register allocation, VLIW, stream processor
15	Palanichamy Manikandan, B. D. Liu, L. Y. Chiou, G. Sundar, Chittaranjan R. Mandal	Asynchronous Design Methodology for an Efficient Implementation of Low power ALU.	APCCAS	2006	DBLP DOI BibTeX RDF
15	Jordi Cortadella, Michael Kishinevsky, Bill Grundmann	Synthesis of synchronous elastic architectures.	DAC	2006	DBLP DOI BibTeX RDF	protocols, synthesis, latency-tolerance, latency-insensitive design
15	Michael B. Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Scalar Operand Networks.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	microprocessors, distributed architectures, Interconnection architectures
15	George Almási 0001, Gábor Dózsa, C. Christopher Erway, Burkhard D. Steinmacher-Burow	Efficient Implementation of Allreduce on BlueGene/L Collective Network.	PVM/MPI	2005	DBLP DOI BibTeX RDF
15	Oliver Bringmann 0001, Wolfgang Rosenstiel, Axel Siebenborn	Conflict analysis in multiprocess synthesis for optimized system integration.	CODES+ISSS	2005	DBLP DOI BibTeX RDF	scheduling, systems-on-chip, system level design, concurrent systems, binding, behavioral synthesis
15	Hong Yue, Ming-che Lai, Kui Dai, Zhiying Wang 0003	Design of a Configurable Embedded Processor Architecture for DSP Functions.	ICPADS (2)	2005	DBLP DOI BibTeX RDF
15	Hongkyu Kim, D. Scott Wills, Linda M. Wills	Reducing Operand Communication Overhead using Instruction Clustering for Multimedia Application.	ISM	2005	DBLP DOI BibTeX RDF
15	Ioannis Voyiatzis, Dimitris Gizopoulos, Antonis M. Paschalis	Accumulator-Based Weighted Pattern Generation.	IOLTS	2005	DBLP DOI BibTeX RDF
15	Hamed Fatemi, Henk Corporaal, Twan Basten, Richard P. Kleihorst, Pieter P. Jonker	Designing Area and Performance Constrained SIMD/VLIW Image Processing Architectures.	ACIVS	2005	DBLP DOI BibTeX RDF
15	Mladen Berekovic, Sören Moch, Peter Pirsch	A scalable, clustered SMT processor for digital signal processing.	SIGARCH Comput. Archit. News	2004	DBLP DOI BibTeX RDF
15	Sridhar Rajagopal, Joseph R. Cavallaro, Scott Rixner	Design Space Exploration for Real-Time Embedded Stream Processors.	IEEE Micro	2004	DBLP DOI BibTeX RDF
15	Paul Willmann, Michael Brogioli, Vijay S. Pai	Spinach: a liberty-based simulator for programmable network interface architectures.	LCTES	2004	DBLP DOI BibTeX RDF	programmable network interfaces, simulation, embedded systems
15	Marc Epalza, Paolo Ienne, Daniel Mlynek	Adding Limited Reconfigurability to Superscalar Processors.	IEEE PACT	2004	DBLP DOI BibTeX RDF
15	W. W. S. Chu, Robert G. Dimond, S. Perrott, S. P. Seng, Wayne Luk	Customisable EPIC Processor: Architecture and Tools.	DATE	2004	DBLP DOI BibTeX RDF
15	Vinod Viswanath	Multi-log Processor - Towards Scalable Event-Driven Multiprocessors.	DSD	2004	DBLP DOI BibTeX RDF
15	Peter G. Sassone, D. Scott Wills	Dynamic Strands: Collapsing Speculative Dependence Chains for Reducing Pipeline Communication.	MICRO	2004	DBLP DOI BibTeX RDF
15	Mei Wen, Chunyuan Zhang, Nan Wu 0003, Haiyan Li, Li Li 0005	A Parallel Reed-Solomon Decoder on the Imagine Stream Processor.	ISPA	2004	DBLP DOI BibTeX RDF
15	Ujval J. Kapasi, Scott Rixner, William J. Dally, Brucek Khailany, Jung Ho Ahn, Peter R. Mattson, John D. Owens	Programmable Stream Processors.	Computer	2003	DBLP DOI BibTeX RDF
15	Vasily G. Moshnyaga	Reducing Switching Activity of Subtraction via Variable Truncation of the Most-Significant Bits.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	bit-truncation, low-power design, video processing, switching activity
15	Hyun Suk Kim, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin	Adapting instruction level parallelism for optimizing leakage in VLIW architectures.	LCTES	2003	DBLP DOI BibTeX RDF	power supply gating, instruction level parallelism, instruction scheduling, VLIW architecture, leakage energy, functional units
15	Mark G. Arnold	A VLIW Architecture for Logarithmic Arithmetic.	DSD	2003	DBLP DOI BibTeX RDF	Very Long Instruction Word, sum of products, pipeline, Logarithmic Number System
15	Michael Bedford Taylor, Walter Lee, Saman P. Amarasinghe, Anant Agarwal	Scalar Operand Networks: On-Chip Interconnect for ILP in Partitioned Architecture.	HPCA	2003	DBLP DOI BibTeX RDF
15	Kay-Chuan Benny Tan, Tughrul Arslan	Shift-accumulator ALU centric JPEG2000 5/3 lifting based discrete wavelet transform architecture.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
15	Kwong-Sak Leung, Kin-Hong Lee, Sin Man Cheang	Parallel Programs Are More Evolvable than Sequential Programs.	EuroGP	2003	DBLP DOI BibTeX RDF
15	Bradley C. Kuszmaul, Dana S. Henry, Gabriel H. Loh	A Comparison of Asymptotically Scalable Superscalar Processors.	Theory Comput. Syst.	2002	DBLP DOI BibTeX RDF
15	Ryan Kastner, Adam Kaplan, Seda Ogrenci Memik, Elaheh Bozorgzadeh	Instruction generation for hybrid reconfigurable systems.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	FPGA, high-level synthesis, reconfigurable computing
15	Sumit Ghosh	P2EDAS: Asynchronous, Distributed Event Driven Simulation Algorithm with Inconsistent Event Preemption for Accurate Execution of VHDL Descriptions on Parallel Processors.	IEEE Trans. Computers	2001	DBLP DOI BibTeX RDF	simulation of hardware descriptions, inertial delays, descheduling, anticipatory scheduling, preemption of inconsistent events, parallel processing, VLSI, distributed algorithms, discrete event simulation, VHDL, Digital simulation, logic simulation, event driven simulation, timing semantics
15	Tsukasa Yamauchi, Shogo Nakaya, Takeshi Inuo, Nobuki Kajihara	Arithmetic Operation Oriented Reconfigurable Chip: RHW.	FPL	2001	DBLP DOI BibTeX RDF
15	Thomas L. Sterling	An Introduction to the Gilgamesh PIM Architecture.	Euro-Par	2001	DBLP DOI BibTeX RDF
15	Ronald D. Blanton, John P. Hayes	On the design of fast, easily testable ALU's.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
15	Nektarios Kranitis, Dimitris Gizopoulos, Antonis M. Paschalis, Mihalis Psarakis, Yervant Zorian	Power-/Energy Efficient BIST Schemes for Processor Data Paths.	IEEE Des. Test Comput.	2000	DBLP DOI BibTeX RDF
15	Panagiotis Manolios	Correctness of Pipelined Machines.	FMCAD	2000	DBLP DOI BibTeX RDF
15	Issam Alzaher-Noufal, Michael Nicolaidis	A CAD Framework for Generating Self-Checking 1 Multipliers Based on Residue Codes.	DATE	1999	DBLP DOI BibTeX RDF	Fault Secure Circuits, Residue Arithmetic Codes, Multipliers, Self-Checking Circuits
15	Dana S. Henry, Bradley C. Kuszmaul, Vinod Viswanath	The Ultrascalar Processor-An Asymptotically Scalable Superscalar Microarchitecture.	ARVLSI	1999	DBLP DOI BibTeX RDF
15	Tonia Morris, Erica Fletcher, Cyrus Afghahi, Sami Issa, Kevin Connolly, Jean-Charles Korta	A Column-based Processing Array for High-speed Digital Image Processing.	ARVLSI	1999	DBLP DOI BibTeX RDF
15	Jörg Henkel	A Methodology for Minimizing Power Dissipation of Embedded Systems through Hardware/Software Partitioning.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
15	Jian Shen, Jacob A. Abraham	Synthesis of Native Mode Self-Test Programs.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	native mode self-test, test synthesis, functional test generation
15	David J. Kolson, Alexandru Nicolau, Nikil D. Dutt	Copy Elimination for Parallelizing Compilers.	LCPC	1998	DBLP DOI BibTeX RDF
15	Walter Lee, Rajeev Barua, Matthew I. Frank, Devabhaktuni Srikrishna, Jonathan Babb, Vivek Sarkar, Saman P. Amarasinghe	Space-Time Scheduling of Instruction-Level Parallelism on a Raw Machine.	ASPLOS	1998	DBLP DOI BibTeX RDF
15	Albrecht P. Stroele	Arithmetic Pattern Generators for Built-In Self-Test.	ICCD	1996	DBLP DOI BibTeX RDF	Arithmetic functions, built-in self-test, design for testability, pattern generator
15	Reiner W. Hartenstein, Jürgen Becker 0001, Rainer Kress 0002, Helmut Reinig, Karin Schmidt	A Parallelizing Compilation Method for the Map-oriented Machine.	ASAP	1995	DBLP DOI BibTeX RDF
15	Debashis Bhattacharya, John P. Hayes	Designing for high-level test generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
15	J. L. Linn, C. D. Ardoin	All example of using pseudofields to eliminate version shuffling in horizontal code compaction.	MICRO	1989	DBLP DOI BibTeX RDF
15	Scott Davidson 0001	High level design automation tools (session overview).	ACM Conference on Computer Science	1985	DBLP DOI BibTeX RDF
15	Henry Fuchs, Jack Goldfeather, Jeff P. Hultquist, Susan Spach, John D. Austin, Frederick P. Brooks Jr., John G. Eyles, John Poulton	Fast spheres, shadows, textures, transparencies, and imgage enhancements in pixel-planes.	SIGGRAPH	1985	DBLP DOI BibTeX RDF