Search results for "ASICs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
90	Vikram Iyengar, Mark Johnson, Theo Anemikos, Bob Bassett, Mike Degregorio, Rudy Farmer, Gary Grise, Phil Stevens, Mark Taylor 0001, Frank Woytowich	Performance verification of high-performance ASICs using at-speed structural test.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	ASICs, structural test, performance verification, at-speed
60	Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh, Tobias G. Noll	Embedding of Dedicated High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	heterogeneous reconfigurable systems, dedicated ASICs, coprocessor board, CardBus, multimedia applications, text search
59	Yuejian Wu, Paul N. MacDonald	Testing ASICs with multiple identical cores.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
50	Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton	The impact of interconnect architecture on via-programmed structured ASICs (VPSAs).	FPGA	2010	DBLP DOI BibTeX RDF	structured asics, via programmable fabric
50	Herman Schmit, Amit Gupta, Radu Ciobanu	Placement challenges for structured ASICs.	ISPD	2008	DBLP DOI BibTeX RDF	field programmable gate arrays, placement, structured ASICs
50	Alex Orailoglu	Microarchitectural synthesis of gracefully degradable, dynamically reconfigurable ASICs.	ICCD	1996	DBLP DOI BibTeX RDF	microarchitectural synthesis, dynamically reconfigurable ASICs, fault-tolerance scheme, band reconfiguration, multiple permanent faults, associated high-level synthesis procedure, hardware rebinding, high-level synthesis, application specific integrated circuits, graceful degradation
50	Eric Chesters	Role of the verification team throughout the ASIC development life cycle.	DAC	2009	DBLP DOI BibTeX RDF	silicon validation, verification
50	Deepak D. Sherlekar	Design considerations for regular fabrics.	ISPD	2004	DBLP DOI BibTeX RDF	structured ASIC, regular fabric
49	Ashutosh Chakraborty, Anurag Kumar 0002, David Z. Pan	RegPlace: a high quality open-source placement framework for structured ASICs.	DAC	2009	DBLP DOI BibTeX RDF	global placement, regular ASIC, FPGA, placement, legalization, structured ASIC
49	Behrooz Zahiri	Structured ASICs: Opportunities and Challenges.	ICCD	2003	DBLP DOI BibTeX RDF
49	Yoshihiro Konno, Kazushi Nakamura, Tatsushige Bitoh, Koji Saga, Seiken Yano	A Consistent Scan Design System for Large-Scale ASICs.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF
41	Ashutosh Chakraborty, David Z. Pan	PASAP: power aware structured ASIC placement.	ISLPED	2010	DBLP DOI BibTeX RDF	structured ASICS, low power, placement, regular fabrics
41	Vikram Iyengar, Gary Grise, Mark Taylor 0001	A flexible and scalable methodology for GHz-speed structural test.	DAC	2006	DBLP DOI BibTeX RDF	asynchronous clock domains, deskewer, test waveform generator, ASICs, structural test, at-speed
41	Jean-Luis Dufour	Safety computations in integrated circuits.	VTS	1996	DBLP DOI BibTeX RDF	safety computations, software-based railway control systems, MATRA TRANSPORT, signature checking, coded processor, reliability, fault tolerant computing, logic testing, redundancy, integrated circuit testing, error correction codes, automatic testing, application specific integrated circuits, ASICs, integrated circuits, coprocessors, arithmetic coding, integrated circuit reliability
40	Alex Orailoglu	On-Line Fault Resilience Through Gracefully Degradable ASICs.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF	fault tolerant ICs, reconfigurable ASICs, high level synthesis, on-line test, graceful degradation
40	André DeHon, Brad L. Hutchings, Daryl Rudusky, James Hwang, Nikhil, Salil Raje, Adrian Stoica	What is the right model for programming and using modern FPGAs?	FPGA	2004	DBLP DOI BibTeX RDF
39	Tiago Muller Gil Cardoso, Leomar S. da Rosa Jr., Felipe de Souza Marques, Renato P. Ribas, André Inácio Reis	Speed-Up of ASICs Derived from FPGAs by Transistor Network Synthesis Including Reordering.	ISQED	2008	DBLP DOI BibTeX RDF	Transistor networks, logic synthesis, BDDs, Logical effort
39	Ian Kuon, Jonathan Rose	Measuring the Gap Between FPGAs and ASICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
39	Ian Kuon, Jonathan Rose	Measuring the gap between FPGAs and ASICs.	FPGA	2006	DBLP DOI BibTeX RDF	area comparison, delay comparison, power comparison, FPGA, ASIC
39	Minoru Watanabe, Fuminori Kobayashi	Optically Reconfigurable Gate Arrays vs. ASICs.	APCCAS	2006	DBLP DOI BibTeX RDF
39	Stephan Held, Bernhard Korte, Jens Maßberg, Matthias Ringe, Jens Vygen	Clock Scheduling and Clocktree Construction for High Performance ASICS.	ICCAD	2003	DBLP DOI BibTeX RDF	ASIC
39	Nikolaus Kerö, Thilo Sauter	Efficient Analysis of Mixed-Signal ASICs for Smart Sensors.	IEEE International Workshop on Rapid System Prototyping	2003	DBLP DOI BibTeX RDF
39	David A. Sunderland, Gary L. Duncan, Brad J. Rasmussen, Harry E. Nichols, Daniel T. Kain, Lawrence C. Lee 0002, Brian A. Clebowicz, Richard W. Hollis IV, Larry Wissel, Tad Wilder	Megagate ASICs for the Thuraya Satellite Digital Signal Processor (invited).	ISQED	2002	DBLP DOI BibTeX RDF	radiation tolerance, CCGA, reliability, DSP, ASIC, satellite communications, qualification
39	Daniela De Venuto, Michael J. Ohletz	On-Chip Test for Mixed-Signal ASICs using Two-Mode Comparators with Bias-Programmable Reference Voltages.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	mixed-signal ASIC, hardware conversion, GO/NOGO test, bias programming, DfT, power consumption, overhead
39	Holger Blume, Hans-Martin Blüthgen, Christiane Henning, Patrick Osterloh	Integration of High-Performance ASICs into Reconfigurable Systems Providing Additional Multimedia Functionality.	ASAP	2000	DBLP DOI BibTeX RDF	reconfigurable coprocessor board, multimedia, VLSI, DSP, digital signal processing, ASIC, CMOS
38	Gilles Bosco	Synthèse et décomposition technologique sur réseaux programmables et ASICs. (Synthesis and mapping on programmables devices and ASICs).		1996	RDF
31	Scott Davidson 0001	How to make your own processor architecture.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	system-on-chip computing, FPGAs, ASICs, processor architecture, processor design
31	Jürgen Teich, Tobias Blickle, Lothar Thiele	An evolutionary approach to system-level synthesis.	CODES	1997	DBLP DOI BibTeX RDF	architecture selection, cost constraints, graph-based mapping model, heterogeneous hardware/software architecture, optimal mapping, performance constraints, task-level specification mapping, video-codec implementations, genetic algorithms, scheduling, memories, ASICs, design space exploration, allocation, optimization problem, binding, buses, system-level synthesis, evolutionary approach, algorithm mapping, general-purpose processors, dedicated processors
31	Adel Baganne, Jean Luc Philippe, Eric Martin 0001	Hardware interface design for real time embedded systems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	real time digital signal processing, hardware interface design, codesign approach, storage components, hardware-software components, I/O data modeling style, hardware I/O transfer sequences, high level synthesis tool, GAUT, I/O transfer order, cosynthesis tool, real-time systems, ASICs, timing constraints, generic model, data communication, real time embedded systems, formal technique, interface specification, FFT algorithms, allocation problem
31	Sheng-Yih Guan, Avi Bleiweiss, Richard Lipes	Parallel implementation of volume rendering on Denali graphics systems.	IPPS	1995	DBLP DOI BibTeX RDF	computer graphic equipment, computer peripheral equipment, Denali graphics systems, 3D graphics systems, texture mapping capability, standard graphics pipeline, pipelined parallel architecture, Kubota Graphics Corporation, maximum intensity projection, iso-surface rendering, partitioning data allocation scheme, texture memory requirements, transformation and rasterization modules, frame buffer modules, parallel node, general purpose RISC processor, object parallelism, hardware ASICs, pixel memory, pixel parallelism, resource allocation, parallel architectures, volume rendering, pipeline processing, dynamic load balancing, image texture, parallel implementation, rendering (computer graphics), reduced instruction set computing, static load balancing
31	Jay K. Adams, Donald E. Thomas	Multiple-process behavioral synthesis for mixed hardware-software systems.	ISSS	1995	DBLP DOI BibTeX RDF	automated iterative improvement technique, concurrency optimization, concurrency tradeoffs, cost/performance ratio, hardware-software tradeoffs, mixed hardware-software systems, multiple-process behavioral synthesis, software engineering, resource allocation, concurrency control, controllers, optimisation, high level synthesis, logic design, multiprocessing systems, microprocessors, ASICs, application specific integrated circuits, ASIC, microprocessor chips, cost-benefit analysis
31	Ti-Yen Yen, Wayne H. Wolf	Sensitivity-driven co-synthesis of distributed embedded systems.	ISSS	1995	DBLP DOI BibTeX RDF	application software architecture, communicating periodic processes, gradient-search algorithm, local sensitivity, priority prediction method, process allocation, real-time distributed embedded systems, sensitivity-driven co-synthesis, software engineering, real-time systems, distributed processing, logic design, ASICs, ASIC, processor scheduling, performance estimates, process scheduling, arbitrary topology, communication links, CPU time, heterogeneous distributed systems
31	Ti-Yen Yen, Wayne H. Wolf	Performance estimation for real-time distributed embedded systems.	ICCD	1995	DBLP DOI BibTeX RDF	real-time distributed embedded systems, efficient analysis algorithm, application task, cosynthesis algorithms, bounding algorithms, performance evaluation, real-time systems, distributed processing, ASICs, data dependencies, execution time, performance estimation, CPUs, tight bounds, communication links
31	Raminder Singh Bajwa, Robert Michael Owens, Mary Jane Irwin	The MGAP's programming environment and the *C++ language.	ASAP	1995	DBLP DOI BibTeX RDF	MGAP's programming environment, *C++ language, workstation co-processor board, fine grain processors, custom ASICs, class concept, parallel data-types like bit, parallel processing, compiler, programming environments, application specific integrated circuits, high-level language, data-types, C language
31	Chao-Lieh Chen, Yau-Hwang Kuo	Fuzzy Hardware Synthesis with Generic LR Fuzzy Cells.	ANNES	1995	DBLP DOI BibTeX RDF	generic LR fuzzy cell, parallel inference, fuzzy ASICs, general-purposed fuzzy processors, current mode analog technology, fuzzy reasoning
30	Joachim Pistorius, Mike Hutton, Jay Schleicher, Mihail Iotov, Enoch Julias, Kumara Tharmalingam	Equivalence Verification of FPGA and Structured ASIC Implementations.	FPL	2007	DBLP DOI BibTeX RDF
30	Vikram Iyengar, Jinjun Xiong, Subbayyan Venkatesan, Vladimir Zolotov, David E. Lackey, Peter A. Habitz, Chandu Visweswariah	Variation-aware performance verification using at-speed structural test and statistical timing.	ICCAD	2007	DBLP DOI BibTeX RDF
30	Ron Wilson, Joe Gianelli, Chris Hamlin, Ken McElvain, Steve Leibson, Ivo Bolson, Rich Tobias, Raul Camposano	Structured/platform ASIC apprentices: which platform will survive your board room?	DAC	2005	DBLP DOI BibTeX RDF	programmable ASIC platforms, digital design
30	Ludovico de Souza, Philip J. Ryan, Jason Crawford, Kevin Wong, Gregory B. Zyner, Tom McDermott	Prototyping for the Concurrent Development.	FPL	2003	DBLP DOI BibTeX RDF
30	J. Bryan Lewis, Ivo Bolsens, Rudy Lauwereins, Chris Wheddon, Bhusan Gupta, Yankin Tanurhan	Reconfigurable SoC - What Will it Look Like?	DATE	2002	DBLP DOI BibTeX RDF
29	J. P. Grossman, Cliff Young, Joseph A. Bank, Kenneth M. Mackenzie, Doug Ierardi, John K. Salmon, Ron O. Dror, David E. Shaw	Simulation and embedded software development for Anton, a parallel machine with heterogeneous multicore ASICs.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	Anton, simulation, embedded software, special-purpose hardware
29	Andrew C. Ling, Deshanand P. Singh, Stephen Dean Brown	Incremental placement for structured ASICs using the transportation problem.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
29	Anatoly O. Melnyk, Andriy Salo	Automatic generation of ASICs.	AHS	2007	DBLP DOI BibTeX RDF
29	Vikram Iyengar, Kenneth Pichamuthu, Andrew Ferko, Frank Woytowich, David E. Lackey, Gary Grise, Mark Taylor 0001, Mike Degregorio, Steven F. Oakland	An Integrated Framework for At-Speed and ATE-Driven Delay Test of Contract-Manufactured ASICs.	VTS	2007	DBLP DOI BibTeX RDF
29	Nima Honarmand, Ali Shahabi, Hasan Sohofi, Maghsoud Abbaspour, Zainalabedin Navabi	High Level Synthesis of Degradable ASICs Using Virtual Binding.	VTS	2007	DBLP DOI BibTeX RDF
29	Régis Roubadia, Sami Ajram, Guy Cathébras	Low Power and Low Jitter Wideband Clock Synthesizers in CMOS ASICs.	PATMOS	2006	DBLP DOI BibTeX RDF
29	Norbert Pramstaller, Stefan Mangard, Sandra Dominikus, Johannes Wolkerstorfer	Efficient AES Implementations on ASICs and FPGAs.	AES Conference	2004	DBLP DOI BibTeX RDF	FPGA, Advanced Encryption Standard (AES), ASIC
29	Brady Benware	Achieving Sub 100 DPPM Defect Levels on VDSM and Nanometer ASICs.	ITC	2004	DBLP DOI BibTeX RDF
29	Pamela S. Gillis, Francis Woytowich, Andrew Ferko, Kevin McCauley	Low Overhead Delay Testing of ASICS.	ITC	2004	DBLP DOI BibTeX RDF
29	Ruchir Puri, David S. Kung 0001, Anthony D. Drumm	Fast and accurate wire delay estimation for physical synthesis of large ASICs.	ACM Great Lakes Symposium on VLSI	2002	DBLP DOI BibTeX RDF	placement driven synthesis, wire delay, estimation, integrated circuit design
29	Gulsun Yasar, Charles Chiu, Robert A. Proctor, James P. Libous	I/O Cell Placement and Electrical Checking Methodology for ASICs with Peripheral I/Os.	ISQED	2001	DBLP DOI BibTeX RDF
29	Mitrajit Chatterjee, Savita Banerjee, Dhiraj K. Pradhan	Buffer Assignment Algorithms on Data Driven ASICs.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	throughput, Application specific integrated circuits, buffers, data flow graph, wave-pipelining, data driven architecture
29	Thomas Meincke, Ahmed Hemani, Shashi Kumar, Peeter Ellervee, Johnny Öberg, Thomas Olsson 0001, Peter Nilsson 0001, Dan Lindqvist, Hannu Tenhunen	Globally asynchronous locally synchronous architecture for large high-performance ASICs.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
29	Josef Schmid, Joachim Knäblein	Advanced Synchronous Scan Test Methodology for Multi Clock Domain ASICs.	VTS	1999	DBLP DOI BibTeX RDF
29	Patrick Schaumont, Serge Vernalde, Luc Rijnders, Marc Engels, Ivo Bolsens	A Programming Environment for the Design of Complex High Speed ASICs.	DAC	1998	DBLP DOI BibTeX RDF	C++, congestion, global routing, quadratic placement, routing models, supply-demand, relaxed pins
29	Adrian Evans, Allan Silburt, Gary Vrckovnik, Thane Brown, Mario Dufresne, Geoffrey Hall, Tung Ho, Ying Liu	Functional Verification of Large ASICs.	DAC	1998	DBLP DOI BibTeX RDF	ASIC verification, simulation, emulation
29	Harry Hollander, Bradley S. Carlson, Toby D. Bennett	Synthesis of SEU-tolerant ASICs using concurrent error correction.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	radiation hardening (electronics), SEU-tolerant ASIC synthesis, single error correction/double error detection Hamming code, delay overhead, memory element set partitioning, error correction codes, sequential circuits, sequential circuit, application specific integrated circuits, logic CAD, circuit layout CAD, single event upsets, logic partitioning, Hamming codes, fault tolerant design, area overhead, memory elements, design experiments, concurrent error correction
29	Marley M. B. R. Vellasco, Philip C. Treleaven	The Generic Neuron Architectural Framework for the Automatic Generation of ASICs.	IWANN	1993	DBLP DOI BibTeX RDF
29	Roger Perry	IDDQ testing in CMOS digital ASICs.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	early life failures, I DDQ current, stuck-at fault, bridging fault, Automatic test program generation
22	John C. Lach, Vinu Vijay Kumar	Application-Specific Product Generics.	Computer	2009	DBLP DOI BibTeX RDF	Nonrecurring engineering costs, FPGAs, High-level synthesis, ASICs
22	Abdelhafid Bouhraoua, Muhammad E. S. Elrabaa	Addressing Heterogeneous Bandwidth Requirements in Modified Fat-Tree Networks-on-Chips.	DELTA	2008	DBLP DOI BibTeX RDF	Routing, Interconnection Networks, Systems-on-Chip, Networks-On-Chip, ASICs, Fat Tree
22	Richard H. Stern	West Coast Federal Appeals Court Upholds Chip Protection Act Violation Finding.	IEEE Micro	2007	DBLP DOI BibTeX RDF	antitrust violation, Semiconductor Chip Protection Act, chip piracy, monopoly, Altera, Clear Logic, reverse engineering, ASICs, law, bitstream
22	Michele Borgatti, Lorenzo Cali, Guido De Sandre, Benoit Forêt, David Iezzi, Francesco Lertora, Gilberto Muzzi, Marco Pasotti, Marco Poles, Pier Luigi Rolandi	A reconfigurable signal processing IC with embedded FPGA and multi-port flash memory.	DAC	2003	DBLP DOI BibTeX RDF	field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), reconfigurable architectures, integrated circuit design, multimedia computing, digital signal processors
22	Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif	An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.	ISPD	2002	DBLP DOI BibTeX RDF	adjoint sensitivity, optimization, placement, ASICs, decoupling capacitor, power grid noise
22	Ioannis Andreadis, Ioannis Karafyllidis, Panagiotis Tzionas, Adonios Thanailakis, Philippos Tsalides	A new hardware module for automated visual inspection based on a cellular automaton architecture.	J. Intell. Robotic Syst.	1996	DBLP DOI BibTeX RDF	detection of uncoated areas, cellular automata, ASICs, Visual inspection
20	Jason Helge Anderson, Chirag Ravishankar	FPGA power reduction by guarded evaluation.	FPGA	2010	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping
20	Husain Parvez, Zied Marrakchi, Habib Mehrez	Heterogeneous-ASIF: an application specific inflexible FPGA using heterogeneous logic blocks (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	asif, fpga, architecture, application specific, cad
20	Kevin Fan, Manjunath Kudlur, Ganesh S. Dasika, Scott A. Mahlke	Bridging the computation gap between programmable processors and hardwired accelerators.	HPCA	2009	DBLP DOI BibTeX RDF
20	William J. Dally, James D. Balfour, David Black-Schaffer, James Chen, R. Curtis Harting, Vishal Parikh, JongSoo Park, David Sheffield	Efficient Embedded Computing.	Computer	2008	DBLP DOI BibTeX RDF
20	Michael T. Frederick, Arun K. Somani	Beyond the arithmetic constraint: depth-optimal mapping of logic chains in LUT-based FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	carry chain, depth optimal mapping, logic chain
20	Kevin Fan, Hyunchul Park 0001, Manjunath Kudlur, Scott A. Mahlke	Modulo scheduling for highly customized datapaths to increase hardware reusability.	CGO	2008	DBLP DOI BibTeX RDF	programmable asic, modulo scheduling, loop accelerator
20	Mythri Alle, Keshavan Varadarajan, Ramesh C. Ramesh, Joseph Nimmy, Alexander Fell, Adarsha Rao, S. K. Nandy 0001, Ranjani Narayan	Synthesis of application accelerators on Runtime Reconfigurable Hardware.	ASAP	2008	DBLP DOI BibTeX RDF
20	Philip Heng Wai Leong	Recent Trends in FPGA Architectures and Applications.	DELTA	2008	DBLP DOI BibTeX RDF	FPGA, applications
20	Manuel Saldaña, Lesley Shannon, Jia Shuo Yue, Sikang Bian, John Craig, Paul Chow	Routability of Network Topologies in FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
20	Shiv Balakrishnan, Chris Eddington	Efficient DSP algorithm development for FPGA and ASIC technologies.	VLSI-SoC	2007	DBLP DOI BibTeX RDF
20	Suresh Srinivasan, Prasanth Mangalagiri, Yuan Xie 0001, Narayanan Vijaykrishnan	FPGA routing architecture analysis under variations.	ICCD	2007	DBLP DOI BibTeX RDF
20	Manuel Saldaña, Lesley Shannon, Paul Chow	The routability of multiprocessor network topologies in FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
20	Yuan Lin 0002, Scott A. Mahlke, Trevor N. Mudge, Chaitali Chakrabarti, Alastair Reid 0001, Krisztián Flautner	Design and Implementation of Turbo Decoders for Software Defined Radio.	SiPS	2006	DBLP DOI BibTeX RDF
20	Jae-Jin Lee, Gi-Yong Song	Super Semi-systolic Array-Based Application-Specific PLD Architecture.	ARC	2006	DBLP DOI BibTeX RDF
20	Manoj Ampalam, Montek Singh	Counterflow pipelining: architectural support for preemption in asynchronous systems using anti-tokens.	ICCAD	2006	DBLP DOI BibTeX RDF
20	Manuel Saldaña, Lesley Shannon, Paul Chow	The routability of multiprocessor network topologies in FPGAs.	SLIP	2006	DBLP DOI BibTeX RDF	FPGA, multiprocessor, network-on-chip, topology, interconnect
20	Arran Derbyshire, Tobias Becker, Wayne Luk	Incremental elaboration for run-time reconfigurable hardware designs.	CASES	2006	DBLP DOI BibTeX RDF	incremental elaboration, run-time reconfiguration, hardware compilation
20	Byeong Kil Lee, Lizy Kurian John	Implications of Executing Compression and Encryption Applications on General Purpose Processors.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	Media compression, memory behavior, MediaZip benchmark, overhead memory bandwidth, encryption, encoding, decoding, workload characterization, decryption
20	Tianpei Zhang, Sachin S. Sapatnekar	Buffering global interconnects in structured ASIC design.	ASP-DAC	2005	DBLP DOI BibTeX RDF
20	Jens Franke, Thorsten Kleinjung, Christof Paar, Jan Pelzl, Christine Priplata, Colin Stahlke	SHARK: A Realizable Special Hardware Sieving Device for Factoring 1024-Bit Integers.	CHES	2005	DBLP DOI BibTeX RDF	GNFS, lattice sieving, RSA 1024 bit, Integer factorization, special hardware
20	David G. Chinnery, Kurt Keutzer	Closing the power gap between ASIC and custom: an ASIC perspective.	DAC	2005	DBLP DOI BibTeX RDF	power, energy, custom, ASIC, comparison, standard cell
20	George Lawton	Will Network Processor Units Live Up to Their Promise?	Computer	2004	DBLP DOI BibTeX RDF
20	Raul Camposano	Will the ASIC survive?	SBCCI	2004	DBLP DOI BibTeX RDF
20	David Wentzlaff, Anant Agarwal	A Quantitative Comparison of Reconfigurable, Tiled, and Conventional Architectures on Bit-Level Computation.	FCCM	2004	DBLP DOI BibTeX RDF
20	Binu K. Mathew, Al Davis, Michael A. Parker	A low power architecture for embedded perception.	CASES	2004	DBLP DOI BibTeX RDF	computer vision, embedded systems, speech recognition, perception, low power design, VLIW, stream processor
20	R. Reed Taylor, Herman Schmit	Enabling energy efficiency in via-patterned gate array devices.	DAC	2004	DBLP DOI BibTeX RDF	VPGA, optimization, low-power, power, voltage scaling, structured ASIC
20	Timothy Sherwood, George Varghese, Brad Calder	A Pipelined Memory Architecture for High Throughput Network Processors.	ISCA	2003	DBLP DOI BibTeX RDF
20	Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung 0001, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni	Pushing ASIC performance in a power envelope.	DAC	2003	DBLP DOI BibTeX RDF	low-power, ASIC, high-performance, design optimization
20	Byeong Kil Lee, Lizy Kurian John	Implications of Programmable General Purpose Processors for Compression/Encryption Applications.	ASAP	2002	DBLP DOI BibTeX RDF
20	Russell Tessier, Wayne P. Burleson	Reconfigurable Computing for Digital Signal Processing: A Survey.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	FPGA, survey, reconfigurable computing, signal processing
20	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO-BIST: A framework for testability analysis and optimization forbuilt-in self-test of RTL circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
20	Simon Leung, Adam Postula, Ahmed Hemani	Development of Programmable Architecture for Base-Band Processing.	EUROMICRO	2000	DBLP DOI BibTeX RDF
20	Ho-Sik Seok, Kwang-Ju Lee, Byoung-Tak Zhang, Dong-Wook Lee, Kwee-Bo Sim	Genetic Programming of Process Decomposition Strategies for Evolvable Hardware.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
20	Srivaths Ravi 0001, Ganesh Lakshminarayana, Niraj K. Jha	TAO-BIST: A Framework for Testability Analysis and Optimizationb of RTL Circuits for BIST.	VTS	1999	DBLP DOI BibTeX RDF
20	Al Bailey, Tim Lada, Jim Preston	Collateral ASIC Test.	IEEE Des. Test Comput.	1997	DBLP DOI BibTeX RDF