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Publication years (Num. hits)
1956-1965 (16) 1966-1978 (17) 1979-1985 (18) 1986-1988 (22) 1989-1990 (18) 1991-1992 (17) 1993 (18) 1994-1995 (37) 1996 (28) 1997 (35) 1998 (34) 1999 (51) 2000 (29) 2001 (59) 2002 (63) 2003 (88) 2004 (70) 2005 (112) 2006 (121) 2007 (110) 2008 (107) 2009 (60) 2010 (49) 2011 (54) 2012 (52) 2013 (56) 2014 (63) 2015 (85) 2016 (69) 2017 (83) 2018 (77) 2019 (83) 2020 (94) 2021 (86) 2022 (68) 2023 (93) 2024 (15)
Publication types (Num. hits)
article(887) inproceedings(1269) phdthesis(1)
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Found 2158 publication records. Showing 2157 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
105Yiran Chen 0001, Hai Li 0001, Jing Li 0073, Cheng-Kok Koh Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF variable-latency adder (VL-adder), negative bias temperature instability (NBTI)
94Krister Landernäs, Johnny Holmberg, Mark Vesterbacka A high-speed low-latency digit-serial hybrid adder. Search on Bibsonomy ISCAS (3) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
92Yu-Ting Pai, Yu-Kumg Chen The Fastest Carry Lookahead Adder. Search on Bibsonomy DELTA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF central processing unit, integrated circuit, adder, gate delay, carry lookahead adder
85Behnam Amelifard, Farzan Fallah, Massoud Pedram Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders. Search on Bibsonomy ISQED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
85Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld Modulo p=3 Checking for a Carry Select Adder. Search on Bibsonomy J. Electron. Test. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF concurrent checking, modulo checking, carry select adder
84Ahmad A. Hiasat High-Speed and Reduced-Area Modular Adder Structures for RNS. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2002 DBLP  DOI  BibTeX  RDF modular adder, hardware requirements, VLSI, Computer arithmetic, Residue Number System, time delay, carry-lookahead adder
81Sumeer Goel, Ashok Kumar 0001, Magdy A. Bayoumi Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
78Sabyasachi Das, Sunil P. Khatri A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
78Jong-Suk Lee, Dong Sam Ha High Speed 1-bit Bypass Adder Design for Low Precision Additions. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
78Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis A Low-Power Carry Skip Adder with Fast Saturation. Search on Bibsonomy ASAP The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
78Jerry W. Bruce, Mitchell A. Thornton, L. Shivakumaraiah, P. S. Kokate, X. Li Efficient Adder Circuits Based on a Conservative Reversible Logic Gate. Search on Bibsonomy ISVLSI The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
78Youngjoon Kim, Ki-Hyuk Sung, Lee-Sup Kim A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme. Search on Bibsonomy ISCAS (1) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
76Riyaz A. Patel, Mohammed Benaissa, Said Boussakta Fast Modulo 2n - (2n-2+1) Addition: A New Class of Adder for RNS. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2007 DBLP  DOI  BibTeX  RDF modular adder, VLSI, Computer arithmetic, residue number system, parallel-prefix adder
75Johannes Grad, James E. Stine New algorithms for carry propagation. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF carry propagate addition, conditional sum adder, hybrid adder, ling adder, pseudo-complements, reed adder, domino logic, carry-skip adder
73Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy 0001 Fine-Grained Redundancy in Adders. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
70Himanshu Thapliyal, M. B. Srinivas A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
70Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld A Modulo p Checked Self-Checking Carry Select Adder. Search on Bibsonomy IOLTS The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
70Oscal T.-C. Chen, Robin R.-B. Sheen, S. Wang A low-power adder operating on effective dynamic data ranges. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
70Youngjoon Kim, Lee-Sup Kim A low power carry select adder with reduced area. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
70R. Shalem, Lizy Kurian John, Eugene John A Novel Low Power Energy Recovery Full Adder Cell. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
69Ahmet Akkas Dual-Mode Quadruple Precision Floating-Point Adder. Search on Bibsonomy DSD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Quadruple precision, dualmode, computer arithmetic, floating-point, adder, double precision
69Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, Cheng-Chew Lim Reduced Latency IEEE Floating-Point Standard Adder Architectures. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1999 DBLP  DOI  BibTeX  RDF VLSI, floating-point, adder, arithmetic
62Jeong-Ho Han, In-Cheol Park FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
62Michael Kirkedal Thomsen, Holger Bock Axelsen Parallel Optimization of a Reversible (Quantum) Ripple-Carry Adder. Search on Bibsonomy UC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF quantum computing, adders, circuits, Reversible computing
62Jeong-Ho Han, In-Cheol Park Digital filter synthesis considering multiple adder graphs for a coefficient. Search on Bibsonomy ICCD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
62Himanshu Thapliyal, A. Prasad Vinod 0001 Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
62Ge Yang 0004, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang A 32-bit carry lookahead adder using dual-path all-N logic. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
62Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham Constructing zero-deficiency parallel prefix adder of minimum depth. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
62Vitalij Ocheretnij, Daniel Marienfeld, Egor S. Sogomonyan, Michael Gössel Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits. Search on Bibsonomy IOLTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
62Ahmed M. Shams, Tarek Darwish, Magdy A. Bayoumi Performance analysis of low-power 1-bit CMOS full adder cells. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
62Neil Burgess The Flagged Prefix Adder and its Applications in Integer Arithmetic. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF prefix adders, absolute difference, end-around carry, computer arithmetic
62M. C. Mekhallalati, M. K. Ibrahim New high radix maximally-redundant signed digit adder. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
61André Silva, Eduardo A. C. da Costa, Sérgio J. M. de Almeida, Marcelo Schiavon Porto, Sergio Bampi High performance motion estimation architecture using efficient adder-compressors. Search on Bibsonomy SBCCI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF adder-compressor, motion estimation, fast algorithm
61Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello New performance/power/area efficient, reliable full adder design. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF d3l, reliability, dynamic, full-adder, sub-threshold
61Yan Sun, Xin Zhang, Xi Jin High-Performance Carry Select Adder Using Fast All-One Finding Logic. Search on Bibsonomy Asia International Conference on Modelling and Simulation The full citation details ... 2008 DBLP  DOI  BibTeX  RDF fast all-one finding circuit, add-one circuit, carry-select adder
61Andreas Herrfeld, Siegbert Hentschke Ternary Multiplication Circuits Using 4-Input Adder Cells and Carry Look-Ahead. Search on Bibsonomy ISMVL The full citation details ... 1999 DBLP  DOI  BibTeX  RDF MVL, ternary adder, ternary multiplication, VLSI, multiple valued-logic
61David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha The Half-Adder Form and Early Branch Condition Resolution. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1997 DBLP  DOI  BibTeX  RDF half-adder form, branch conditions, early zero detection, carry generation detection, addition, subtraction
60Matthew M. Ziegler, Mircea R. Stan A Unified Design Space for Regular Parallel Prefix Adders. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Kogge-Stone adder, Han-Carlson adder, Brent-Kung adder, parallel prefix adder
60Akito Sakurai, Saburo Muroga Parallel Binary Adders with a Minimum Number of Connections. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1983 DBLP  DOI  BibTeX  RDF ripple adder, Adder with a minimum number of connections, minimal adder, NOR gates, parallel adder, logic design
60Andrew Beaumont-Smith, Neil Burgess A GaAs 32-bit Adder. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1997 DBLP  DOI  BibTeX  RDF high speed adder, VLSI, low power, adder, GaAs, Gallium Arsenide
58Vitit Kantabutra A Recursive Carry-Lookahead/Carry-Select Hybrid Adder. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1993 DBLP  DOI  BibTeX  RDF recursive carry-lookahead/carry-select hybrid adder, double-precision mantissas, spanning tree carry lookahead adder, redundant cell adder, Am29050 microprocessor, Manchester carry chains, delays, adders
57Bernd Becker 0001, Reiner Kolla On the Construction of Optimal Time Adders (Extended Abstract). Search on Bibsonomy STACS The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
54Jianhua Liu, Yi Zhu 0002, Haikun Zhu, Chung-Kuan Cheng, John Lillis Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF optimum prefix adders, static power consumptions, dynamic power consumptions, high-level synthesis, integer linear programming, buffer insertion, gate sizing, power models, ASIC designs, parallel prefix adder, binary adder
54Wen-Chang Yeh, Chein-Wei Jen High-Speed Booth Encoded Parallel Multiplier Design. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Final adder, multiple-level conditional-sum adder and parallel multiplier, Booth encoding
54Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
54Tzu-Yuan Kuo, Jinn-Shyan Wang A low-voltage latch-adder based tree multiplier. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
54Liang-Kai Wang, Michael J. Schulte Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
54Vibhuti B. Dave, Erdal Oruklu, Jafar Saniie Design and Synthesis of a Three Input Flagged Prefix Adder. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
54Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu The new architecture of radix-4 Chinese abacus adder. Search on Bibsonomy ISMVL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
54Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho A high speed and energy efficient full adder design using complementary & level restoring carry logic. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
54Deepanjan Datta, Samiran Ganguly Design of Multi-bit SET Adder and Its Fault Simulation. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
54Yijun Liu, Stephen B. Furber The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics. Search on Bibsonomy PATMOS The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
54Egor S. Sogomonyan, Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel A New Self-Checking Sum-Bit Duplicated Carry-Select Adder. Search on Bibsonomy DATE The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
54Kai Chirca, Michael J. Schulte, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis A Static Low-Power, High-Performance 32-bit Carry Skip Adder. Search on Bibsonomy DSD The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
54Neil Burgess PAPA - Packed Arithmetic on a Prefix Adder for Multimedia Applications. Search on Bibsonomy ASAP The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
54Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan Partially Duplicated Code-Disjoint Carry-Skip Adder. Search on Bibsonomy DFT The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
54Ayman A. Fayed, Magdy A. Bayoumi A low power 10-transistor full adder cell for embedded architectures. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
54Hanan A. Mahmoud, Magdy A. Bayoumi A 10-transistor low-power high-speed full adder cell. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
54Gin Yee, Carl Sechen Clock-Delayed Domino for Adder and Combinational Logic Desig. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
53Parag K. Lala, Alvernon Walker On-Line Error Detectable Carry-Free Adder Design. Search on Bibsonomy DFT The full citation details ... 2001 DBLP  DOI  BibTeX  RDF carry-free adder, signed binary digits, 1-out-of-3 code, on-line error detection
53Nestoras Tzartzanis, William C. Athas Design and analysis of a low-power energy-recovery adder. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF energy-recovery adder, frequency range, VLSI, VLSI, delays, logic CAD, circuit analysis computing, integrated circuit design, adders, CMOS logic circuits, CMOS logic circuits, circuit CAD, SPICE, SPICE simulation, delay time, energy dissipation
51Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy 0001 Low-power carry-select adder using adaptive supply voltage based on input vector patterns. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF adaptive supply voltage, low power adder, carry-select adder
51Colleen van Lent, Adder Argueta, Russel Casella, Nate Jahns Robots in Education: Student Perspectives from the Classroom and the Field. Search on Bibsonomy AAAI Spring Symposium: Semantic Scientific Knowledge Integration The full citation details ... 2007 DBLP  BibTeX  RDF
49Erdal Oruklu, Vibhuti B. Dave, Jafar Saniie Performance analysis of flagged prefix adders with logical effort. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
49Jeong-Gun Lee, Jeong-A Lee, Byeong-Seok Lee, Milos D. Ercegovac A Design Method for Heterogeneous Adders. Search on Bibsonomy ICESS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
49Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang A micropower low-voltage multiplier with reduced spurious switching. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
49Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures. Search on Bibsonomy IWANN The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
49Jin-Fu Li 0001, Chih-Chiang Hsu Efficient Test Methodologies for Conditional Sum Adders. Search on Bibsonomy Asian Test Symposium The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
49Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald Self-Timed Carry-Lookahead Adders. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF delay-insenstive circuits, tree iterative circuits, CMOS, Self-timed circuits, carry-lookahead adders
49Yirng-An Chen, Randal E. Bryant Verification of Floating-Point Adders. Search on Bibsonomy CAV The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
49Ravichandran Ramachandran, Shih-Lien Lu Efficient arithmetic using self-timing. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
48David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha Early Zero Detection. Search on Bibsonomy ICCD The full citation details ... 1996 DBLP  DOI  BibTeX  RDF half-adder form, branch penalties, branch resolution, zero detection, speculative execution, ILP
46Keivan Navi, Daniel Etiemble From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators. Search on Bibsonomy ISMVL The full citation details ... 1995 DBLP  DOI  BibTeX  RDF multivalued current mode CMOS circuits, voltage mode CMOS arithmetic operators, 3-valued current mode CMOS 2-input BSC adder, CMOS binary 4-2 counter, 1-digit Avizienis-like adder, adders, CMOS integrated circuits, integrated logic circuits, multivalued logic circuits, ternary logic, redundant number representation
46Mitra Mirhassani Mixed-signal CVNS adder for two-operand binary addition. Search on Bibsonomy EIT The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
46Fekri Kharbash, Ghulam M. Chaudhry Reliable Binary Signed Digit Number Adder Design. Search on Bibsonomy ISVLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
46Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, Si-Ying Chen Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection. Search on Bibsonomy SiPS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
46Charles Tsen, Sonia González-Navarro, Michael J. Schulte Hardware design of a Binary Integer Decimal-based floating-point adder. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
46Joo-Young Kim 0001, Kangmin Lee, Hoi-Jun Yoo A 372 ps 64-bit adder using fast pull-up logic in 0.18µm CMOS. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
46Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung, Ming-Chien Tsai High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability. Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
46Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang A review of 0.18-μm full adder performances for tree structured arithmetic circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
46Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan A new formulation of fast diminished-one multioperand modulo 2n/+1 adder. Search on Bibsonomy ISCAS (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
46Mawahib H. Sulieman, Valeriu Beiu Characterization of a 16-bit threshold logic single-electron technology adder. Search on Bibsonomy ISCAS (3) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
46Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities. Search on Bibsonomy IOLTS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
46Hafiz Md. Hasan Babu, Md. Rafiqul Islam 0001, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury Reversible Logic Synthesis for Minimization of Full-Adder Circuit. Search on Bibsonomy DSD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
46Yngvar Berg, Snorre Aunet, Øivind Næss, O. Hagen, Mats Høvin A novel floating-gate multiple-valued CMOS full-adder. Search on Bibsonomy ISCAS (1) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
46R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah A Low Power Approach to Floating Point Adder Design for DSP Applications. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF digital-CMOS, power-consumption-model, VLSI, low-power-design, computer-arithmetic, floating-point, switching-activity
46Vitalij Ocheretnij, Egor S. Sogomonyan, Michael Gössel A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes. Search on Bibsonomy Asian Test Symposium The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
46Matthew M. Ziegler, Mircea Stan Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product. Search on Bibsonomy ISCAS (2) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
46Hanho Lee, Gerald E. Sobelman A New Low-Voltage Full Adder Circuit. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
46Mahmoud A. Manzoul A quaternary complex number CCD adder (abstract only). Search on Bibsonomy ACM Conference on Computer Science The full citation details ... 1987 DBLP  DOI  BibTeX  RDF
45Daniel E. Atkins, Shauchi Ong Time-Component Complexity of Two Approaches to Multioperand Binary Addition. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1979 DBLP  DOI  BibTeX  RDF time-component complexity, Adder tree, multioperand addition, carry-save adder, carry-lookahead adder, binary addition
44Dong-Yu Zheng, Yan Sun, Shao-Qing Li, Liang Fang A 485ps 64-Bit Parallel Adder in 0.18mum CMOS. Search on Bibsonomy J. Comput. Sci. Technol. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF semi-dynamic, sparse-tree, parallel prefix adder
44Mariano Aguirre, Mónico Linares Aranda An alternative logic approach to implement high-speed low-power full adder cells. Search on Bibsonomy SBCCI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF low-power, high-speed, full adder
44Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao 64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi. Search on Bibsonomy ISVLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF CPL, conditional sum adder, low-threshold voltage, differential-end, VLSI design, low-voltage
44Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even Pipelined Packet-Forwarding Floating Point: II. An Adder. Search on Bibsonomy IEEE Symposium on Computer Arithmetic The full citation details ... 1997 DBLP  DOI  BibTeX  RDF pipelined packet forwarding floating point, floating point addition algorithm, adder pipeline design, packet forwarding pipeline paradigm, data hazards, deeply pipelined floating point pipelines, four stage execution phase pipeline, short clock period, fifteen logic levels, addition algorithm, standard binary floating point format, standard IEEE 754 rounded result, two cycle latency, cooperating multiplier pipeline, packet forwarding operand, IEEE 754 binary floating point compatibility, pipeline arithmetic
44Issam S. Abu-Khater, Abdellatif Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan Circuit/architecture for low-power high-performance 32-bit adder. Search on Bibsonomy Great Lakes Symposium on VLSI The full citation details ... 1995 DBLP  DOI  BibTeX  RDF conditional sum architecture, CPL-like logic implementation, power supply voltage, minimum size, optimized speed, 1 to 3.3 V, logic design, CMOS, integrated circuit design, adders, adder, CMOS logic circuits, circuit optimisation, 32 bit
43Dilip Kumar Gayen, Arunava Bhattacharyya, Chinmoy Taraphdar, Rajat Kumar Pal, Jitendra Nath Roy All-Optical Binary-Coded Decimal Adder with a Terahertz Optical Asymmetric Demultiplexer. Search on Bibsonomy Comput. Sci. Eng. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF Terahertz optical asymmetric demultiplexer, optical full adder, optical binary-coded decimal adder, optical switch
43Chien-In Henry Chen, Anup Kumar Comments on "Area-Time Optimal Adder Design". Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF VLSI parallel adder, optimal 32-bit fast carry generator, fast carry generator, BiCMOS drivers, optimal adder design, adders, carry logic, critical path delay
43Belle W. Y. Wei, Clark D. Thompson Area-Time Optimal Adder Design. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1990 DBLP  DOI  BibTeX  RDF area-time optimal adder design, VLSI parallel adder, component cells, static CMOS, floating-point processor, 66 bit, VLSI, dynamic programming, dynamic programming, logic design, digital arithmetic, adders, CMOS integrated circuits, modular design
43Robert W. Doran Variants of an Improved Carry Look-Ahead Adder. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1988 DBLP  DOI  BibTeX  RDF look-ahead carry, adder, adders, variation, improved, carry look-ahead adder
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