Search results for "Adder"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
105	Yiran Chen 0001, Hai Li 0001, Jing Li 0073, Cheng-Kok Koh	Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI.	ISLPED	2007	DBLP DOI BibTeX RDF	variable-latency adder (VL-adder), negative bias temperature instability (NBTI)
94	Krister Landernäs, Johnny Holmberg, Mark Vesterbacka	A high-speed low-latency digit-serial hybrid adder.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
92	Yu-Ting Pai, Yu-Kumg Chen	The Fastest Carry Lookahead Adder.	DELTA	2004	DBLP DOI BibTeX RDF	central processing unit, integrated circuit, adder, gate delay, carry lookahead adder
85	Behnam Amelifard, Farzan Fallah, Massoud Pedram	Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class Closing the Gap between Carry Select Adder and Ripple Carry Adder: A New Class of Low-Power High-Performance Adders.	ISQED	2005	DBLP DOI BibTeX RDF
85	Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld	Modulo p=3 Checking for a Carry Select Adder.	J. Electron. Test.	2006	DBLP DOI BibTeX RDF	concurrent checking, modulo checking, carry select adder
84	Ahmad A. Hiasat	High-Speed and Reduced-Area Modular Adder Structures for RNS.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	modular adder, hardware requirements, VLSI, Computer arithmetic, Residue Number System, time delay, carry-lookahead adder
81	Sumeer Goel, Ashok Kumar 0001, Magdy A. Bayoumi	Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
78	Sabyasachi Das, Sunil P. Khatri	A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
78	Jong-Suk Lee, Dong Sam Ha	High Speed 1-bit Bypass Adder Design for Low Precision Additions.	ISCAS	2007	DBLP DOI BibTeX RDF
78	Michael J. Schulte, Kai Chirca, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis	A Low-Power Carry Skip Adder with Fast Saturation.	ASAP	2004	DBLP DOI BibTeX RDF
78	Jerry W. Bruce, Mitchell A. Thornton, L. Shivakumaraiah, P. S. Kokate, X. Li	Efficient Adder Circuits Based on a Conservative Reversible Logic Gate.	ISVLSI	2002	DBLP DOI BibTeX RDF
78	Youngjoon Kim, Ki-Hyuk Sung, Lee-Sup Kim	A 1.67 GHz 32-bit pipelined carry-select adder using the complementary scheme.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
76	Riyaz A. Patel, Mohammed Benaissa, Said Boussakta	Fast Modulo 2n - (2n-2+1) Addition: A New Class of Adder for RNS.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	modular adder, VLSI, Computer arithmetic, residue number system, parallel-prefix adder
75	Johannes Grad, James E. Stine	New algorithms for carry propagation.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	carry propagate addition, conditional sum adder, hybrid adder, ling adder, pseudo-complements, reed adder, domino logic, carry-skip adder
73	Patrick Ndai, Shih-Lien Lu, Dinesh Somasekhar, Kaushik Roy 0001	Fine-Grained Redundancy in Adders.	ISQED	2007	DBLP DOI BibTeX RDF
70	Himanshu Thapliyal, M. B. Srinivas	A Novel Reversible TSG Gate and Its Application for Designing Reversible Carry Look-Ahead and Other Adder Architectures.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF
70	Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan, Daniel Marienfeld	A Modulo p Checked Self-Checking Carry Select Adder.	IOLTS	2003	DBLP DOI BibTeX RDF
70	Oscal T.-C. Chen, Robin R.-B. Sheen, S. Wang	A low-power adder operating on effective dynamic data ranges.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
70	Youngjoon Kim, Lee-Sup Kim	A low power carry select adder with reduced area.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
70	R. Shalem, Lizy Kurian John, Eugene John	A Novel Low Power Energy Recovery Full Adder Cell.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
69	Ahmet Akkas	Dual-Mode Quadruple Precision Floating-Point Adder.	DSD	2006	DBLP DOI BibTeX RDF	Quadruple precision, dualmode, computer arithmetic, floating-point, adder, double precision
69	Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, Cheng-Chew Lim	Reduced Latency IEEE Floating-Point Standard Adder Architectures.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF	VLSI, floating-point, adder, arithmetic
62	Jeong-Ho Han, In-Cheol Park	FIR Filter Synthesis Considering Multiple Adder Graphs for a Coefficient.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
62	Michael Kirkedal Thomsen, Holger Bock Axelsen	Parallel Optimization of a Reversible (Quantum) Ripple-Carry Adder.	UC	2008	DBLP DOI BibTeX RDF	quantum computing, adders, circuits, Reversible computing
62	Jeong-Ho Han, In-Cheol Park	Digital filter synthesis considering multiple adder graphs for a coefficient.	ICCD	2008	DBLP DOI BibTeX RDF
62	Himanshu Thapliyal, A. Prasad Vinod 0001	Transistor Realization of Reversible TSG Gate and Reversible Adder Architectures.	APCCAS	2006	DBLP DOI BibTeX RDF
62	Ge Yang 0004, Seong-Ook Jung, Kwang-Hyun Baek, Soo Hwan Kim, Suki Kim, Sung-Mo Kang	A 32-bit carry lookahead adder using dual-path all-N logic.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
62	Haikun Zhu, Chung-Kuan Cheng, Ronald L. Graham	Constructing zero-deficiency parallel prefix adder of minimum depth.	ASP-DAC	2005	DBLP DOI BibTeX RDF
62	Vitalij Ocheretnij, Daniel Marienfeld, Egor S. Sogomonyan, Michael Gössel	Self-Checking Code-Disjoint Carry-Select Adder with Low Area Overhead by Use of Add1-Circuits.	IOLTS	2004	DBLP DOI BibTeX RDF
62	Ahmed M. Shams, Tarek Darwish, Magdy A. Bayoumi	Performance analysis of low-power 1-bit CMOS full adder cells.	IEEE Trans. Very Large Scale Integr. Syst.	2002	DBLP DOI BibTeX RDF
62	Neil Burgess	The Flagged Prefix Adder and its Applications in Integer Arithmetic.	J. VLSI Signal Process.	2002	DBLP DOI BibTeX RDF	prefix adders, absolute difference, end-around carry, computer arithmetic
62	M. C. Mekhallalati, M. K. Ibrahim	New high radix maximally-redundant signed digit adder.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
61	André Silva, Eduardo A. C. da Costa, Sérgio J. M. de Almeida, Marcelo Schiavon Porto, Sergio Bampi	High performance motion estimation architecture using efficient adder-compressors.	SBCCI	2009	DBLP DOI BibTeX RDF	adder-compressor, motion estimation, fast algorithm
61	Sohan Purohit, Martin Margala, Marco Lanuzza, Pasquale Corsonello	New performance/power/area efficient, reliable full adder design.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	d3l, reliability, dynamic, full-adder, sub-threshold
61	Yan Sun, Xin Zhang, Xi Jin	High-Performance Carry Select Adder Using Fast All-One Finding Logic.	Asia International Conference on Modelling and Simulation	2008	DBLP DOI BibTeX RDF	fast all-one finding circuit, add-one circuit, carry-select adder
61	Andreas Herrfeld, Siegbert Hentschke	Ternary Multiplication Circuits Using 4-Input Adder Cells and Carry Look-Ahead.	ISMVL	1999	DBLP DOI BibTeX RDF	MVL, ternary adder, ternary multiplication, VLSI, multiple valued-logic
61	David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha	The Half-Adder Form and Early Branch Condition Resolution.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	half-adder form, branch conditions, early zero detection, carry generation detection, addition, subtraction
60	Matthew M. Ziegler, Mircea R. Stan	A Unified Design Space for Regular Parallel Prefix Adders.	DATE	2004	DBLP DOI BibTeX RDF	Kogge-Stone adder, Han-Carlson adder, Brent-Kung adder, parallel prefix adder
60	Akito Sakurai, Saburo Muroga	Parallel Binary Adders with a Minimum Number of Connections.	IEEE Trans. Computers	1983	DBLP DOI BibTeX RDF	ripple adder, Adder with a minimum number of connections, minimal adder, NOR gates, parallel adder, logic design
60	Andrew Beaumont-Smith, Neil Burgess	A GaAs 32-bit Adder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	high speed adder, VLSI, low power, adder, GaAs, Gallium Arsenide
58	Vitit Kantabutra	A Recursive Carry-Lookahead/Carry-Select Hybrid Adder.	IEEE Trans. Computers	1993	DBLP DOI BibTeX RDF	recursive carry-lookahead/carry-select hybrid adder, double-precision mantissas, spanning tree carry lookahead adder, redundant cell adder, Am29050 microprocessor, Manchester carry chains, delays, adders
57	Bernd Becker 0001, Reiner Kolla	On the Construction of Optimal Time Adders (Extended Abstract).	STACS	1988	DBLP DOI BibTeX RDF
54	Jianhua Liu, Yi Zhu 0002, Haikun Zhu, Chung-Kuan Cheng, John Lillis	Optimum Prefix Adders in a Comprehensive Area, Timing and Power Design Space.	ASP-DAC	2007	DBLP DOI BibTeX RDF	optimum prefix adders, static power consumptions, dynamic power consumptions, high-level synthesis, integer linear programming, buffer insertion, gate sizing, power models, ASIC designs, parallel prefix adder, binary adder
54	Wen-Chang Yeh, Chein-Wei Jen	High-Speed Booth Encoded Parallel Multiplier Design.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Final adder, multiple-level conditional-sum adder and parallel multiplier, Booth encoding
54	Mitra Mirhassani, Majid Ahmadi, Graham A. Jullien	Low-Power Mixed-Signal CVNS-Based 64-Bit Adder for Media Signal Processing.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
54	Tzu-Yuan Kuo, Jinn-Shyan Wang	A low-voltage latch-adder based tree multiplier.	ISCAS	2008	DBLP DOI BibTeX RDF
54	Liang-Kai Wang, Michael J. Schulte	Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
54	Vibhuti B. Dave, Erdal Oruklu, Jafar Saniie	Design and Synthesis of a Three Input Flagged Prefix Adder.	ISCAS	2007	DBLP DOI BibTeX RDF
54	Shu-Chung Yi, Kun-Tse Lee, Jin-Jia Chen, Chien-Hung Lin, Chuen-Ching Wang, Chin-Fa Hsieh, Chih-Yung Lu	The new architecture of radix-4 Chinese abacus adder.	ISMVL	2006	DBLP DOI BibTeX RDF
54	Jin-Fa Lin, Yin-Tsung Hwang, Ming-Hwa Sheu, Cheng-Che Ho	A high speed and energy efficient full adder design using complementary & level restoring carry logic.	ISCAS	2006	DBLP DOI BibTeX RDF
54	Deepanjan Datta, Samiran Ganguly	Design of Multi-bit SET Adder and Its Fault Simulation.	VLSI Design	2006	DBLP DOI BibTeX RDF
54	Yijun Liu, Stephen B. Furber	The Design of an Asynchronous Carry-Lookahead Adder Based on Data Characteristics.	PATMOS	2005	DBLP DOI BibTeX RDF
54	Egor S. Sogomonyan, Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel	A New Self-Checking Sum-Bit Duplicated Carry-Select Adder.	DATE	2004	DBLP DOI BibTeX RDF
54	Kai Chirca, Michael J. Schulte, John Glossner, Haoran Wang, Suman Mamidi, Pablo I. Balzola, Stamatis Vassiliadis	A Static Low-Power, High-Performance 32-bit Carry Skip Adder.	DSD	2004	DBLP DOI BibTeX RDF
54	Neil Burgess	PAPA - Packed Arithmetic on a Prefix Adder for Multimedia Applications.	ASAP	2002	DBLP DOI BibTeX RDF
54	Daniel Marienfeld, Vitalij Ocheretnij, Michael Gössel, Egor S. Sogomonyan	Partially Duplicated Code-Disjoint Carry-Skip Adder.	DFT	2002	DBLP DOI BibTeX RDF
54	Ayman A. Fayed, Magdy A. Bayoumi	A low power 10-transistor full adder cell for embedded architectures.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
54	Hanan A. Mahmoud, Magdy A. Bayoumi	A 10-transistor low-power high-speed full adder cell.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
54	Gin Yee, Carl Sechen	Clock-Delayed Domino for Adder and Combinational Logic Desig.	ICCD	1996	DBLP DOI BibTeX RDF
53	Parag K. Lala, Alvernon Walker	On-Line Error Detectable Carry-Free Adder Design.	DFT	2001	DBLP DOI BibTeX RDF	carry-free adder, signed binary digits, 1-out-of-3 code, on-line error detection
53	Nestoras Tzartzanis, William C. Athas	Design and analysis of a low-power energy-recovery adder.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	energy-recovery adder, frequency range, VLSI, VLSI, delays, logic CAD, circuit analysis computing, integrated circuit design, adders, CMOS logic circuits, CMOS logic circuits, circuit CAD, SPICE, SPICE simulation, delay time, energy dissipation
51	Hiroaki Suzuki, Woopyo Jeong, Kaushik Roy 0001	Low-power carry-select adder using adaptive supply voltage based on input vector patterns.	ISLPED	2004	DBLP DOI BibTeX RDF	adaptive supply voltage, low power adder, carry-select adder
51	Colleen van Lent, Adder Argueta, Russel Casella, Nate Jahns	Robots in Education: Student Perspectives from the Classroom and the Field.	AAAI Spring Symposium: Semantic Scientific Knowledge Integration	2007	DBLP BibTeX RDF
49	Erdal Oruklu, Vibhuti B. Dave, Jafar Saniie	Performance analysis of flagged prefix adders with logical effort.	ISCAS	2008	DBLP DOI BibTeX RDF
49	Jeong-Gun Lee, Jeong-A Lee, Byeong-Seok Lee, Milos D. Ercegovac	A Design Method for Heterogeneous Adders.	ICESS	2007	DBLP DOI BibTeX RDF
49	Kwen-Siong Chong, Bah-Hwee Gwee, Joseph Sylvester Chang	A micropower low-voltage multiplier with reduced spurious switching.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
49	Valeriu Beiu, Asbjørn Djupdal, Snorre Aunet	Ultra Low-Power Neural Inspired Addition: When Serial Might Outperform Parallel Architectures.	IWANN	2005	DBLP DOI BibTeX RDF
49	Jin-Fu Li 0001, Chih-Chiang Hsu	Efficient Test Methodologies for Conditional Sum Adders.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
49	Fu-Chiung Cheng, Stephen H. Unger, Michael Theobald	Self-Timed Carry-Lookahead Adders.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	delay-insenstive circuits, tree iterative circuits, CMOS, Self-timed circuits, carry-lookahead adders
49	Yirng-An Chen, Randal E. Bryant	Verification of Floating-Point Adders.	CAV	1998	DBLP DOI BibTeX RDF
49	Ravichandran Ramachandran, Shih-Lien Lu	Efficient arithmetic using self-timing.	IEEE Trans. Very Large Scale Integr. Syst.	1996	DBLP DOI BibTeX RDF
48	David Raymond Lutz, Doddaballapur Narasimha-Murthy Jayasimha	Early Zero Detection.	ICCD	1996	DBLP DOI BibTeX RDF	half-adder form, branch penalties, branch resolution, zero detection, speculative execution, ILP
46	Keivan Navi, Daniel Etiemble	From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators.	ISMVL	1995	DBLP DOI BibTeX RDF	multivalued current mode CMOS circuits, voltage mode CMOS arithmetic operators, 3-valued current mode CMOS 2-input BSC adder, CMOS binary 4-2 counter, 1-digit Avizienis-like adder, adders, CMOS integrated circuits, integrated logic circuits, multivalued logic circuits, ternary logic, redundant number representation
46	Mitra Mirhassani	Mixed-signal CVNS adder for two-operand binary addition.	EIT	2009	DBLP DOI BibTeX RDF
46	Fekri Kharbash, Ghulam M. Chaudhry	Reliable Binary Signed Digit Number Adder Design.	ISVLSI	2007	DBLP DOI BibTeX RDF
46	Su-Hon Lin, Ming-Hwa Sheu, Kuang-Hui Wang, Jun-Jie Zhu, Si-Ying Chen	Efficient VLSI Design of Modulo 2n-1 Adder Using Hybrid Carry Selection.	SiPS	2007	DBLP DOI BibTeX RDF
46	Charles Tsen, Sonia González-Navarro, Michael J. Schulte	Hardware design of a Binary Integer Decimal-based floating-point adder.	ICCD	2007	DBLP DOI BibTeX RDF
46	Joo-Young Kim 0001, Kangmin Lee, Hoi-Jun Yoo	A 372 ps 64-bit adder using fast pull-up logic in 0.18µm CMOS.	ISCAS	2006	DBLP DOI BibTeX RDF
46	Chiou-Kou Tung, Shao-Hui Shieh, Yu-Cherng Hung, Ming-Chien Tsai	High-Performance Low-Power Full-Swing Full Adder Cores with Output Driving Capability.	APCCAS	2006	DBLP DOI BibTeX RDF
46	Chip-Hong Chang, Jiangmin Gu, Mingyan Zhang	A review of 0.18-μm full adder performances for tree structured arithmetic circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
46	Bin Cao, Chip-Hong Chang, Thambipillai Srikanthan	A new formulation of fast diminished-one multioperand modulo 2n/+1 adder.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
46	Mawahib H. Sulieman, Valeriu Beiu	Characterization of a 16-bit threshold logic single-electron technology adder.	ISCAS (3)	2004	DBLP DOI BibTeX RDF
46	Gian Carlo Cardarilli, Marco Ottavi, Salvatore Pontarelli, Marco Re, Adelio Salsano	A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities.	IOLTS	2004	DBLP DOI BibTeX RDF
46	Hafiz Md. Hasan Babu, Md. Rafiqul Islam 0001, Ahsan Raja Chowdhury, Syed Mostahed Ali Chowdhury	Reversible Logic Synthesis for Minimization of Full-Adder Circuit.	DSD	2003	DBLP DOI BibTeX RDF
46	Yngvar Berg, Snorre Aunet, Øivind Næss, O. Hagen, Mats Høvin	A novel floating-gate multiple-valued CMOS full-adder.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
46	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah	A Low Power Approach to Floating Point Adder Design for DSP Applications.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	digital-CMOS, power-consumption-model, VLSI, low-power-design, computer-arithmetic, floating-point, switching-activity
46	Vitalij Ocheretnij, Egor S. Sogomonyan, Michael Gössel	A New Code-Disjoint Sum-Bit Duplicated Carry Look-Ahead Adder for Parity Codes.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
46	Matthew M. Ziegler, Mircea Stan	Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product.	ISCAS (2)	2001	DBLP DOI BibTeX RDF
46	Hanho Lee, Gerald E. Sobelman	A New Low-Voltage Full Adder Circuit.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF
46	Mahmoud A. Manzoul	A quaternary complex number CCD adder (abstract only).	ACM Conference on Computer Science	1987	DBLP DOI BibTeX RDF
45	Daniel E. Atkins, Shauchi Ong	Time-Component Complexity of Two Approaches to Multioperand Binary Addition.	IEEE Trans. Computers	1979	DBLP DOI BibTeX RDF	time-component complexity, Adder tree, multioperand addition, carry-save adder, carry-lookahead adder, binary addition
44	Dong-Yu Zheng, Yan Sun, Shao-Qing Li, Liang Fang	A 485ps 64-Bit Parallel Adder in 0.18mum CMOS.	J. Comput. Sci. Technol.	2007	DBLP DOI BibTeX RDF	semi-dynamic, sparse-tree, parallel prefix adder
44	Mariano Aguirre, Mónico Linares Aranda	An alternative logic approach to implement high-speed low-power full adder cells.	SBCCI	2005	DBLP DOI BibTeX RDF	low-power, high-speed, full adder
44	Kuo-Hsing Cheng, Shun-Wen Cheng, Che-Yu Liao	64-bit Low Threshold Voltage High-Speed Conditional Carry Adder by Complementary Pass-Transistor Logi.	ISVLSI	2004	DBLP DOI BibTeX RDF	CPL, conditional sum adder, low-threshold voltage, differential-end, VLSI design, low-voltage
44	Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even	Pipelined Packet-Forwarding Floating Point: II. An Adder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, floating point addition algorithm, adder pipeline design, packet forwarding pipeline paradigm, data hazards, deeply pipelined floating point pipelines, four stage execution phase pipeline, short clock period, fifteen logic levels, addition algorithm, standard binary floating point format, standard IEEE 754 rounded result, two cycle latency, cooperating multiplier pipeline, packet forwarding operand, IEEE 754 binary floating point compatibility, pipeline arithmetic
44	Issam S. Abu-Khater, Abdellatif Bellaouar, Mohamed I. Elmasry, Ran-Hong Yan	Circuit/architecture for low-power high-performance 32-bit adder.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	conditional sum architecture, CPL-like logic implementation, power supply voltage, minimum size, optimized speed, 1 to 3.3 V, logic design, CMOS, integrated circuit design, adders, adder, CMOS logic circuits, circuit optimisation, 32 bit
43	Dilip Kumar Gayen, Arunava Bhattacharyya, Chinmoy Taraphdar, Rajat Kumar Pal, Jitendra Nath Roy	All-Optical Binary-Coded Decimal Adder with a Terahertz Optical Asymmetric Demultiplexer.	Comput. Sci. Eng.	2011	DBLP DOI BibTeX RDF	Terahertz optical asymmetric demultiplexer, optical full adder, optical binary-coded decimal adder, optical switch
43	Chien-In Henry Chen, Anup Kumar	Comments on "Area-Time Optimal Adder Design".	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	VLSI parallel adder, optimal 32-bit fast carry generator, fast carry generator, BiCMOS drivers, optimal adder design, adders, carry logic, critical path delay
43	Belle W. Y. Wei, Clark D. Thompson	Area-Time Optimal Adder Design.	IEEE Trans. Computers	1990	DBLP DOI BibTeX RDF	area-time optimal adder design, VLSI parallel adder, component cells, static CMOS, floating-point processor, 66 bit, VLSI, dynamic programming, dynamic programming, logic design, digital arithmetic, adders, CMOS integrated circuits, modular design
43	Robert W. Doran	Variants of an Improved Carry Look-Ahead Adder.	IEEE Trans. Computers	1988	DBLP DOI BibTeX RDF	look-ahead carry, adder, adders, variation, improved, carry look-ahead adder