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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 6729 occurrences of 2700 keywords
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Results
Found 15248 publication records. Showing 15248 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
99 | Cheng-Wen Wu, Peter R. Cappello |
Easily Testable Iterative Logic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 39(5), pp. 640-652, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
easily testable iterative logic arrays, octagonally connected arrays, combinational arrays, inhomogeneous arrays, bilateral arrays, test complexity, pipelined arrays, logic testing, systolic arrays, upper bound, matrix multiplication, cellular arrays, combinatorial circuits, multidimensional arrays |
66 | Robert C. Minnick |
A Survey of Microcellular Research. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 14(2), pp. 203-241, 1967. The full citation details ...](Pics/full.jpeg) |
1967 |
DBLP DOI BibTeX RDF |
|
64 | Chun-Yuan Lin, Yeh-Ching Chung, Jen-Shiuh Liu |
Efficient Data Distribution Schemes for EKMR-Based Sparse Arrays on Distributed Memory Multicomputers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Supercomput. ![In: J. Supercomput. 34(3), pp. 291-313, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
data distribution schemes, data compression methods, sparse ratio, partition methods, Karnaugh map |
63 | Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis |
Testing combinational iterative logic arrays for realistic faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 35-41, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
combinational iterative logic arrays, realistic faults, two-dimensional logic arrays, one-dimensional logic arrays, n-pattern tests, linear-testability, efficient test set, ILA, VLSI, fault diagnosis, logic testing, integrated circuit testing, combinational circuits, cellular arrays, logic arrays, C-testability, cell fault model |
62 | PeiZong Lee, Zvi M. Kedem |
Mapping Nested Loop Algorithms into Multidimensional Systolic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 1(1), pp. 64-76, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
nested loop algorithms, multidimensional systolic arrays, correct transformation, programmable systolic arrays, general purpose programmable arrays, planar systolic array implementations, three-dimensional cube-graph algorithm, reindexed Warshall-Floyd path-finding algorithm, parallel algorithms, parallel processing, graph theory, matrix multiplication, data dependence, matrix algebra, cellular arrays, sufficient conditions, necessary conditions, algorithm transformations, automatic compilation |
60 | Javed Absar, Francky Catthoor |
Reuse analysis of indirectly indexed arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(2), pp. 282-305, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
indirectly indexed arrays, irregular access, reuse vector, data reuse, Scratch-pad |
56 | Sosina Martirosyan, Tran van Trung |
On t-Covering Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 32(1-3), pp. 323-339, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
t-covering arrays, perfect hash families, orthogonal arrays, algebraic-geometric codes |
51 | Dong Kyue Kim, Minhwan Kim, Heejin Park |
Linearized Suffix Tree: an Efficient Index Data Structure with the Capabilities of Suffix Trees and Suffix Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmica ![In: Algorithmica 52(3), pp. 350-377, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Index data structures, Suffix trees, Suffix arrays, String algorithms |
50 | José E. Moreira, Samuel P. Midkiff, Manish Gupta 0002 |
A comparison of three approaches to language, compiler, and library support for multidimensional arrays in Java. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Java Grande ![In: Proceedings of the ACM 2001 Java Grande Conference, Stanford University, California, USA, June 2-4, 2001, pp. 116-125, 2001, ACM, 1-58113-359-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Java |
49 | Steven J. E. Wilton |
Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2000, Monterey, CA, USA, February 10-11, 2000, pp. 67-74, 2000, ACM, 1-58113-193-3. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
49 | Steven J. E. Wilton |
SMAP: Heterogeneous Technology Mapping for Area Reduction in FPGAs with Embedded Memory Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the 1998 ACM/SIGDA Sixth International Symposium on Field Programmable Gate Arrays, FPGA 1998, Monterey, CA, USA, February 22-24, 1998, pp. 171-178, 1998, ACM, 0-89791-978-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
48 | Edwin Hsing-Mean Sha, Kenneth Steiglitz |
Reconfigurability and Reliability of Systolic/Wavefront Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 42(7), pp. 854-862, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
wavefront arrays, fault-tolerant redundant structures, reliable arrays, application graph, finitely reconfigurable, locally reconfigurable, reliability, lower bound, fault tolerant computing, reconfigurability, time complexity, systolic arrays, systolic arrays, reconfigurable architectures, dynamic graphs, bounded-degree graphs |
48 | Viktor K. Prasanna, Yu-Chen Tsai |
On Mapping Algorithms to Linear and Fault-Tolerant Systolic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(3), pp. 470-478, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
fault-tolerant systolic arrays, linearly connected arrays, processor elements, VLSI model, Diogenes methodology, algorithms, fault tolerant computing, cellular arrays, propagation delay, matrix computations, mapping technique, linear systolic arrays |
48 | Wei-Kang Huang, Fabrizio Lombardi |
An approach for testing programmable/configurable field programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 450-455, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
behavioral characterization, single fault detection, disjoint one-dimensional arrays, unilateral horizontal connections, common vertical input lines, array testing, logic blocks, field programmable gate arrays, field programmable gate arrays, VLSI, logic testing, integrated circuit testing, stuck-at fault, FPGA testing, functional fault, hybrid fault model |
48 | Michèle Dion, Tanguy Risset, Yves Robert |
Resource-constrained scheduling of partitioned algorithms on processor arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 3rd Euromicro Workshop on Parallel and Distributed Processing (PDP '95), January 25-27, 1995, San Remo, Italy, pp. 571-580, 1995, IEEE Computer Society, 0-8186-7031-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
physical processor arrays, communication capabilities, complex optimization problem, single integer linear programming problem, scheduling, computational complexity, complexity, linear programming, mapping, optimisation, processor arrays, partitioned algorithms, communication links, resource-constrained scheduling, optimal scheduling algorithms, linear processor arrays |
47 | Gary W. Elko |
Future Directions for Microphone Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 383-387, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
47 | Sven Nordholm, Ingvar Claesson, Nedelko Grbic |
Optimal and Adaptive Microphone Arrays for Speech Input in Automobiles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 307-329, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
47 | Jörg Bitzer, Klaus Uwe Simmer |
Superdirective Microphone Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 19-38, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
47 | Walter L. Kellermann |
Acoustic Echo Cancellation for Beamforming Microphone Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 281-306, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
47 | Rainer Martin 0001 |
Small Microphone Arrays with Postfilters for Noise and Acoustic Echo Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 255-279, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
47 | Maurizio Omologo, Marco Matassoni, Piergiorgio Svaizer |
Speech Recognition with Microphone Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 331-353, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
46 | John P. McSorley |
Double Arrays, Triple Arrays and Balanced Grids with v=r+c - 1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 37(2), pp. 313-318, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
double arrays, triple arrays, balanced grids, designs, arrays |
46 | Wu Jigang, Thambipillai Srikanthan, Xiaodong Wang |
Integrated Row and Column Rerouting for Reconfiguration of VLSI Arrays with Four-Port Switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(10), pp. 1387-1400, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Degradable VLSI array, algorithm, routing, reconfiguration, faulttolerance |
46 | Scott Y. L. Chin, Clarence S. P. Lee, Steven J. E. Wilton |
Power Implications of Implementing Logic Using FPGA Embedded Memory Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-8, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
46 | Jürgen Teich, Lothar Thiele |
Control generation in the design of processor arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 3(1-2), pp. 77-92, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
43 | Richard D. Neidinger |
Computing Multivariable Taylor Series to Arbitrary Order. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APL ![In: Proceedings of the 1995 International Conference on Applied Programming Languages, APL 1995, San Antonio, Texas, USA, June 4-8, 1995., pp. 134-144, 1995, ACM, 0-89791-722-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
nested arrays, data structure, APL, numerical method, automatic differentiation, Taylor series, partial derivatives |
43 | Graham M. Megson, Xian Chen |
A synthesis method of LSGP partitioning for given-shape regular arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 234-238, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
LSGP partitioning, given-shape regular arrays, computational polytope, activity matrix, timing vector, locally sequential globally parallel, parallel algorithms, data structures, systolic arrays, processor arrays |
42 | Gary M. Zoppetti, Gagan Agrawal, Rishi Kumar |
Impact of Data Distribution on Performance of Irregular Reductions on Multithreaded Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCN ![In: High-Performance Computing and Networking, 9th International Conference, HPCN Europe 2001, Amsterdam, The Netherlands, June 25-27, 2001, Proceedings, pp. 483-492, 2001, Springer, 3-540-42293-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
42 | Itsuo Takanami, Tadayoshi Horita |
A built-in self-reconfigurable scheme for 3D mesh arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPAN ![In: 1997 International Symposium on Parallel Architectures, Algorithms and Networks (ISPAN '97), 18-20 December 1997, Taipei, Taiwan, pp. 458-464, 1997, IEEE Computer Society, 0-8186-8259-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
fault tolerant 3D processor arrays, 3D mesh arrays, self-reconfigurable scheme, track switches, fault compensation, reconfiguration, reconfigurable architectures |
42 | Seiken Yano |
Unified scan design with scannable memory arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 153-159, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
unified scan design, scannable memory arrays, single scan path, scan operation time, scannable register file, fault diagnosis, design for testability, design-for-testability, automatic testing, logic CAD, flip-flops, flip-flops, arrays, shift registers, integrated memory circuits |
41 | Pantelis K. Varlamos, Panagiotis J. Papakanellos, Christos N. Capsalis |
Design of Circular Switched Parasitic Dipole Arrays Using a Genetic Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Wirel. Inf. Networks ![In: Int. J. Wirel. Inf. Networks 11(4), pp. 201-206, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Circular switched parasitic dipole arrays, electronic beam steering, induced EMF method, genetic algorithms, method of moments |
41 | Elias Yaacoub, Zaher Dawy |
On WCDMA Downlink Capacity with Power Allocation Strategy and Adaptive Antenna Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2008, Beijing, China, 19-23 May 2008, pp. 5043-5047, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Silvio Ghilardi, Enrica Nicolini, Silvio Ranise, Daniele Zucchelli |
Decision procedures for extensions of the theory of arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Math. Artif. Intell. ![In: Ann. Math. Artif. Intell. 50(3-4), pp. 231-254, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Mathematics Subject Classifications (2000) 68T27, 03B25, 03B70, 68T15 |
41 | Silvio Ghilardi, Enrica Nicolini, Silvio Ranise, Daniele Zucchelli |
Deciding Extensions of the Theory of Arrays by Integrating Decision Procedures and Instantiation Strategies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
JELIA ![In: Logics in Artificial Intelligence, 10th European Conference, JELIA 2006, Liverpool, UK, September 13-15, 2006, Proceedings, pp. 177-189, 2006, Springer, 3-540-39625-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
41 | Ralph T. Hoctor, Saleem A. Kassam |
Array redundancy for active line arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Image Process. ![In: IEEE Trans. Image Process. 5(7), pp. 1179-1183, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
|
40 | Guy Even, Ami Litman |
Overcoming chip-to-chip delays and clock skews. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 199-208, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
chip-to-chip delays, chip-to-chip interconnections, feasible clock period, large systolic linear arrays, systolic two-dimensional arrays, logic duplication, delays, logic design, systolic arrays, systolic array, functionality, retiming, clock skews |
39 | Naotake Kamiura, Yutaka Hata, Kazuharu Yamato |
A cellular array designed from a Multiple-valued Decision Diagram and its fault tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 20-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
multiple-valued decision diagram, fault tests, testable cellular arrays, VLSI, fault diagnosis, logic testing, logic CAD, cellular arrays, cellular array, multivalued logic circuits, switch functions, multiple stuck-at faults |
39 | Jean Frédéric Myoupo |
A Fully-Pipelined Solutions Constructor for Dynamic Programming Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCI ![In: Advances in Computing and Information - ICCI'91, International Conference on Computing and Information, Ottawa, Canada, May 27-29, 1991, Proceedings, pp. 421-430, 1991, Springer, 3-540-54029-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
Modular Arrays, Parallel Algorithms, Complexity, Dynamic Programming, Design of Algorithms, Linear Systolic Arrays |
39 | Osamu Hoshuyama, Akihiko Sugiyama |
Robust Adaptive Beamforming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 87-109, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Joseph H. DiBiase, Harvey F. Silverman, Michael S. Brandstein |
Robust Localization in Reverberant Rooms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 157-180, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Elio D. Di Claudio, Raffaele Parisi |
Multi-Source Localization Strategies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 181-201, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Gary W. Elko |
Spatial Coherence Functions for Differential Microphones in Isotropic Noise Fields. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 61-85, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Darren B. Ward, Rodney A. Kennedy, Robert C. Williamson |
Constant Directivity Beamforming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 3-17, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Klaus Uwe Simmer, Jörg Bitzer, Claude Marro |
Post-Filtering Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 39-60, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Simon Doclo, Marc Moonen |
GSVD-Based Optimal Filtering for Multi-Microphone Speech Enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 111-132, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Norbert Strobel, Sascha Spors, Rudolf Rabenstein |
Joint Audio-Video Signal Processing for Object Localization and Tracking. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 203-225, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Scott C. Douglas |
Blind Separation of Acoustic Signals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 355-380, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Michael S. Brandstein, Scott M. Griebel |
Explicit Speech Modeling for Microphone Array Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 133-153, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Dirk Van Compernolle |
Future Directions in Microphone Array Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 389-394, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
39 | Julie E. Greenberg, Patrick M. Zurek |
Microphone-Array Hearing Aids. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microphone Arrays ![In: Microphone Arrays - Signal Processing Techniques and Applications, pp. 229-253, 2001, Springer, 978-3-642-07547-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
38 | Mauricio Ayala-Rincón, Carlos H. Llanos, Ricardo P. Jacobi, Reiner W. Hartenstein |
Prototyping time- and space-efficient computations of algebraic operations over dynamically reconfigurable systems modeled by rewriting-logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(2), pp. 251-281, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Term Rewriting Systems (TRS), algebraic manipulation, dynamically reconfigurable systems, Fast Fourier Transform (FFT), reconfigurable computing, systolic arrays, rewriting-logic |
38 | John C. Ramirez, Rami G. Melhem |
Computational Arrays with Flexible Redundancy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 43(4), pp. 413-430, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
flexible redundancy, computational arrays, processor/switch array, redundant arrays, Markov chain techniques, probability arguments, fault tolerant arrays, defect avoidance, parallel processing, fault tolerant computing, reconfiguration, redundancy, redundancy, embedding, logic design, fault detection, correction, fault masking, faulty processors, reconfiguration algorithms |
38 | Sy-Yen Kuo, Sheng-Chiech Liang |
Concurrent Error Detection and Correction in Real-Time Systolic Sorting Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 41(12), pp. 1615-1620, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
online error correction, two level pipelining, real-time systolic sorting arrays, online error detection, VLSI sorting arrays, functional errors, data errors, real-time systems, parallel algorithms, VLSI, sorting, error correction codes, systolic arrays, error detection codes, concurrent error detection, high-throughput, self-checking, WSI, concurrent error correction |
38 | H. V. Jagadish, Thomas Kailath |
A Family of New Efficient Arrays for Matrix Multiplication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 38(1), pp. 149-155, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
regular iterative algorithm, matrix multiplication arrays, iteration vector, conventional arrays, processor cells, iterative methods, matrix algebra, cellular arrays, multiplying circuits |
37 | Alexander Thomasian, Gang Fu, Chunqi Han |
Performance of Two-Disk Failure-Tolerant Disk Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(6), pp. 799-814, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Redundant arrays of independent disks, RAID5, RAID6, two-disk failure-tolerant arrays, EVENODD, RM2, operation in degraded mode, clustered RAID, fork-join requests, simulation, performance evaluation, queuing analysis, load imbalance, RDP |
37 | Massimo Maresca |
Polymorphic Processor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 4(5), pp. 490-506, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
polymorphic processor arrays, mesh-connected arrays, PPA, low complexity algorithms, PPA programming model, computational complexity, parallel processing, parallel computers, parallel architectures, multiprocessor interconnection networks |
37 | Jennifer B. Sartor, Stephen M. Blackburn, Daniel Frampton, Martin Hirzel, Kathryn S. McKinley |
Z-rays: divide arrays and conquer speed and flexibility. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PLDI ![In: Proceedings of the 2010 ACM SIGPLAN Conference on Programming Language Design and Implementation, PLDI 2010, Toronto, Ontario, Canada, June 5-10, 2010, pp. 471-482, 2010, ACM, 978-1-4503-0019-3. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
arraylets, z-rays, compression, arrays, heap |
37 | Lin Wan, Wenjiang J. Fu, Minghua Deng, Minping Qian |
A Method to Correct Systematic Bias in Affymetrix SNP Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
BMEI (1) ![In: Proceedings of the 2008 International Conference on BioMedical Engineering and Informatics, BMEI 2008, May 28-30, 2008, Sanya, Hainan, China - Volume 1, pp. 442-446, 2008, IEEE Computer Society, 978-0-7695-3118-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Affymetrix SNP arrays, copy number estimation, systematic bias |
37 | Morten Kromberg |
Arrays of objects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DLS ![In: Proceedings of the 2007 Symposium on Dynamic Languages, DLS 2007, October 22, 2007, Montreal, Quebec, Canada, pp. 20-28, 2007, ACM, 978-1-59593-868-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multi-paradigm languages, object orientation, functional programming, language design, arrays |
37 | Ekow J. Otoo, Doron Rotem, Sridhar Seshadri |
Optimal chunking of large multidimensional arrays for data warehousing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DOLAP ![In: DOLAP 2007, ACM 10th International Workshop on Data Warehousing and OLAP, Lisbon, Portugal, November 9, 2007, Proceedings, pp. 25-32, 2007, ACM, 978-1-59593-827-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
multi-dimensional arrays, data warehousing, chunking |
37 | Dean S. Hoskins, Charles J. Colbourn, Douglas C. Montgomery |
Software performance testing using covering arrays: efficient screening designs with categorical factors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WOSP ![In: Proceedings of the Fifth International Workshop on Software and Performance, WOSP 2005, Palma, Illes Balears, Spain, July 12-14, 2005, pp. 131-136, 2005, ACM, 1-59593-087-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
D-optimal designs, performance testing, covering arrays |
37 | Gerhard E. Hoernes, Garth H. Foster |
Declaration and Addressing of Varying Density Arrays and Structure. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMOD Workshop, Vol. 1 ![In: Proceedings of 1974 ACM-SIGMOD Workshop on Data Description, Access and Control, Ann Arbor, Michigan, USA, May 1-3, 1974, 2 Volumes, pp. 15-33, 1974, ACM, 978-1-4503-7415-6. The full citation details ...](Pics/full.jpeg) |
1974 |
DBLP DOI BibTeX RDF |
DBTG, Data structures, APL, Schema, Arrays, Data base, Addressing, Declaration, PL/I |
36 | Shoulun Long, Josef Pieprzyk, Huaxiong Wang, Duncan S. Wong |
Generalised Cumulative Arrays in Secret Sharing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Des. Codes Cryptogr. ![In: Des. Codes Cryptogr. 40(2), pp. 191-209, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Cumulative array, Perfect hash family, Secret sharing |
36 | Veli Mäkinen, Gonzalo Navarro 0001 |
Compressed Compact Suffix Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CPM ![In: Combinatorial Pattern Matching, 15th Annual Symposium, CPM 2004, Istanbul,Turkey, July 5-7, 2004, Proceedings, pp. 420-433, 2004, Springer, 3-540-22341-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | John Schewel, Michael Thornburg, Steve Casselman |
Transformable computers & hardware object technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 518-522, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
transformable computers, hardware object technology, reconfigurable aspects, computationally intensive software algorithms, on-the-fly use, field programmable gate arrays, field programmable gate arrays, programming, reconfigurable architectures, programmable logic arrays, hardware design, performance gain |
35 | Anmol Mathur, Kuang-Chien Chen, C. L. Liu 0001 |
Re-engineering of timing constrained placements for regular architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 485-490, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Xilinx 3000 FPGA architecture, engineering requirements, regular architectures, timing constrained placements reengineering, FPGAs, field programmable gate arrays, logic CAD, program debugging, systems re-engineering, logic arrays, design flow, gate arrays, design specification, timing performance, design cycle, design debugging |
35 | Chris J. Myers, Tomas Rokicki, Teresa H.-Y. Meng |
Automatic synthesis of gate-level timed circuits with choice. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARVLSI ![In: 16th Conference on Advanced Research in VLSI (ARVLSI '95), March 27-29, 1995, Chapel Hill, North Carolina, USA, pp. 42-58, 1995, IEEE Computer Society, 0-8186-7047-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
gate-level timed circuits, C-elements, explicit timing information, textual specification, conditional operation, reachable state space, semi-custom components, timing, logic CAD, asynchronous circuits, asynchronous circuits, circuit CAD, cellular arrays, circuit complexity, logic arrays, graphical representation, standard-cells, CAD tool, automatic synthesis, gate-arrays, state-space methods, AND gates, OR gates |
35 | Philip Gillett, Miles Johnson, Jamie Carneal |
Performance benefits of spherical diffracting arrays versus free field arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2008, March 30 - April 4, 2008, Caesars Palace, Las Vegas, Nevada, USA, pp. 5264-5267, 2008, IEEE, 1-4244-1484-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Tong Liu 0007, Wei-Kang Huang, Fabrizio Lombardi |
Testing of Uncustomized Segmented Channel Field Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the Third International ACM Symposium on Field-Programmable Gate Arrays,FPGA 1995, Monterey, California, USA, February 12-14, 1995, pp. 125-131, 1995, ACM, 0-89791-743-X. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
constant testability, FPGA, testing, manufacturing |
34 | S. D. Kaushik, Chua-Huang Huang, J. Ramanujam, P. Sadayappan |
Multi-phase array redistribution: modeling and evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPPS ![In: Proceedings of IPPS '95, The 9th International Parallel Processing Symposium, April 25-28, 1995, Santa Barbara, California, USA, pp. 441-445, 1995, IEEE Computer Society, 0-8186-7074-6. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
block-cyclically distributed arrays, multi-phase approach, parallel programming, processor scheduling, cost model, arrays, High Performance Fortran, communication overhead, array redistribution, modeling and evaluation |
34 | Peng Zhao, Shimin Cui, Yaoqing Gao, Raúl Silvera, José Nelson Amaral |
Forma: A framework for safe automatic array reshaping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Program. Lang. Syst. ![In: ACM Trans. Program. Lang. Syst. 30(1), pp. 2, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
reference analysis, data structure, Arrays |
33 | Martin C. Herbordt, Jade Cravy, Honghai Zhang, Calvin Lin, Hong Rao |
An Array Control Unit for High Performance SIMD Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CAMP ![In: Fifth International Workshop on Computer Architectures for Machine Perception (CAMP 2000), September 11-13, 2000, Padova, Italy, pp. 293-301, 2000, IEEE Computer Society, 0-7695-0740-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
array control unit, high performance SIMD arrays, array utilization, SIMD arrays, parallel processing |
33 | T. Utsumi, Naotake Kamiura, Yutaka Hata, Kazuharu Yamato |
Multiple-Valued Programmable Logic Arrays with Universal Literals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 27th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1997, Antigonish, Nova Scotia, Canada, May 28-30, 1997, Proceedings, pp. 163-168, 1997, IEEE Computer Society, 0-8186-7910-7. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
universal literals, multiple-valued programmable logic, universal literal generators, operator structures, programmable logic arrays, programmable logic arrays |
33 | Bradly K. Fawcett, J. Watson |
Reconfigurable Processing With Field Programmable Gate Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 1996 International Conference on Application-Specific Systems, Architectures, and Processors (ASAP '96), August 19-23, 1996, Chicago, IL , USA, pp. 293-302, 1996, IEEE Computer Society, 0-8186-7542-X. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
reconfigurable processing, internal architecture, computationally-intensive tasks, programmable solution, XC6200 FPGA architecture, SRAM control store, on-chip memory capability, field programmable gate arrays, interconnections, reconfigurable architectures, processors, coprocessors, coprocessors, SRAM chips, SRAM-based field programmable gate arrays |
33 | Timothy J. Schulz |
Coherent array imaging with sparse arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICIP ![In: Proceedings 1995 International Conference on Image Processing, Washington, DC, USA, October 23-26, 1995, pp. 133-135, 1995, IEEE Computer Society, 0-8186-7310-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
antenna phased arrays, sparse arrays, coherent array imaging, phased-array imaging systems, Fourier inversion, coherent imaging system, image processing, maximum likelihood estimation, maximum-likelihood estimation, missing data, incomplete data, array signal processing, aperture |
33 | David C. J. Naylor, Simon Jones 0001 |
A Performance Model for Multilayer Neural Networks in Linear Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 5(12), pp. 1322-1328, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
throughput rate, input-output bandwidth, two-hidden-layer network, performance evaluation, performance, performance model, latency, systolic arrays, multilayer perceptrons, feedforward neural nets, linear arrays, multilayer neural networks |
32 | Jeremy Kepner |
Multicore programming in pMatlab using distributed arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLADE ![In: 6th International Workshop on Challenges of Large Applications in Distributed Environments, CLADE@HPDC 2008, Boston, MA, USA, June 23, 2008, pp. 59-60, 2008, ACM, 978-1-60558-156-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
parallel computing, distributed arrays |
32 | Cemal Yilmaz 0001, Myra B. Cohen, Adam A. Porter |
Covering Arrays for Efficient Fault Characterization in Complex Configuration Spaces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 32(1), pp. 20-34, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
fault characterization, Software testing, covering arrays, distributed continuous quality assurance |
32 | Marco A. Panduro, Carlos A. Brizuela, David Covarrubias, Claudio Lopez |
A trade-off curve computation for linear antenna arrays using an evolutionary multi-objective approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Soft Comput. ![In: Soft Comput. 10(2), pp. 125-131, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Non-regular arrays, Minor lobes, Radiation pattern, Genetic algorithms, Multi-objective |
32 | Ming Wu, Xiao-Ming Dong, Huaiyang Li |
Queue Network Modeling Approach to Analysis of the Optimal Stripe Unit Size for Disk Arrays under Synchronous I/O Workloads. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWNAS ![In: 2006 International Workshop on Networking, Architecture and Storages (IWNAS 2006), 1-3 August 2006, Shenyang, China, pp. 36-42, 2006, IEEE Computer Society, 0-7695-2651-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
stripe unit size, simulation, RAID, disk arrays, queue network model |
32 | Phil Ventura, Christopher A. Egert, Adrienne Decker |
Ancestor worship in CS1: on the primacy of arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
OOPSLA Companion ![In: Companion to the 19th Annual ACM SIGPLAN Conference on Object-Oriented Programming, Systems, Languages, and Applications, OOPSLA 2004, October 24-28, 2004, Vancouver, BC, Canada, pp. 68-72, 2004, ACM, 1-58113-833-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
data structures, object-oriented programming, CS1, curriculum, object oriented-design, arrays, objects-first |
32 | Kees van Reeuwijk, Will Denissen, Henk J. Sips, Edwin M. R. M. Paalvast |
An Implementation Framework for HPF Distributed Arrays on Message-Passing Parallel Computer Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(9), pp. 897-914, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
message aggregation, parallel computers, message passing, HPF, distributed arrays |
32 | Kumar N. Ganapathy, Benjamin W. Wah |
Optimal Synthesis of Algorithm-Specific Lower-Dimensional Processor Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 7(3), pp. 274-287, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
polynomial-time search, transitive closure, processor arrays, optimal design, objective function, Design constraints, uniform recurrence equations |
32 | William P. Marnane, Will R. Moore |
Testing VLSI regular arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 6(2), pp. 153-177, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
testing regular arrays, C-testability, test vector generation |
31 | Ali M. Bazzi, Sami H. Karaki |
Simulation of a new maximum power point tracking technique for multiple photovoltaic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2008 IEEE International Conference on Electro/Information Technology, EIT 2008, held at Iowa State University, Ames, Iowa, USA, May 18-20, 2008, pp. 175-178, 2008, IEEE, 978-1-4244-2030-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Tansu Filik, T. Engin Tuncer |
Design and evaluation of V-shaped arrays for 2-D DOA estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICASSP ![In: Proceedings of the IEEE International Conference on Acoustics, Speech, and Signal Processing, ICASSP 2008, March 30 - April 4, 2008, Caesars Palace, Las Vegas, Nevada, USA, pp. 2477-2480, 2008, IEEE, 1-4244-1484-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
31 | Inas Khalifa, Rodney G. Vaughan |
Optimal Configuration of Multi-Faceted Phased Arrays for Wide Angle Coverage. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTC Spring ![In: Proceedings of the 65th IEEE Vehicular Technology Conference, VTC Spring 2007, 22-25 April 2007, Dublin, Ireland, pp. 304-308, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Craig B. Zilles |
Accordion arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMM ![In: Proceedings of the 6th International Symposium on Memory Management, ISMM 2007, Montreal, Quebec, Canada, October 21-22, 2007, pp. 55-66, 2007, ACM, 978-1-59593-893-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Java, compression, memory management, polymorphism, array, character, unicode |
31 | Martin Kutrib, Andreas Malcher |
Real-Time Reversible Iterative Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCT ![In: Fundamentals of Computation Theory, 16th International Symposium, FCT 2007, Budapest, Hungary, August 27-30, 2007, Proceedings, pp. 376-387, 2007, Springer, 978-3-540-74239-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Adam O'Donovan, Ramani Duraiswami, Jan Neumann |
Microphone Arrays as Generalized Cameras for Integrated Audio Visual Processing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CVPR ![In: 2007 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR 2007), 18-23 June 2007, Minneapolis, Minnesota, USA, 2007, IEEE Computer Society, 1-4244-1179-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Laura Ruff |
Functional-Based Comparison between Two Special Classes of Uni- and Bidirectional Systolic Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SYNASC ![In: Proceedings of the Ninth International Symposium on Symbolic and Numeric Algorithms for Scientific Computing, SYNASC 2007, Timisoara, Romania, September 26-29, 2007, pp. 51-58, 2007, IEEE Computer Society, 978-0-7695-3078-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Ekow J. Otoo, Doron Rotem |
Parallel access of out-of-core dense extendible arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: Proceedings of the 2007 IEEE International Conference on Cluster Computing, 17-20 September 2007, Austin, Texas, USA, pp. 31-40, 2007, IEEE Computer Society, 978-1-4244-1387-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
31 | Simon J. Puglisi, William F. Smyth, Andrew Turpin |
Suffix arrays: what are they good for? ![Search on Bibsonomy](Pics/bibsonomy.png) |
ADC ![In: Database Technologies 2006, Proceedings of the 17th Australasian Database Conference, ADC 2006, Hobart, Tasmania, Australia, January 16-19 2006, pp. 17-18, 2006, Australian Computer Society, 1-920682-31-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
31 | Hiroshi Umeo, Masaya Hisaoka, Shunsuke Akiguchi |
A Twelve-State Optimum-Time Synchronization Algorithm for Two-Dimensional Rectangular Cellular Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UC ![In: Unconventional Computation, 4th International Conference, UC 2005, Sevilla, Spain, October 3-7, 2005, Proceedings, pp. 214-223, 2005, Springer, 3-540-29100-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Margaret Miró-Julià |
Degenerate Arrays: A Framework for Uncertain Data Tables. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCAST ![In: Computer Aided Systems Theory - EUROCAST 2005, 10th International Conference on Computer Aided Systems Theory, Las Palmas de Gran Canaria, Spain, February 7-11, 2005, Revised Selected Papers, pp. 21-26, 2005, Springer, 3-540-29002-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Klaus-Bernd Schürmann, Jens Stoye |
Counting Suffix Arrays and Strings. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPIRE ![In: String Processing and Information Retrieval, 12th International Conference, SPIRE 2005, Buenos Aires, Argentina, November 2-4, 2005, Proceedings, pp. 55-66, 2005, Springer, 3-540-29740-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
31 | Dong Kyue Kim, Junha Jo, Heejin Park |
A Fast Algorithm for Constructing Suffix Arrays for Fixed-Size Alphabets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WEA ![In: Experimental and Efficient Algorithms, Third International Workshop, WEA 2004, Angra dos Reis, Brazil, May 25-28, 2004, Proceedings, pp. 301-314, 2004, Springer, 3-540-22067-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Steven Hinckley, Paul V. Jansz-Drávetzky, Kamran Eshraghian |
Pixel Structure Effects on Crosstalk in Backwall Illuminated CMOS Compatible Photodiode Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 2nd IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2004), 28-30 January 2004, Perth, Australia, pp. 53-58, 2004, IEEE Computer Society, 0-7695-2081-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
31 | Hiroshi Umeo, Masashi Maeda, Norio Fujiwara |
An Efficient Mapping Scheme for Embedding Any One-Dimensional Firing Squad Synchronization Algorithm onto Two-Dimensional Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACRI ![In: Cellular Automata, 5th International Conference on Cellular Automata for Research and Industry, ACRI 2002, Geneva, Switzerland, October 9-11, 2002, Proceedings, pp. 69-81, 2002, Springer, 3-540-44304-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
31 | Tatsuo Tsuji, Hidetatsu Kawahara, Teruhisa Hochin, Ken Higuchi |
Sharing Extendible Arrays in a Distributed Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IICS ![In: Innovative Internet Computing Systems, International Workshop IICS 2001, Ilmenau, Germany, June 21-22, 2001, Proceedings, pp. 41-52, 2001, Springer, 3-540-42275-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
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