|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 1319 occurrences of 656 keywords
|
|
|
Results
Found 1392 publication records. Showing 1392 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
82 | A. N. Trahtman |
Piecewise and Local Threshold Testability of DFA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCT ![In: Fundamentals of Computation Theory, 13th International Symposium, FCT 2001, Riga, Latvia, August 22-24, 2001, Proceedings, pp. 347-358, 2001, Springer, 3-540-42487-3. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
locally threshold testable, piecewise testable, locally testable, syntactic semigroup, algorithm, automaton, transition graph |
82 | Roy S. Freedman |
Testability of Software Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 17(6), pp. 553-564, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
domain testability, domain-testable program, input-output inconsistencies, small test sets, test outputs, domain-testable specification, nondomain-testable specification, formal specification, controllability, software components, program testing, observability, program specifications |
75 | Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi |
A C-testable carry-free divider. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 2(4), pp. 472-488, 1994. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
75 | Niraj K. Jha, Abha Ahuja |
Easily testable nonrestoring and restoring gate-level cellular array dividers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(1), pp. 114-123, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
73 | R. D. (Shawn) Blanton, John P. Hayes |
Design of a fast, easily testable ALU. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 9-16, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
ALU, adder design, L-testable design, level-testable, carry-lookahead addition, fault diagnosis, logic testing, integrated circuit testing, automatic testing, digital arithmetic, integrated circuit design, adders, logic arrays, test patterns, area overhead, functional faults, carry logic, arithmetic-logic unit, 8 bit |
73 | Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja |
An optimized testable architecture for finite state machines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 164-169, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
optimized testable architecture, FSM synthesis, testable machine, transfer sequences, synthesis benchmark circuits, logic testing, finite state machines, finite state machines, sequential circuits, logic CAD, sequences, circuit optimisation, distinguishing sequences, synchronizing sequence |
69 | Eldar Fischer |
Testing graphs for colorable properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SODA ![In: Proceedings of the Twelfth Annual Symposium on Discrete Algorithms, January 7-9, 2001, Washington, DC, USA., pp. 873-882, 2001, ACM/SIAM, 0-89871-490-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
68 | Avraham Trakhtman |
Reducing the Time Complexity of Testing for Local Threshold Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIAA ![In: Implementation and Application of Automata, 8th International Conference, CIAA 2003, Santa Barbara, California, USA, July 16-18, 2003, Proceedings, pp. 141-149, 2003, Springer, 3-540-40561-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
threshold locally testable, algorithm, graph, Automaton |
68 | A. N. Trahtman |
An Algorithm to Verify Local Threshold Testability of Deterministic Finite Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WIA ![In: Automata Implementation, 4th International Workshop on Implementing Automata, WIA'99, Potsdam, Germany, July 17-19, 1999, Revised Papers, pp. 164-173, 1999, Springer, 3-540-42812-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
locally threshold testable, semigroup AMS subject classification 68Q25, 68Q68, 20M07, algorithm, deterministic finite automaton, 68Q45 |
67 | Jonathan S. Ostroff, Faraz Ahmadi Torshizi |
Testable Requirements and Specifications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TAP ![In: Tests and Proofs - 1st International Conference, TAP 2007, Zurich, Switzerland, February 12-13, 2007. Revised Papers, pp. 17-40, 2007, Springer, 978-3-540-73769-8. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
67 | Oded Goldreich 0001, Madhu Sudan 0001 |
Locally testable codes and PCPs of almost-linear length. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 53(4), pp. 558-655, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
error-correcting codes, derandomization, probabilistically checkable proofs, Proof verification |
67 | Irith Pomeranz |
Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(10), pp. 1465-1478, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
67 | Oded Goldreich 0001, Madhu Sudan 0001 |
Locally Testable Codes and PCPs of Almost-Linear Length. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 43rd Symposium on Foundations of Computer Science (FOCS 2002), 16-19 November 2002, Vancouver, BC, Canada, Proceedings, pp. 13-22, 2002, IEEE Computer Society, 0-7695-1822-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
67 | Oliver Matz |
On Piecewise Testable, Starfree, and Recognizable Picture Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FoSSaCS ![In: Foundations of Software Science and Computation Structure, First International Conference, FoSSaCS'98, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS'98, Lisbon, Portugal, March 28 - April 4, 1998, Proceedings, pp. 203-210, 1998, Springer, 3-540-64300-1. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
67 | Andres R. Takach, Niraj K. Jha |
Easily testable gate-level and DCVS multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 10(7), pp. 932-942, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
66 | S. Crepaux-Motte, Mireille Jacomino, Rene David |
An algebraic method for delay fault testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 308-315, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
input values, output function, robustly testable fault, nonrobustly testable fault, weakly verifiable, fault diagnosis, logic testing, delays, timing, Markov processes, random testing, delay fault testing, state transition, input vectors, algebraic method |
58 | Artur Czumaj, Christian Sohler |
On testable properties in bounded degree graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SODA ![In: Proceedings of the Eighteenth Annual ACM-SIAM Symposium on Discrete Algorithms, SODA 2007, New Orleans, Louisiana, USA, January 7-9, 2007, pp. 494-501, 2007, SIAM, 978-0-898716-24-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP BibTeX RDF |
|
58 | László Babai, Amir Shpilka, Daniel Stefankovic |
Locally testable cyclic codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Inf. Theory ![In: IEEE Trans. Inf. Theory 51(8), pp. 2849-2858, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
58 | Noga Alon, Asaf Shapira |
A Characterization of the (natural) Graph Properties Testable with One-Sided Error. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 46th Annual IEEE Symposium on Foundations of Computer Science (FOCS 2005), 23-25 October 2005, Pittsburgh, PA, USA, Proceedings, pp. 429-438, 2005, IEEE Computer Society, 0-7695-2468-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
58 | Ronald D. Blanton, John P. Hayes |
On the design of fast, easily testable ALU's. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 8(2), pp. 220-223, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
58 | Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis |
C-Testable modified-Booth multipliers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 8(3), pp. 241-260, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model |
58 | Sam M. Kim, Robert McNaughton, Robert McCloskey |
An Upper Bound on the Order of Locally Testable Deterministic Finite Automata. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Optimal Algorithms ![In: Optimal Algorithms, International Symposium, Varna, Bulgaria, May 29 - June 2, 1989, Proceedings, pp. 48-65, 1989, Springer, 3-540-51859-2. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
57 | Yun Shao 0002, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara |
On Selecting Testable Paths in Scan Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 19(4), pp. 447-456, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
testable path, delay testing, delay fault, path delay fault, path selection |
57 | Debesh K. Das, Bhargab B. Bhattacharya |
Testable design of non-scan sequential circuits using extra logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 176-, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
nonscan sequential circuits, sequentially redundant faults, multiple stuck-at-fault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design |
57 | S. M. Aziz |
A C-testable modified Booth's array multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 278-282, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
C-testable multiplier, modified Booth algorithm, gate-level design, parallel processing, logic testing, integrated circuit testing, digital arithmetic, stuck-at faults, CMOS logic circuits, multiplying circuits, logic arrays, array multiplier, parallel multiplier |
50 | Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng |
On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 15-22, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing |
49 | Himanshu Thapliyal, A. Prasad Vinod 0001 |
Designing Efficient Online Testable Reversible Adders With New Reversible Gate. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 1085-1088, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
49 | Noga Alon, Eldar Fischer, Ilan Newman, Asaf Shapira |
A combinatorial characterization of the testable graph properties: it's all about regularity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 38th Annual ACM Symposium on Theory of Computing, Seattle, WA, USA, May 21-23, 2006, pp. 251-260, 2006, ACM, 1-59593-134-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
characterization, property testing, regularity lemma |
49 | Tali Kaufman, Simon Litsyn |
Almost Orthogonal Linear Codes are Locally Testable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 46th Annual IEEE Symposium on Foundations of Computer Science (FOCS 2005), 23-25 October 2005, Pittsburgh, PA, USA, Proceedings, pp. 317-326, 2005, IEEE Computer Society, 0-7695-2468-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
49 | László Babai, Amir Shpilka, Daniel Stefankovic |
Locally Testable Cyclic Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 44th Symposium on Foundations of Computer Science (FOCS 2003), 11-14 October 2003, Cambridge, MA, USA, Proceedings, pp. 116-125, 2003, IEEE Computer Society, 0-7695-2040-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
49 | Pan Zhongliang |
Fault Detection for Testable Realizations of Multiple-Valued Logic Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 242-249, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
49 | Jerry Z. Gao 0002, Kamal Gupta, Shalini Gupta, Simon S. Y. Shim |
On Building Testable Software Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCBSS ![In: COTS-Based Software Systems, First International Conference, ICCBSS 2002, Orlando, FL, USA, February 4-6, 2002, Proceedings, pp. 108-121, 2002, Springer, 3-540-43100-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
49 | Meghanad D. Wagh, Chien-In Henry Chen |
High-level design synthesis with redundancy removal for high speed testable adders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (6) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 358-361, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
49 | Sen-Pin Lin, Charles Njinda, Melvin A. Breuer |
Generating a family of testable designs using the BILBO methodology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 4(1), pp. 71-89, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
BILBO design system, built-in self-test, test scheduling, synthesis for testability |
49 | Srinivas Devadas, Kurt Keutzer |
Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, Florida, USA, June 24-28, 1990., pp. 221-227, 1990, IEEE Computer Society Press, 0-89791-363-9. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
48 | Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir |
C-testable bit parallel multipliers over GF(2m). ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(1), pp. 5:1-5:18, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
testing, cryptography, built-in self-test, digital signal processing, polynomials, VLSI design, stuck-at fault, TPG, fault, multiplier, Galois field, error control code, C-testable |
48 | Or Meir |
Combinatorial construction of locally testable codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 40th Annual ACM Symposium on Theory of Computing, Victoria, British Columbia, Canada, May 17-20, 2008, pp. 285-294, 2008, ACM, 978-1-60558-047-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
pcps of proximity, probabilistically checkable proofs, locally testable codes |
48 | Eliane Martins, Cristina Maria Toyota, Rosileny Lie Yanagawa |
Constructing Self-Testable Software Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSN ![In: 2001 International Conference on Dependable Systems and Networks (DSN 2001) (formerly: FTCS), 1-4 July 2001, Göteborg, Sweden, Proceedings, pp. 151-160, 2001, IEEE Computer Society, 0-7695-1101-5. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
component testability, self-testable component, OO testing, design for testability |
48 | Masayuki Tsukisaka, Takashi Nanya |
A testable design for asynchronous fine-grain pipeline circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), 18-20 December 2000, Los Angeles, CA, USA, pp. 148-155, 2000, IEEE Computer Society, 0-7695-0975-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design |
48 | Ugur Kalay, Marek A. Perkowski, Douglas V. Hall |
Highly Testable Boolean Ring Logic Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISMVL ![In: 29th IEEE International Symposium on Multiple-Valued Logic, ISMVL 1999, Freiburg im Breisgau, Germany, May 20-22, 1999, Proceedings, pp. 268-274, 1999, IEEE Computer Society, 0-7695-0161-3. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Boolean Ring Circuits, Easily Testable Multiple-Valued Logic Circuits, Binary Implementation of MVL Circuits |
48 | Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu |
Design of C-Testable Multipliers Based on the Modified Booth Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 42-47, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
modified Booth Algorithm, c-testable design, design for testability, multiplier, exhaustive testing, cell fault model |
48 | Gosta Pada Biswas, Idranil Sen Gupta |
Generalized modular design of testable m-out-of-n code checker. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 322-326, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
testable m-out-of-n code checker, combinational logic port, combinational logic cells, unidirectional faults, complementary outputs, VLSI, fault diagnosis, logic testing, cellular automata, combinational circuits, fault location, stuck-at faults, logic arrays, cellular automaton, modular design, iterative array, initial state |
48 | Dong Sam Ha, Sudhakar M. Reddy |
On the design of random pattern testable PLA based on weighted random pattern testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 3(2), pp. 149-157, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
built-in self-test, PLA, testable design, random pattern testability |
47 | Irith Pomeranz |
Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 441-450, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
47 | Mohamed Soufi, Yvon Savaria, Bozena Kaminska |
On the design of at-speed testable VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 13th IEEE VLSI Test Symposium (VTS'95), April 30 - May 3, 1995, Princeton, New Jersey, USA, pp. 290-295, 1995, IEEE Computer Society, 0-8186-7000-2. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
at-speed testable circuits, testable VLSI circuits, application test time, parallel vectors, stuck-at test, observability problems, probe observation point, VLSI, logic testing, integrated circuit testing, design for testability, design-for-testability, logic design, sequential circuits, sequential circuits, observability, fault coverages, integrated circuit design, integrated logic circuits, operational speed, DFT technique |
43 | Oded Lachish, Ilan Newman, Asaf Shapira |
Space Complexity Vs. Query Complexity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comput. Complex. ![In: Comput. Complex. 17(1), pp. 70-93, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Subject classification. 68Q15, 68Q10 |
43 | Oded Lachish, Ilan Newman, Asaf Shapira |
Space Complexity vs. Query Complexity. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPROX-RANDOM ![In: Approximation, Randomization, and Combinatorial Optimization. Algorithms and Techniques, 9th International Workshop on Approximation Algorithms for Combinatorial Optimization Problems, APPROX 2006 and 10th International Workshop on Randomization and Computation, RANDOM 2006, Barcelona, Spain, August 28-30 2006, Proceedings, pp. 426-437, 2006, Springer, 3-540-38044-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
43 | Noga Alon, Asaf Shapira |
Linear equations, arithmetic progressions and hypergraph property testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SODA ![In: Proceedings of the Sixteenth Annual ACM-SIAM Symposium on Discrete Algorithms, SODA 2005, Vancouver, British Columbia, Canada, January 23-25, 2005, pp. 708-717, 2005, SIAM, 0-89871-585-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
43 | Eldar Fischer, Ilan Newman |
Testing versus estimation of graph properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 37th Annual ACM Symposium on Theory of Computing, Baltimore, MD, USA, May 22-24, 2005, pp. 138-146, 2005, ACM, 1-58113-960-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
property testing, regularity lemma, graph properties, distance approximation |
43 | A. N. Trahtman |
A Package TESTAS for Checking Some Kinds of Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIAA ![In: Implementation and Application of Automata, 7th International Conference, CIAA 2002, Tours, France, July 3-5, 2002, Revised Papers, pp. 228-232, 2002, Springer, 3-540-40391-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
43 | Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli |
Irredundant sequential machines via optimal logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 9(1), pp. 8-18, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
42 | A. N. Trahtman |
A Polynomial Time Algorithm for Left [Right] Local Testability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIAA ![In: Implementation and Application of Automata, 7th International Conference, CIAA 2002, Tours, France, July 3-5, 2002, Revised Papers, pp. 203-212, 2002, Springer, 3-540-40391-4. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
locally testable, algorithm, graph, language, semigroup, deterministic finite automaton |
41 | Swastik Kopparty, Shubhangi Saraf |
Tolerant Linearity Testing and Locally Testable Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPROX-RANDOM ![In: Approximation, Randomization, and Combinatorial Optimization. Algorithms and Techniques, 12th International Workshop, APPROX 2009, and 13th International Workshop, RANDOM 2009, Berkeley, CA, USA, August 21-23, 2009. Proceedings, pp. 601-614, 2009, Springer, 978-3-642-03684-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
41 | Itai Benjamini, Oded Schramm, Asaf Shapira |
Every minor-closed property of sparse graphs is testable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 40th Annual ACM Symposium on Theory of Computing, Victoria, British Columbia, Canada, May 17-20, 2008, pp. 393-402, 2008, ACM, 978-1-60558-047-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
minor closed properties, graph algorithms, property testing |
41 | Soheila Bashardoust-Tajali, Jean-Pierre Corriveau |
On Extracting Tests from a Testable Model in the Context of Domain Engineering. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICECCS ![In: 13th International Conference on Engineering of Complex Computer Systems (ICECCS 2008), March 31 2008 - April 3 2008, Belfast, Northern Ireland, pp. 98-107, 2008, IEEE Computer Society, 0-7695-3139-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
41 | Tali Kaufman, Madhu Sudan 0001 |
Sparse Random Linear Codes are Locally Decodable and Testable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 48th Annual IEEE Symposium on Foundations of Computer Science (FOCS 2007), October 20-23, 2007, Providence, RI, USA, Proceedings, pp. 590-600, 2007, IEEE Computer Society, 978-0-7695-3010-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
41 | Saravanan Padmanaban, Spyros Tragoudas |
Efficient identification of (critical) testable path delay faults using decision diagrams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(1), pp. 77-87, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Jose L. Verdú-Mas, Rafael C. Carrasco, Jorge Calera-Rubio |
Parsing with Probabilistic Strictly Locally Testable Tree Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 27(7), pp. 1040-1050, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Noga Alon, Asaf Shapira |
Every monotone graph property is testable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 37th Annual ACM Symposium on Theory of Computing, Baltimore, MD, USA, May 22-24, 2005, pp. 128-137, 2005, ACM, 1-58113-960-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
monotone properties, property testing, regularity lemma |
41 | Venkatesan Guruswami, Atri Rudra |
Tolerant Locally Testable Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPROX-RANDOM ![In: Approximation, Randomization and Combinatorial Optimization, Algorithms and Techniques, 8th International Workshop on Approximation Algorithms for Combinatorial Optimization Problems, APPROX 2005 and 9th InternationalWorkshop on Randomization and Computation, RANDOM 2005, Berkeley, CA, USA, August 22-24, 2005, Proceedings, pp. 306-317, 2005, Springer, 3-540-28239-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Paul Valiant |
The Tensor Product of Two Codes Is Not Necessarily Robustly Testable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPROX-RANDOM ![In: Approximation, Randomization and Combinatorial Optimization, Algorithms and Techniques, 8th International Workshop on Approximation Algorithms for Combinatorial Optimization Problems, APPROX 2005 and 9th InternationalWorkshop on Randomization and Computation, RANDOM 2005, Berkeley, CA, USA, August 22-24, 2005, Proceedings, pp. 472-481, 2005, Springer, 3-540-28239-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
41 | Eli Ben-Sasson, Madhu Sudan 0001 |
Robust Locally Testable Codes and Products of Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPROX-RANDOM ![In: Approximation, Randomization, and Combinatorial Optimization, Algorithms and Techniques, 7th International Workshop on Approximation Algorithms for Combinatorial Optimization Problems, APPROX 2004, and 8th International Workshop on Randomization and Computation, RANDOM 2004, Cambridge, MA, USA, August 22-24, 2004, Proceedings, pp. 286-297, 2004, Springer, 3-540-22894-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
41 | Tomokazu Yoneda, Hideo Fujiwara |
Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(4-5), pp. 487-501, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
consecutive transparency, built-in self test, design for testability, system-on-a-chip, test access mechanism, consecutive testability |
41 | Shyue-Kung Lu, Chien-Hung Yeh |
Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 230-, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
41 | Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara |
A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 5-12, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
41 | José Ruiz 0001, Salvador España Boquera, Pedro García 0001 |
Locally Threshold Testable Languages in Strict Sense: Application to the Inference Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICGI ![In: Grammatical Inference, 4th International Colloquium, ICGI-98, Ames, Iowa, USA, July 12-14, 1998, Proceedings, pp. 150-161, 1998, Springer, 3-540-64776-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
41 | Dariusz Bojanowicz |
How Faults can be Simulated in Self-Testable VLSI Digital Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROMICRO ![In: 24th EUROMICRO '98 Conference, Engineering Systems and Software for the Next Decade, 25-27 August 1998, Vesteras, Sweden, pp. 10180-10183, 1998, IEEE Computer Society, 0-8186-8646-4. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
41 | Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu |
C-testable design techniques for iterative logic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 3(1), pp. 146-152, 1995. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
41 | Chen-Huan Chiang, Sandeep K. Gupta 0001 |
Random pattern testable logic synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 125-128, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
41 | Gwo-Haur Hwang, Wen-Zen Shen |
Restructuring and logic minimization for testable PLA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(4), pp. 488-496, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
41 | Bernhard Eschermann, Hans-Joachim Wunderlich |
Optimized synthesis techniques for testable sequential circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 11(3), pp. 301-312, 1992. The full citation details ...](Pics/full.jpeg) |
1992 |
DBLP DOI BibTeX RDF |
|
41 | Sam M. Kim, Robert McNaughton |
Computing the Order of a Locally Testable Automaton. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSTTCS ![In: Foundations of Software Technology and Theoretical Computer Science, 11th Conference, New Delhi, India, December 17-19, 1991, Proceedings, pp. 186-211, 1991, Springer, 3-540-54967-6. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
41 | Che W. Chiou, Ted C. Yang |
Fully testable PLA design with minimal extra input. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EURO-DAC ![In: European Design Automation Conference, EURO-DAC 1990, Glasgow, Scotland, UK, March 12-15, 1990, pp. 633-638, 1990, IEEE Computer Society, 0-8186-2024-2. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
40 | Ugur Kalay, Douglas V. Hall, Marek A. Perkowski |
A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(3), pp. 267-276, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
AND-EXOR realizations, Reed-Muller expressions, single stuck-at fault model, easily testable combinational networks, self-testable circuits, Built-in Self-Test (BIST), test pattern generation, Design for Testing (DFT), Universal test set |
40 | Syed Mahfuzul Aziz, C. N. Basheer, Joarder Kamruzzaman |
A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DELTA ![In: 1st IEEE International Workshop on Electronic Design, Test and Applications (DELTA 2002), 29-31 January 2002, Christchurch, New Zealand, pp. 504-506, 2002, IEEE Computer Society, 0-7695-1453-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Modified Booth, Generic, Synthesis, VHDL, Multiplier, C-Testable |
40 | Daniel Deveaux, Patrice Frison, Jean-Marc Jézéquel |
Increase Software Trustability with Self-Testable Classes in Java. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Australian Software Engineering Conference ![In: 13th Australian Software Engineering Conference (ASWEC 2001), 26-28 August 2001, Canberra, Australia, pp. 3-11, 2001, IEEE Computer Society, 0-7695-1254-2. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
self-testable class, java, XML, software engineering, Software component, software development process, design by contract, testing tools |
40 | Elena Dubrova, Jon C. Muzio |
Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 49(11), pp. 1285-1289, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Reed-Muller circuit, easily testable circuit, stuck-at fault, Multiple-valued function |
40 | Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas |
C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 2-4 November 1998, Austin, TX, USA, Proceedings, pp. 155-163, 1998, IEEE Computer Society, 0-8186-8832-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
robustly delay fault testable circuits, path delay faults, C-testability, Iterative-logic-arrays |
40 | Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri |
On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 10th International Conference on VLSI Design (VLSI Design 1997), 4-7 January 1997, Hyderabad, India, pp. 547-563, 1997, IEEE Computer Society, 0-8186-7755-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model |
40 | Valery A. Vardanian |
On completely robust path delay fault testable realization of logic functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 14th IEEE VLSI Test Symposium (VTS'96), April 28 - May 1, 1996, Princeton, NJ, USA, pp. 302-307, 1996, IEEE Computer Society, 0-8186-7304-4. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
robust path delay fault testable realization, two-level completely RPDFT realization, RPDFT-extension, input variables, VLSI, VLSI, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, integrated circuit testing, combinational circuits, combinational circuits, multivalued logic circuits, symmetric functions |
40 | Sukumar Nandi, Parimal Pal Chaudhuri |
Theory and applications of cellular automata for synthesis of easily testable combinational logic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 146-152, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
testable combinational logic, combinational logic blocks, test machine, data path synthesis phase, autonomous mode, aliasing error probability, associated lines, test application overheads, test parallelism, simultaneous testing, multiple combinational modules, graph theory, fault diagnosis, logic testing, high level synthesis, test generation, cellular automata, cellular automata, design for testability, combinational circuits, logic CAD, stuck-at faults, shift registers, cost effectiveness, registers, test vectors, test responses, state transition graph |
40 | P. Jayalakshmi, S. Vidya, S. Krishnakumar, K. Ravisankar, P. Kumar |
A highly testable ASIC for telephone signaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 8th International Conference on VLSI Design (VLSI Design 1995), 4-7 January 1995, New Delhi, India, pp. 183-, 1995, IEEE Computer Society, 0-8186-6905-5. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
telephone equipment, telecommunication signalling, highly testable ASIC, telephone signaling, online system diagnostic functions, integrated circuit testing, design for testability, fault simulation, application specific integrated circuits, integrated circuit design, functional simulation, digital integrated circuits, telephony |
40 | Pedro García 0001, Enrique Vidal 0001 |
Inference of k-Testable Languages in the Strict Sense and Application to Syntactic Pattern Recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Pattern Anal. Mach. Intell. ![In: IEEE Trans. Pattern Anal. Mach. Intell. 12(9), pp. 920-925, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
k-testable languages, deterministic finite-state automation, pattern recognition, computational complexity, inference mechanisms, formal languages, finite automata, grammars, grammars, strings, inductive inference, syntactic pattern recognition, inference algorithm |
34 | Kaoru Onodera |
New Morphic Characterizations of Languages in Chomsky Hierarchy Using Insertion and Locality. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LATA ![In: Language and Automata Theory and Applications, Third International Conference, LATA 2009, Tarragona, Spain, April 2-8, 2009. Proceedings, pp. 648-659, 2009, Springer, 978-3-642-00981-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Eli Ben-Sasson, Michael Viderman |
Composition of Semi-LTCs by Two-Wise Tensor Products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPROX-RANDOM ![In: Approximation, Randomization, and Combinatorial Optimization. Algorithms and Techniques, 12th International Workshop, APPROX 2009, and 13th International Workshop, RANDOM 2009, Berkeley, CA, USA, August 21-23, 2009. Proceedings, pp. 378-391, 2009, Springer, 978-3-642-03684-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
34 | Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi |
A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(9), pp. 1535-1544, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
34 | Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas, Michael Laisne, Hailong Cui, Tsvetomir Petrov |
Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 717-722, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Shirley Halevy, Oded Lachish, Ilan Newman, Dekel Tsur |
Testing Properties of Constraint-Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCC ![In: 22nd Annual IEEE Conference on Computational Complexity (CCC 2007), 13-16 June 2007, San Diego, California, USA, pp. 264-277, 2007, IEEE Computer Society, 0-7695-2780-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
34 | Noga Alon, Eldar Fischer, Michael Krivelevich, Mario Szegedy |
Efficient Testing of Large Graphs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Comb. ![In: Comb. 20(4), pp. 451-476, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
AMS Subject Classification (1991) Classes: 68R10, 05C35, 05C85 |
34 | Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey |
Fault Escapes in Duplex Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 18th IEEE VLSI Test Symposium (VTS 2000), 30 April - 4 May 2000, Montreal, Canada, pp. 453-458, 2000, IEEE Computer Society, 0-7695-0613-5. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
Duplex systems, Common-Mode Failures (CMFs), Test points, User-programmable logic, Data Integrity, Availability, Diversity |
34 | R. D. (Shawn) Blanton |
IDDQ-Testability of Tree Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 78-86, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
34 | Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal |
Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 11(1), pp. 55-67, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
digital circuit testing, test generation, fault models, delay test, path delay faults |
33 | Tali Kaufman, Madhu Sudan 0001 |
Algebraic property testing: the role of invariance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 40th Annual ACM Symposium on Theory of Computing, Victoria, British Columbia, Canada, May 17-20, 2008, pp. 403-412, 2008, ACM, 978-1-60558-047-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
error-correcting codes, locally testable codes, sublinear time algorithms |
33 | Hafizur Rahaman 0001, Dipak Kumar Kole, Debesh Kumar Das, Bhargab B. Bhattacharya |
On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 163-168, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Missing-gate faults, quantum computing, reversible logic, testable design, universal test set |
33 | Hafizur Rahaman 0001, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan |
Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}). ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 422-430, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
cryptography, polynomials, Multipliers, Galois field, error control code, Transition fault, C-testable |
33 | Shyue-Kung Lu, Cheng-Wen Wu, Ruei-Zong Hwang |
Cell delay fault testing for iterative logic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 9(3), pp. 311-316, 1996. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
cell delay fault, path delay fault, C-testable, iterative logic array, pseudoexhaustive testing |
32 | Thomas Place, Luc Segoufin |
A Decidable Characterization of Locally Testable Tree Languages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICALP (2) ![In: Automata, Languages and Programming, 36th Internatilonal Colloquium, ICALP 2009, Rhodes, Greece, July 5-12, 2009, Proceedings, Part II, pp. 285-296, 2009, Springer, 978-3-642-02929-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
32 | Philippe Golle, Richard Chow, Jessica Staddon |
Testable commitments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
StorageSS ![In: Proceedings of the 2008 ACM Workshop On Storage Security And Survivability, StorageSS 2008, Alexandria, VA, USA, October 31, 2008, pp. 37-42, 2008, ACM, 978-1-60558-299-3. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
litigation, responsive content, privacy, discovery, commitment scheme |
32 | Joaquin Gonzalez-Rodriguez, P. Rose, Daniel Ramos 0001, Doroteo T. Toledano, Javier Ortega-Garcia |
Emulating DNA: Rigorous Quantification of Evidential Weight in Transparent and Testable Forensic Speaker Recognition. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Speech Audio Process. ![In: IEEE Trans. Speech Audio Process. 15(7), pp. 2104-2115, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
32 | Görschwin Fey, Anna Bernasconi 0001, Valentina Ciriani, Rolf Drechsler |
On the Construction of Small Fully Testable Circuits with Low Depth. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 563-569, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
Displaying result #1 - #100 of 1392 (100 per page; Change: ) Pages: [ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ >>] |
|