Search results for "C-testable"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
82	A. N. Trahtman	Piecewise and Local Threshold Testability of DFA.	FCT	2001	DBLP DOI BibTeX RDF	locally threshold testable, piecewise testable, locally testable, syntactic semigroup, algorithm, automaton, transition graph
82	Roy S. Freedman	Testability of Software Components.	IEEE Trans. Software Eng.	1991	DBLP DOI BibTeX RDF	domain testability, domain-testable program, input-output inconsistencies, small test sets, test outputs, domain-testable specification, nondomain-testable specification, formal specification, controllability, software components, program testing, observability, program specifications
75	Hosahalli R. Srinivas, Bapiraju Vinnakota, Keshab K. Parhi	A C-testable carry-free divider.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
75	Niraj K. Jha, Abha Ahuja	Easily testable nonrestoring and restoring gate-level cellular array dividers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
73	R. D. (Shawn) Blanton, John P. Hayes	Design of a fast, easily testable ALU.	VTS	1996	DBLP DOI BibTeX RDF	ALU, adder design, L-testable design, level-testable, carry-lookahead addition, fault diagnosis, logic testing, integrated circuit testing, automatic testing, digital arithmetic, integrated circuit design, adders, logic arrays, test patterns, area overhead, functional faults, carry logic, arithmetic-logic unit, 8 bit
73	Ting-Yu Kuo, Chun-Yeh Liu, Kewal K. Saluja	An optimized testable architecture for finite state machines.	VTS	1995	DBLP DOI BibTeX RDF	optimized testable architecture, FSM synthesis, testable machine, transfer sequences, synthesis benchmark circuits, logic testing, finite state machines, finite state machines, sequential circuits, logic CAD, sequences, circuit optimisation, distinguishing sequences, synchronizing sequence
69	Eldar Fischer	Testing graphs for colorable properties.	SODA	2001	DBLP BibTeX RDF
68	Avraham Trakhtman	Reducing the Time Complexity of Testing for Local Threshold Testability.	CIAA	2003	DBLP DOI BibTeX RDF	threshold locally testable, algorithm, graph, Automaton
68	A. N. Trahtman	An Algorithm to Verify Local Threshold Testability of Deterministic Finite Automata.	WIA	1999	DBLP DOI BibTeX RDF	locally threshold testable, semigroup AMS subject classification 68Q25, 68Q68, 20M07, algorithm, deterministic finite automaton, 68Q45
67	Jonathan S. Ostroff, Faraz Ahmadi Torshizi	Testable Requirements and Specifications.	TAP	2007	DBLP DOI BibTeX RDF
67	Oded Goldreich 0001, Madhu Sudan 0001	Locally testable codes and PCPs of almost-linear length.	J. ACM	2006	DBLP DOI BibTeX RDF	error-correcting codes, derandomization, probabilistically checkable proofs, Proof verification
67	Irith Pomeranz	Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
67	Oded Goldreich 0001, Madhu Sudan 0001	Locally Testable Codes and PCPs of Almost-Linear Length.	FOCS	2002	DBLP DOI BibTeX RDF
67	Oliver Matz	On Piecewise Testable, Starfree, and Recognizable Picture Languages.	FoSSaCS	1998	DBLP DOI BibTeX RDF
67	Andres R. Takach, Niraj K. Jha	Easily testable gate-level and DCVS multipliers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
66	S. Crepaux-Motte, Mireille Jacomino, Rene David	An algebraic method for delay fault testing.	VTS	1996	DBLP DOI BibTeX RDF	input values, output function, robustly testable fault, nonrobustly testable fault, weakly verifiable, fault diagnosis, logic testing, delays, timing, Markov processes, random testing, delay fault testing, state transition, input vectors, algebraic method
58	Artur Czumaj, Christian Sohler	On testable properties in bounded degree graphs.	SODA	2007	DBLP BibTeX RDF
58	László Babai, Amir Shpilka, Daniel Stefankovic	Locally testable cyclic codes.	IEEE Trans. Inf. Theory	2005	DBLP DOI BibTeX RDF
58	Noga Alon, Asaf Shapira	A Characterization of the (natural) Graph Properties Testable with One-Sided Error.	FOCS	2005	DBLP DOI BibTeX RDF
58	Ronald D. Blanton, John P. Hayes	On the design of fast, easily testable ALU's.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
58	Dimitris Gizopoulos, Dimitris Nikolos, Antonis M. Paschalis, Constantin Halatsis	C-Testable modified-Booth multipliers.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	Booth multipliers, design for testability, C-testability, iterative logic arrays, carry lookahead adders, cell fault model
58	Sam M. Kim, Robert McNaughton, Robert McCloskey	An Upper Bound on the Order of Locally Testable Deterministic Finite Automata.	Optimal Algorithms	1989	DBLP DOI BibTeX RDF
57	Yun Shao 0002, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara	On Selecting Testable Paths in Scan Designs.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	testable path, delay testing, delay fault, path delay fault, path selection
57	Debesh K. Das, Bhargab B. Bhattacharya	Testable design of non-scan sequential circuits using extra logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	nonscan sequential circuits, sequentially redundant faults, multiple stuck-at-fault model, augmented logic, performance evaluation, logic testing, redundancy, test generation, design for testability, logic design, sequential circuits, logic synthesis, synchronous sequential circuits, benchmark circuits, testable design
57	S. M. Aziz	A C-testable modified Booth's array multiplier.	VLSI Design	1995	DBLP DOI BibTeX RDF	C-testable multiplier, modified Booth algorithm, gate-level design, parallel processing, logic testing, integrated circuit testing, digital arithmetic, stuck-at faults, CMOS logic circuits, multiplying circuits, logic arrays, array multiplier, parallel multiplier
50	Wei-Cheng Lai, Angela Krstic, Kwang-Ting Cheng	On Testing the Path Delay Faults of a Microprocessor Using its Instruction Set.	VTS	2000	DBLP DOI BibTeX RDF	Microprocessor self-testing, Path delay fault classification, Functionally testable paths, Functional tests, Delay fault testing
49	Himanshu Thapliyal, A. Prasad Vinod 0001	Designing Efficient Online Testable Reversible Adders With New Reversible Gate.	ISCAS	2007	DBLP DOI BibTeX RDF
49	Noga Alon, Eldar Fischer, Ilan Newman, Asaf Shapira	A combinatorial characterization of the testable graph properties: it's all about regularity.	STOC	2006	DBLP DOI BibTeX RDF	characterization, property testing, regularity lemma
49	Tali Kaufman, Simon Litsyn	Almost Orthogonal Linear Codes are Locally Testable.	FOCS	2005	DBLP DOI BibTeX RDF
49	László Babai, Amir Shpilka, Daniel Stefankovic	Locally Testable Cyclic Codes.	FOCS	2003	DBLP DOI BibTeX RDF
49	Pan Zhongliang	Fault Detection for Testable Realizations of Multiple-Valued Logic Functions.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF
49	Jerry Z. Gao 0002, Kamal Gupta, Shalini Gupta, Simon S. Y. Shim	On Building Testable Software Components.	ICCBSS	2002	DBLP DOI BibTeX RDF
49	Meghanad D. Wagh, Chien-In Henry Chen	High-level design synthesis with redundancy removal for high speed testable adders.	ISCAS (6)	1999	DBLP DOI BibTeX RDF
49	Sen-Pin Lin, Charles Njinda, Melvin A. Breuer	Generating a family of testable designs using the BILBO methodology.	J. Electron. Test.	1993	DBLP DOI BibTeX RDF	BILBO design system, built-in self-test, test scheduling, synthesis for testability
49	Srinivas Devadas, Kurt Keutzer	Synthesis and Optimization Procedures for Robustly Delay-Fault Testable Combinational Logic Circuits.	DAC	1990	DBLP DOI BibTeX RDF
48	Hafizur Rahaman 0001, Jimson Mathew, Dhiraj K. Pradhan, Abusaleh M. Jabir	C-testable bit parallel multipliers over GF(2m).	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	testing, cryptography, built-in self-test, digital signal processing, polynomials, VLSI design, stuck-at fault, TPG, fault, multiplier, Galois field, error control code, C-testable
48	Or Meir	Combinatorial construction of locally testable codes.	STOC	2008	DBLP DOI BibTeX RDF	pcps of proximity, probabilistically checkable proofs, locally testable codes
48	Eliane Martins, Cristina Maria Toyota, Rosileny Lie Yanagawa	Constructing Self-Testable Software Components.	DSN	2001	DBLP DOI BibTeX RDF	component testability, self-testable component, OO testing, design for testability
48	Masayuki Tsukisaka, Takashi Nanya	A testable design for asynchronous fine-grain pipeline circuits.	PRDC	2000	DBLP DOI BibTeX RDF	asynchronous fine-grain pipeline circuits, dynamic gates, high-performance datapath design, pipeline latches, scan latch libraries, logic testing, logic CAD, SPICE, CMOS technology, scan path, SPICE simulation, testable design
48	Ugur Kalay, Marek A. Perkowski, Douglas V. Hall	Highly Testable Boolean Ring Logic Circuits.	ISMVL	1999	DBLP DOI BibTeX RDF	Boolean Ring Circuits, Easily Testable Multiple-Valued Logic Circuits, Binary Implementation of MVL Circuits
48	Kwame Osei Boateng, Hiroshi Takahashi, Yuzo Takamatsu	Design of C-Testable Multipliers Based on the Modified Booth Algorithm.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	modified Booth Algorithm, c-testable design, design for testability, multiplier, exhaustive testing, cell fault model
48	Gosta Pada Biswas, Idranil Sen Gupta	Generalized modular design of testable m-out-of-n code checker.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testable m-out-of-n code checker, combinational logic port, combinational logic cells, unidirectional faults, complementary outputs, VLSI, fault diagnosis, logic testing, cellular automata, combinational circuits, fault location, stuck-at faults, logic arrays, cellular automaton, modular design, iterative array, initial state
48	Dong Sam Ha, Sudhakar M. Reddy	On the design of random pattern testable PLA based on weighted random pattern testing.	J. Electron. Test.	1992	DBLP DOI BibTeX RDF	built-in self-test, PLA, testable design, random pattern testability
47	Irith Pomeranz	Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains.	ITC	2003	DBLP DOI BibTeX RDF
47	Mohamed Soufi, Yvon Savaria, Bozena Kaminska	On the design of at-speed testable VLSI circuits.	VTS	1995	DBLP DOI BibTeX RDF	at-speed testable circuits, testable VLSI circuits, application test time, parallel vectors, stuck-at test, observability problems, probe observation point, VLSI, logic testing, integrated circuit testing, design for testability, design-for-testability, logic design, sequential circuits, sequential circuits, observability, fault coverages, integrated circuit design, integrated logic circuits, operational speed, DFT technique
43	Oded Lachish, Ilan Newman, Asaf Shapira	Space Complexity Vs. Query Complexity.	Comput. Complex.	2008	DBLP DOI BibTeX RDF	Subject classification. 68Q15, 68Q10
43	Oded Lachish, Ilan Newman, Asaf Shapira	Space Complexity vs. Query Complexity.	APPROX-RANDOM	2006	DBLP DOI BibTeX RDF
43	Noga Alon, Asaf Shapira	Linear equations, arithmetic progressions and hypergraph property testing.	SODA	2005	DBLP BibTeX RDF
43	Eldar Fischer, Ilan Newman	Testing versus estimation of graph properties.	STOC	2005	DBLP DOI BibTeX RDF	property testing, regularity lemma, graph properties, distance approximation
43	A. N. Trahtman	A Package TESTAS for Checking Some Kinds of Testability.	CIAA	2002	DBLP DOI BibTeX RDF
43	Srinivas Devadas, Hi-Keung Tony Ma, A. Richard Newton, Alberto L. Sangiovanni-Vincentelli	Irredundant sequential machines via optimal logic synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
42	A. N. Trahtman	A Polynomial Time Algorithm for Left [Right] Local Testability.	CIAA	2002	DBLP DOI BibTeX RDF	locally testable, algorithm, graph, language, semigroup, deterministic finite automaton
41	Swastik Kopparty, Shubhangi Saraf	Tolerant Linearity Testing and Locally Testable Codes.	APPROX-RANDOM	2009	DBLP DOI BibTeX RDF
41	Itai Benjamini, Oded Schramm, Asaf Shapira	Every minor-closed property of sparse graphs is testable.	STOC	2008	DBLP DOI BibTeX RDF	minor closed properties, graph algorithms, property testing
41	Soheila Bashardoust-Tajali, Jean-Pierre Corriveau	On Extracting Tests from a Testable Model in the Context of Domain Engineering.	ICECCS	2008	DBLP DOI BibTeX RDF
41	Tali Kaufman, Madhu Sudan 0001	Sparse Random Linear Codes are Locally Decodable and Testable.	FOCS	2007	DBLP DOI BibTeX RDF
41	Saravanan Padmanaban, Spyros Tragoudas	Efficient identification of (critical) testable path delay faults using decision diagrams.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
41	Jose L. Verdú-Mas, Rafael C. Carrasco, Jorge Calera-Rubio	Parsing with Probabilistic Strictly Locally Testable Tree Languages.	IEEE Trans. Pattern Anal. Mach. Intell.	2005	DBLP DOI BibTeX RDF
41	Noga Alon, Asaf Shapira	Every monotone graph property is testable.	STOC	2005	DBLP DOI BibTeX RDF	monotone properties, property testing, regularity lemma
41	Venkatesan Guruswami, Atri Rudra	Tolerant Locally Testable Codes.	APPROX-RANDOM	2005	DBLP DOI BibTeX RDF
41	Paul Valiant	The Tensor Product of Two Codes Is Not Necessarily Robustly Testable.	APPROX-RANDOM	2005	DBLP DOI BibTeX RDF
41	Eli Ben-Sasson, Madhu Sudan 0001	Robust Locally Testable Codes and Products of Codes.	APPROX-RANDOM	2004	DBLP DOI BibTeX RDF
41	Tomokazu Yoneda, Hideo Fujiwara	Design for Consecutive Testability of System-on-a-Chip with Built-In Self Testable Cores.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	consecutive transparency, built-in self test, design for testability, system-on-a-chip, test access mechanism, consecutive testability
41	Shyue-Kung Lu, Chien-Hung Yeh	Easily Testable and Fault-Tolerant Design of FFT Butterfly Networks.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
41	Satoshi Ohtake, Michiko Inoue, Hideo Fujiwara	A Method of Test Generation for Weakly Testable Data Paths Using Test Knowledge Extracted from RTL Description.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF
41	José Ruiz 0001, Salvador España Boquera, Pedro García 0001	Locally Threshold Testable Languages in Strict Sense: Application to the Inference Problem.	ICGI	1998	DBLP DOI BibTeX RDF
41	Dariusz Bojanowicz	How Faults can be Simulated in Self-Testable VLSI Digital Circuits.	EUROMICRO	1998	DBLP DOI BibTeX RDF
41	Shyue-Kung Lu, Jen-Chuan Wang, Cheng-Wen Wu	C-testable design techniques for iterative logic arrays.	IEEE Trans. Very Large Scale Integr. Syst.	1995	DBLP DOI BibTeX RDF
41	Chen-Huan Chiang, Sandeep K. Gupta 0001	Random pattern testable logic synthesis.	ICCAD	1994	DBLP DOI BibTeX RDF
41	Gwo-Haur Hwang, Wen-Zen Shen	Restructuring and logic minimization for testable PLA.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
41	Bernhard Eschermann, Hans-Joachim Wunderlich	Optimized synthesis techniques for testable sequential circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
41	Sam M. Kim, Robert McNaughton	Computing the Order of a Locally Testable Automaton.	FSTTCS	1991	DBLP DOI BibTeX RDF
41	Che W. Chiou, Ted C. Yang	Fully testable PLA design with minimal extra input.	EURO-DAC	1990	DBLP DOI BibTeX RDF
40	Ugur Kalay, Douglas V. Hall, Marek A. Perkowski	A Minimal Universal Test Set for Self-Test of EXOR-Sum-of-Products Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	AND-EXOR realizations, Reed-Muller expressions, single stuck-at fault model, easily testable combinational networks, self-testable circuits, Built-in Self-Test (BIST), test pattern generation, Design for Testing (DFT), Universal test set
40	Syed Mahfuzul Aziz, C. N. Basheer, Joarder Kamruzzaman	A Synthesisable VHDL Model for an Easily Testable Generalised Multiplier.	DELTA	2002	DBLP DOI BibTeX RDF	Modified Booth, Generic, Synthesis, VHDL, Multiplier, C-Testable
40	Daniel Deveaux, Patrice Frison, Jean-Marc Jézéquel	Increase Software Trustability with Self-Testable Classes in Java.	Australian Software Engineering Conference	2001	DBLP DOI BibTeX RDF	self-testable class, java, XML, software engineering, Software component, software development process, design by contract, testing tools
40	Elena Dubrova, Jon C. Muzio	Easily Testable Multiple-Valued Logic Circuits Derived from Reed-Muller Circuits.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Reed-Muller circuit, easily testable circuit, stuck-at fault, Multiple-valued function
40	Th. Haniotakis, Dimitris Nikolos, Y. Tsiatouhas	C-Testable One-Dimensional ILAs with Respect to Path Delay Faults: Theory and Applications.	DFT	1998	DBLP DOI BibTeX RDF	robustly delay fault testable circuits, path delay faults, C-testability, Iterative-logic-arrays
40	Chunduri Rama Mohan, Srobona Mitra, Partha Pal Chaudhuri	On Incorporation of BIST for the Synthesis of Easily and Fully Testable Controllers.	VLSI Design	1997	DBLP DOI BibTeX RDF	fully testable controllers, testing scheme, Cadence, target library, built-in self test, cellular automata, VHDL, ATPGs, BIST, testability, FSMs, partial scan, VERILOG, area overhead, RTL designs, SYNERGY, full scan, stuck-at fault model
40	Valery A. Vardanian	On completely robust path delay fault testable realization of logic functions.	VTS	1996	DBLP DOI BibTeX RDF	robust path delay fault testable realization, two-level completely RPDFT realization, RPDFT-extension, input variables, VLSI, VLSI, fault diagnosis, logic testing, delays, Boolean functions, Boolean functions, integrated circuit testing, combinational circuits, combinational circuits, multivalued logic circuits, symmetric functions
40	Sukumar Nandi, Parimal Pal Chaudhuri	Theory and applications of cellular automata for synthesis of easily testable combinational logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testable combinational logic, combinational logic blocks, test machine, data path synthesis phase, autonomous mode, aliasing error probability, associated lines, test application overheads, test parallelism, simultaneous testing, multiple combinational modules, graph theory, fault diagnosis, logic testing, high level synthesis, test generation, cellular automata, cellular automata, design for testability, combinational circuits, logic CAD, stuck-at faults, shift registers, cost effectiveness, registers, test vectors, test responses, state transition graph
40	P. Jayalakshmi, S. Vidya, S. Krishnakumar, K. Ravisankar, P. Kumar	A highly testable ASIC for telephone signaling.	VLSI Design	1995	DBLP DOI BibTeX RDF	telephone equipment, telecommunication signalling, highly testable ASIC, telephone signaling, online system diagnostic functions, integrated circuit testing, design for testability, fault simulation, application specific integrated circuits, integrated circuit design, functional simulation, digital integrated circuits, telephony
40	Pedro García 0001, Enrique Vidal 0001	Inference of k-Testable Languages in the Strict Sense and Application to Syntactic Pattern Recognition.	IEEE Trans. Pattern Anal. Mach. Intell.	1990	DBLP DOI BibTeX RDF	k-testable languages, deterministic finite-state automation, pattern recognition, computational complexity, inference mechanisms, formal languages, finite automata, grammars, grammars, strings, inductive inference, syntactic pattern recognition, inference algorithm
34	Kaoru Onodera	New Morphic Characterizations of Languages in Chomsky Hierarchy Using Insertion and Locality.	LATA	2009	DBLP DOI BibTeX RDF
34	Eli Ben-Sasson, Michael Viderman	Composition of Semi-LTCs by Two-Wise Tensor Products.	APPROX-RANDOM	2009	DBLP DOI BibTeX RDF
34	Hideo Fujiwara, Hiroyuki Iwata, Tomokazu Yoneda, Chia Yee Ooi	A Nonscan Design-for-Testability Method for Register-Transfer-Level Circuits to Guarantee Linear-Depth Time Expansion Models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
34	Rajsekhar Adapa, Edward Flanigan, Spyros Tragoudas, Michael Laisne, Hailong Cui, Tsvetomir Petrov	Function-Based Test Generation for (Non-Robust) Path Delay Faults Using the Launch-off-Capture Scan Architecture.	ISQED	2007	DBLP DOI BibTeX RDF
34	Shirley Halevy, Oded Lachish, Ilan Newman, Dekel Tsur	Testing Properties of Constraint-Graphs.	CCC	2007	DBLP DOI BibTeX RDF
34	Noga Alon, Eldar Fischer, Michael Krivelevich, Mario Szegedy	Efficient Testing of Large Graphs.	Comb.	2000	DBLP DOI BibTeX RDF	AMS Subject Classification (1991) Classes: 68R10, 05C35, 05C85
34	Subhasish Mitra, Nirmal R. Saxena, Edward J. McCluskey	Fault Escapes in Duplex Systems.	VTS	2000	DBLP DOI BibTeX RDF	Duplex systems, Common-Mode Failures (CMFs), Test points, User-programmable logic, Data Integrity, Availability, Diversity
34	R. D. (Shawn) Blanton	IDDQ-Testability of Tree Circuits.	VLSI Design	1999	DBLP DOI BibTeX RDF
34	Marwan A. Gharaybeh, Michael L. Bushnell, Vishwani D. Agrawal	Classification and Test Generation for Path-Delay Faults Using Single Struck-at Fault Tests.	J. Electron. Test.	1997	DBLP DOI BibTeX RDF	digital circuit testing, test generation, fault models, delay test, path delay faults
33	Tali Kaufman, Madhu Sudan 0001	Algebraic property testing: the role of invariance.	STOC	2008	DBLP DOI BibTeX RDF	error-correcting codes, locally testable codes, sublinear time algorithms
33	Hafizur Rahaman 0001, Dipak Kumar Kole, Debesh Kumar Das, Bhargab B. Bhattacharya	On the Detection of Missing-Gate Faults in Reversible Circuits by a Universal Test Set.	VLSI Design	2008	DBLP DOI BibTeX RDF	Missing-gate faults, quantum computing, reversible logic, testable design, universal test set
33	Hafizur Rahaman 0001, Jimson Mathew, Biplab K. Sikdar, Dhiraj K. Pradhan	Transition Fault Testability in Bit Parallel Multipliers over GF(2^{m}).	VTS	2007	DBLP DOI BibTeX RDF	cryptography, polynomials, Multipliers, Galois field, error control code, Transition fault, C-testable
33	Shyue-Kung Lu, Cheng-Wen Wu, Ruei-Zong Hwang	Cell delay fault testing for iterative logic arrays.	J. Electron. Test.	1996	DBLP DOI BibTeX RDF	cell delay fault, path delay fault, C-testable, iterative logic array, pseudoexhaustive testing
32	Thomas Place, Luc Segoufin	A Decidable Characterization of Locally Testable Tree Languages.	ICALP (2)	2009	DBLP DOI BibTeX RDF
32	Philippe Golle, Richard Chow, Jessica Staddon	Testable commitments.	StorageSS	2008	DBLP DOI BibTeX RDF	litigation, responsive content, privacy, discovery, commitment scheme
32	Joaquin Gonzalez-Rodriguez, P. Rose, Daniel Ramos 0001, Doroteo T. Toledano, Javier Ortega-Garcia	Emulating DNA: Rigorous Quantification of Evidential Weight in Transparent and Testable Forensic Speaker Recognition.	IEEE Trans. Speech Audio Process.	2007	DBLP DOI BibTeX RDF
32	Görschwin Fey, Anna Bernasconi 0001, Valentina Ciriani, Rolf Drechsler	On the Construction of Small Fully Testable Circuits with Low Depth.	DSD	2007	DBLP DOI BibTeX RDF