Search results for "CLB"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
88	Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001	An Area and Configuration-Bit Optimized CLB Architecture and Timing-Driven Packing for FPGAs.	VLSI Design	2006	DBLP DOI BibTeX RDF
88	Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001	A novel CLB architecture and circuit packing algorithm for logic-area reduction in SRAM-based FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
73	Shantanu Dutt, Li Li	Trust-Based Design and Check of FPGA Circuits Using Two-Level Randomized ECC Structures.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	masking probability, parity groups, parity randomization, trust checking, trust-based design, FPGAs, Error-correcting codes
73	Jason Meyer, Fatih Kocan	Sharing of SRAM Tables Among NPN-Equivalent LUTs in SRAM-Based FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
59	Wei Liang Huang, Fred J. Meyer, Fabrizio Lombardi	Multiple fault detection in logic resources of FPGAs.	DFT	1997	DBLP DOI BibTeX RDF	logic resources, AND tree, OR tree, CLB test generation, field programmable gate arrays, fault model, configurability, testability, programmability, multiple fault detection, SRAM-based FPGA
59	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs.	IPDPS	2005	DBLP DOI BibTeX RDF
59	Pin Zhou, Wei Liu 0014, Long Fei, Shan Lu 0001, Feng Qin, Yuanyuan Zhou 0001, Samuel P. Midkiff, Josep Torrellas	AccMon: Automatically Detecting Memory-Related Bugs via Program Counter-Based Invariants.	MICRO	2004	DBLP DOI BibTeX RDF
59	Salvatore Pontarelli, Gian Carlo Cardarilli, A. Leandri, Marco Ottavi, Marco Re, Adelio Salsano	A self-checking cell logic block for fault tolerant FPGAs.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
58	Peter M. Kelly, T. Martin McGinnity, Liam P. Maguire, L. J. McDaid	A Quaternary CLB Design Using Quantum Device Technology on Silicon for FPGA Neural Network Architectures.	IWANN	2005	DBLP DOI BibTeX RDF
58	Noriyoshi Itazaki, Fumiro Matsuki, Yasuyuki Matsumoto, Kozo Kinoshita	Built-In Self-Test for Multiple CLB Faults of a LUT Type FPGA.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
58	Chia-Ching Tung, Ruchi B. Rungta, Eric Peskin	Simulation of a QCA-based CLB and a multi-CLB application.	FPT	2009	DBLP DOI BibTeX RDF
44	Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali	Testing embedded RAM modules in SRAM-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
44	Vivek Garg, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001	A function generator-based reconfigurable system.	ASP-DAC	2005	DBLP DOI BibTeX RDF
44	Xiaoling Sun, Jian Xu, Pieter M. Trouborst	Testing Xilinx XC4000 Configurable Logic Blocks with Carry Logic Modules.	DFT	2001	DBLP DOI BibTeX RDF	configurable logic blocks, fault diagnosis, BIST, FPGA testing
44	K. K. Lee, D. F. Wong 0001	An Exact Tree-Based Structural Technology Mapping Algorithm for Configurable Logic Blocks in FPGAs.	ICCD	1999	DBLP DOI BibTeX RDF
44	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	IDDQ Testing of Bridging Faults in Logic Resources of Reconfigurable Field Programmable Gate Arrays.	IEEE Trans. Computers	1998	DBLP DOI BibTeX RDF
44	A. R. Naseer, M. Balakrishnan, Anshul Kumar	Direct mapping of RTL structures onto LUT-based FPGA's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
44	Jason Cong, Yean-Yow Hwang	Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation.	FPGA	1998	DBLP DOI BibTeX RDF
30	Kuan Zhou, John F. McDonald 0001	Multi-GHz SiGe design methodologies for reconfigurable computing.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	CLB, virtex, FPGA, SiGe
29	Vasilios Kalenteridis, Haroula Pournara, Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, Ilias Pappas 0001, Spiridon Nikolaidis 0001, Stilianos Siskos, D. J. Soudris, Adonios Thanailakis	An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development.	IPDPS	2004	DBLP DOI BibTeX RDF	Low Power FPGA interconnect architecture, CLB Architecture, Graphical User Interface
29	Helena Krupnova, Gabriele Saucier	FPGA Technology Snapshot: Current Devices and Design Tools.	IEEE International Workshop on Rapid System Prototyping	2000	DBLP DOI BibTeX RDF	Configurable Logic Block (CLB), System on a Programmable Chip (SOPC), FPGAs, routing, synthesis, placement, Rapid prototyping, floorplanning, timing optimization, macro block
29	Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert	Architectural Modifications to Enhance the Floating-Point Performance of FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
29	S. Raghunath, Syed Mahfuzul Aziz	Design of an Area Efficient High-Speed Color FDWT Processor.	APCCAS	2006	DBLP DOI BibTeX RDF
29	Saumil Shah, Puneet Gupta 0001, Andrew B. Kahng	Standard cell library optimization for leakage reduction.	DAC	2006	DBLP DOI BibTeX RDF	gate-length biasing, library optimization, leakage reduction
29	Naoki Miyata, Toru Ishida 0001	Community-Based Load Balancing for Massively Multi-Agent Systems.	MMAS/LSMAS/CCMMS	2006	DBLP DOI BibTeX RDF	scalability and performance issues: robustness, fault tolerance and dependability, mobile agents
29	Yirong OuYang, Jiarong Tong	A New Universal Test Pattern Auto-generating Approach for FPGA Logic Resources (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
29	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Cluster-based detection of SEU-caused errors in LUTs of SRAM-based FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
29	Marvin Tom, Guy G. Lemieux	Logic block clustering of large designs for channel-width constrained FPGAs.	DAC	2005	DBLP DOI BibTeX RDF	channel width constraints, clustering, field-programmable gate arrays (FPGA), packing
29	Tong Ye, Qingji Zeng, Yikai Su, Lufeng Leng, Wei Wei 0010, Zhizhong Zhang, Wei Guo 0003, Yaohui Jin	On-line integrated routing in dynamic multifiber IP/WDM networks.	IEEE J. Sel. Areas Commun.	2004	DBLP DOI BibTeX RDF
29	Shyue-Kung Lu, Hung-Chin Wu, Shoei-Jia Yan, Yu-Cheng Tsai	Testing and Diagnosis Techniques for LUT-Based FPGA's.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
29	Nazar Abbas Saqib, Francisco Rodríguez-Henríquez, Arturo Díaz-Pérez	AES Algorithm Implementation-An efficient approach for Sequential and Pipeline Architectures.	ENC	2003	DBLP DOI BibTeX RDF
29	Shyue-Kung Lu, Chung-Yang Chen	Fault Detection and Fault Diagnosis Technoques for Lookup Table FPGA's.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
29	Xiaoling Sun, Jian Xu, Pieter M. Trouborst	Testing Carry Logic Modules of SRAM-based FPGAs.	MTDT	2001	DBLP DOI BibTeX RDF
29	Wen-Jong Fang, Allen C.-H. Wu	Multiway FPGA partitioning by fully exploiting design hierarchy.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	fine-grained synthesis, functional clustering, multi-way partitioning, multiple-FPGA synthesis
29	Chi-Chou Kao, Yen-Tai Lai	A routability and performance driven technology mapping algorithm for LUT based FPGA designs.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
29	Madhav Y. Chikodikar, Shridhar Laddha, Ashish Sirasao	A Technology Mapper for Xilinx FPGAs.	VLSI Design	1997	DBLP DOI BibTeX RDF
29	Wen-Jong Fang, Allen C.-H. Wu	Multi-Way FPGA Partitioning by Fully Exploiting Design Hierarchy.	DAC	1997	DBLP DOI BibTeX RDF
29	Jiarui Wang, Jing Mai, Zhixiong Di, Yibo Lin	A Robust FPGA Router with Concurrent Intra-CLB Rerouting.	ASP-DAC	2023	DBLP DOI BibTeX RDF
29	Shashwat Shrivastava, Stefan Nikolic 0001, Chirag Ravishankar, Dinesh Gaitonde, Mirjana Stojilovic	IIBLAST: Speeding Up Commercial FPGA Routing by Decoupling and Mitigating the Intra-CLB Bottleneck.	ICCAD	2023	DBLP DOI BibTeX RDF
29	Yongqiang Zhang 0006, Chunsong Zhu, Xin Cheng 0001, Guangjun Xie	Design and Implementation of SRAM for LUT and CLB Using Clocking Mechanism in Quantum-Dot Cellular Automata.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
29	Debobroto Das Robin, Javed I. Khan	CLB: Coarse-Grained Precision Traffic-Aware Weighted Cost Multipath Load Balancing on PISA.	IEEE Trans. Netw. Serv. Manag.	2022	DBLP DOI BibTeX RDF
29	Byomakesh Mahapatra, Rahul Kumar, Ashok K. Turuk, Sarat Kumar Patra	CLB: a multilevel co-operative load balancing algorithm for C-RAN architecture.	Digit. Commun. Networks	2019	DBLP DOI BibTeX RDF
29	Shang-Liang Chen, Yun-Yao Chen, Suang-Hong Kuo	CLB: A novel load balancing architecture and algorithm for cloud services.	Comput. Electr. Eng.	2017	DBLP DOI BibTeX RDF
29	Sanjeet Kumar Nayak, Sujata Mohanty, Banshidhar Majhi	CLB-ECC: Certificateless Blind Signature Using ECC.	J. Inf. Process. Syst.	2017	DBLP DOI BibTeX RDF
29	Anzhela Yu. Matrosova, Sergey Ostanin, Irina Kirienko	Increasing Manufacturing Yield Using Partially Programmable Circuits with CLB Implementation of Incompletely Specified Boolean Function of the Corresponding Sub-Circuit.	DDECS	2015	DBLP DOI BibTeX RDF
29	Shant Chandrakar, Dinesh Gaitonde, Trevor Bauer	Enhancements in UltraScale CLB Architecture.	FPGA	2015	DBLP DOI BibTeX RDF
29	Oluseyi A. Ayorinde, He Qi, Yu Huang 0015, Benton H. Calhoun	Using island-style bi-directional intra-CLB routing in low-power FPGAs.	FPL	2015	DBLP DOI BibTeX RDF
29	Yuan Xue, Patrick Cronin, Chengmo Yang, Jingtong Hu	Fine-tuning CLB placement to speed up reconfigurations in NVM-based FPGAs.	FPL	2015	DBLP DOI BibTeX RDF
29	Moein Kianpour, Reza Sabbaghi-Nadooshan	A conventional design and simulation for CLB implementation of an FPGA quantum-dot cellular automata.	Microprocess. Microsystems	2014	DBLP DOI BibTeX RDF
29	Kejun Dong, Ji Li, Kai Nan, Wilfred W. Li	Biomedical Research Data Cloud Services with Duckling Collaboration LiBrary (CLB).	e-Science	2013	DBLP DOI BibTeX RDF
29	Vyacheslav S. Kharchenko, V. Duzhyi, Volodymyr Sklyar, Andriy V. Volkoviy	Diversity assessment of multi-version NPP I&C Systems: NUREG7007 and CLB-BASED techniques.	EWDTS	2013	DBLP DOI BibTeX RDF
29	Arwa Ben Dhia, Lirida A. B. Naviner, Philippe Matherat	Evaluating CLB designs under multiple SETs in SRAM-based FPGAs.	DFTS	2013	DBLP DOI BibTeX RDF
29	Jun Wu, Yong-Bin Kim, Minsu Choi	Configurable logic block (CLB) design for Asynchronous Nanowire Crossbar system.	MWSCAS	2012	DBLP DOI BibTeX RDF
29	Moein Kianpour, Reza Sabbaghi-Nadooshan	A conventional design for CLB implementation of a FPGA in quantum-dot cellular automata (QCA).	NANOARCH	2012	DBLP DOI BibTeX RDF
29	Alireza Rohani, Hamid R. Zarandi	A New CLB Architecture for Tolerating SEU in SRAM-Based FPGAs.	ReConFig	2009	DBLP DOI BibTeX RDF	Dependability, FPGA-Test
29	Choong-Mo Youn, Jae-Jin Kim	A CLB-based CPLD Low-power Technology Mapping Algorithm considered a Trade-off.	J. Inform. and Commun. Convergence Engineering	2007	DBLP BibTeX RDF
29	Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan	CLB-based Detection and Correction of Bit-flip faults in SRAM-based FPGAs.	ISCAS	2007	DBLP DOI BibTeX RDF
29	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Vijaykrishnan Narayanan	A novel CLB architecture to detect and correct SEU in LUTs of SRAM-based FPGAs.	FPT	2004	DBLP DOI BibTeX RDF
29	Bruce Schulman, Gerald G. Pechanek	A 90k Gate "CLB" for Parallel Distributed Computing.	IPDPS Workshops	2000	DBLP DOI BibTeX RDF
15	Mohammed Y. Niamat, Sowmya Panuganti, Tejas Raviraj	Modeling and simulation of nano quantum FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	nano, fpga, qca, quantum
15	Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal	A high-level clustering algorithm targeting dual Vdd FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	clustering, field programmable gate arrays, partitioning, placement, voltage scaling, Dynamic power
15	Kanupriya Gulati, Sunil P. Khatri	Improving FPGA routability using network coding.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	FPGA, network coding
15	Doris T. Chen, Kristofer Vorwerk, Andrew A. Kennings	Improving Timing-Driven FPGA Packing With Physical Information.	FPL	2007	DBLP DOI BibTeX RDF
15	Bradley R. Quinton, Steven J. E. Wilton	Embedded Programmable Logic Core Enhancements for System Bus Interfaces.	FPL	2007	DBLP DOI BibTeX RDF
15	Hamid R. Zarandi, Seyed Ghassem Miremadi, Costas Argyrides, Dhiraj K. Pradhan	Fast SEU Detection and Correction in LUT Configuration Bits of SRAM-based FPGAs.	IPDPS	2007	DBLP DOI BibTeX RDF
15	Guijun Gao, Youren Wang, Jiang Cui, Rui Yao	Research on Multi-objective On-Line Evolution Technology of Digital Circuit Based on FPGA Model.	ICES	2007	DBLP DOI BibTeX RDF	On-line Evolution, Multi-objective Evolutionary Method, FPGA Model, Digital Circuit, Evolvable Hardware
15	Kostas Siozios, Dimitrios Soudris, Antonios Thanailakis	Efficient Power Management Strategy of FPGAs Using a Novel Placement Technique.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
15	Senthamaraikannan Raghunath, Syed Mahfuzul Aziz	High Speed Area Efficient Multi-resolution 2-D 9/7 filter DWT Processor.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
15	Norbert Pramstaller, Christian Rechberger, Vincent Rijmen	A compact FPGA implementation of the hash function whirlpool.	FPGA	2006	DBLP DOI BibTeX RDF	compact hardware implementation, FPGA, hash function, whirlpool
15	Joaquín Olivares 0001, Ignacio Benavides, Javier Hormigo, Julio Villalba, Emilio L. Zapata	Fast Full-Search Block Matching Algorithm Motion Estimation Alternatives in FPGA.	FPL	2006	DBLP DOI BibTeX RDF
15	Allen Michalski, Duncan A. Buell	A Scalable Architecture for RSA Cryptography on Large FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
15	Allen Michalski, Duncan A. Buell	A Scalable Architecture for RSA Cryptography on Large FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
15	Alexander A. Petrovsky, Sergei L. Shkredov	Automatic Generation of Split-Radix 2-4 Parallel-Pipeline FFT Processors: Hardware Reconfiguration and Core Optimizations.	PARELEC	2006	DBLP DOI BibTeX RDF
15	Sai Gopalan, Gayathri Venkataraman, Sabu Emmanuel	FPGA Implementation and Analyses of Cluster Maintenance Algorithms in Mobile Ad-Hoc Networks.	Asia-Pacific Computer Systems Architecture Conference	2005	DBLP DOI BibTeX RDF	cluster maintenance algorithm, VHDL (Very High Speed Integrated Circuit Hardware Description Language), FPGA (Field Programmable Gate Arrays), Mobile ad-hoc networks
15	Chun-Chieh Wang, Jing-Jia Liou, Yen-Lin Peng, Chih-Tsun Huang, Cheng-Wen Wu	A BIST Scheme for FPGA Interconnect Delay Faults.	VTS	2005	DBLP DOI BibTeX RDF
15	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Detecting SEU-Caused Routing Errors in SRAM-Based FPGAs.	VLSI Design	2005	DBLP DOI BibTeX RDF	Complex Logic Blocks, Routing Errors, Vertex Coloring problem, Fault Tolerance, Field Programmable Gate Arrays, Graph Theory, Single Event Upset
15	Norbert Pramstaller, Johannes Wolkerstorfer	A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays.	FPL	2004	DBLP DOI BibTeX RDF
15	Frank Honoré, Benton H. Calhoun, Anantha P. Chandrakasan	Power-aware architectures and circuits for FPGA-based signal processing.	FPGA	2003	DBLP DOI BibTeX RDF
15	François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat	A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL.	FPGA	2003	DBLP DOI BibTeX RDF	AES RIJNDAEL, high encryption rates, FPGA, cryptography, reconfigurable hardware
15	Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, Russell P. Kraft, John F. McDonald 0001	A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology.	FPGA	2003	DBLP DOI BibTeX RDF	basic cell, FPGA, CML, SiGe
15	Nazar Abbas Saqib, Francisco Rodríguez-Henríquez, Arturo Díaz-Pérez	Two Approaches for a Single-Chip FPGA Implementation of an Encryptor/Decryptor AES Core.	FPL	2003	DBLP DOI BibTeX RDF
15	Seok-Bum Ko, Jien-Chung Lo	A Novel Technology Mapping Method for AND/XOR Expressions.	ISMVL	2003	DBLP DOI BibTeX RDF
15	Benton H. Calhoun, Frank Honoré, Anantha P. Chandrakasan	Design methodology for fine-grained leakage control in MTCMOS.	ISLPED	2003	DBLP DOI BibTeX RDF	fine-grain sleep regions, sneak leakage, low power, design methodology, leakage, circuit design, sleep mode, MTCMOS
15	Li Shang, Alireza Kaviani, Kusuma Bathala	Dynamic power consumption in Virtex[tm]-II FPGA family.	FPGA	2002	DBLP DOI BibTeX RDF
15	Anshuman Nayak, Malay Haldar, Alok N. Choudhary, Prithviraj Banerjee	Accurate Area and Delay Estimators for FPGAs.	DATE	2002	DBLP DOI BibTeX RDF
15	Channakeshav, Kuan Zhou, Jong-Ru Guo, Chao You, Bryan S. Goda, Russell P. Kraft, John F. McDonald 0001	Fast SiGe HBT BiCMOS FPGAs with New Architecture and Power Saving Techniques.	FPL	2002	DBLP DOI BibTeX RDF
15	Channakeshav, Kuan Zhou, Russell P. Kraft, John F. McDonald 0001	Gigahertz FPGAs with New Power Saving Techniques and Decoding Logic.	Evolvable Hardware	2002	DBLP DOI BibTeX RDF
15	Jason Cong, Yean-Yow Hwang	Boolean matching for LUT-based logic blocks with applications toarchitecture evaluation and technology mapping.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
15	Gennadiy Kiryukhin, Mehmet Celenk	Implementation of 2D-DCT on XC4000 series FPGA using DFT-based DSFG and DA architectures.	ICIP (3)	2001	DBLP DOI BibTeX RDF
15	Pawel Chodowiec, Po Khuon, Kris Gaj	Fast implementations of secret-key block ciphers using mixed inner- and outer-round pipelining.	FPGA	2001	DBLP DOI BibTeX RDF	fast architectures, secret-key ciphers, pipelining, AES
15	Srihari Cadambi, Seth Copen Goldstein	Static Profile-Driven Compilation for FPGAs.	FPL	2001	DBLP DOI BibTeX RDF
15	Valery Sklyarov	Synthesis and Implementation of RAM-Based Finite State Machines in FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
15	Kamlesh Rath, Sirisha Tangirala, Patrick Friel, Poras T. Balsara, Jose Flores, John P. Wadley	Reconfigurable Array Media Processor (RAMP).	FCCM	2000	DBLP DOI BibTeX RDF
15	Jinwoo Suh, Dong-In Kang, Stephen P. Crago	A Communication Scheduling Algorithm for Multi-FPGA Systems.	FCCM	2000	DBLP DOI BibTeX RDF
15	Parag K. Lala, Alvernon Walker	An On-Line Reconfigurable FPGA Architecture.	DFT	2000	DBLP DOI BibTeX RDF
15	Lijun Gao, Sarvesh Shrivastava, Hanho Lee, Gerald E. Sobelman	A Compact Fast Variable Key Size Elliptic Curve Cryptosystem Coprocessor.	FCCM	1999	DBLP DOI BibTeX RDF	FPGA, Elliptic curve cryptography, Reconfigurable hardware, Scalar multiplication, Galois field, Coprocessor
15	Parag K. Lala, Alfred L. Burress	A technique for designing self-checking logic for FPGAs.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
15	Lijun Gao, Sarvesh Shrivastava, Gerald E. Sobelman	Elliptic Curve Scalar Multiplier Design Using FPGAs.	CHES	1999	DBLP DOI BibTeX RDF	FPGA, public-key cryptography, elliptic curves, reconfigurable hardware, scalar multiplication, Galois field, coprocessor
15	Tomoo Inoue, Satoshi Miyazaki, Hideo Fujiwara	Universal Fault Diagnosis for Lookup Table FPGAs.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
15	Takashi Miyamori, Kunle Olukotun	A Quantitative Analysis of Reconfigurable Coprocessors for Multimedia Applications.	FCCM	1998	DBLP DOI BibTeX RDF