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Publication years (Num. hits)
1977-1986 (17) 1988-1994 (22) 1995-1996 (17) 1997-1998 (23) 1999 (39) 2000 (20) 2001 (33) 2002 (29) 2003 (56) 2004 (42) 2005 (50) 2006 (95) 2007 (69) 2008 (83) 2009 (68) 2010 (55) 2011 (72) 2012 (70) 2013 (71) 2014 (75) 2015 (99) 2016 (91) 2017 (81) 2018 (83) 2019 (88) 2020 (100) 2021 (93) 2022 (102) 2023 (98) 2024 (27)
Publication types (Num. hits)
article(742) incollection(1) inproceedings(1122) phdthesis(3)
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Found 1868 publication records. Showing 1868 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
120Martin John Burbidge Detection and Evaluation of Deterministic Jitter Causes in CP-PLL's Due to Macro Level Faults and Pre-Detection Using Simple Methods. Search on Bibsonomy J. Electron. Test. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF CP-PLL, deterministic jitter, jitter, PLL
118Martin John Burbidge, Jim Tijou, Andrew Richardson 0001 Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loops. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF CP-PLL, TEST, DfT, BIST, PLL
89Chanwoo Park, Jinbeom Lee, Younglok Kim Modified Reduced Constellation PLL for Higher Order QAM. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
89Martin John Burbidge, Frédéric Poullet, Jim Tijou, Andrew Richardson 0001 Investigations for Minimum Invasion Digital Only Built-In "Ramp" Based Test Techniques for Charge Pump PLL's. Search on Bibsonomy J. Electron. Test. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF test, DfT, BIST, jitter, phase locked loop
88Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera A dynamically phase adjusting PLL with a variable delay. Search on Bibsonomy ASP-DAC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF phase adjust, variable delay, lock-up, PLL
78T. M. Almaida, Moisés Simões Piedade High performance analog and digital PLL design. Search on Bibsonomy ISCAS (4) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
67Ching-Lung Ti, Yao-Hong Liu, Tsung-Hsien Lin A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
67Xiaolue Lai, Yayun Wan, Jaijeet S. Roychowdhury Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
67Thomas Olsson 0001, Peter Nilsson 0001 A digitally controlled PLL for digital SOCs. Search on Bibsonomy ISCAS (5) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
65Prakash Easwaran, Prasenjit Bhowmik, Rupak Ghayal Specification Driven Design of Phase Locked Loops. Search on Bibsonomy VLSI Design The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
65Abdelohahab Djemouai, Mohamad Sawan Fast-locking low-jitter integrated CMOS phase-locked loop. Search on Bibsonomy ISCAS (1) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
56Yang Liu, Ashok Kumar Srivastava, Yao Xu A switchable PLL frequency synthesizer and hot carrier effects. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF cmos phase-locked loop, hot carrier effects, jitter, voltage-controlled oscillator, phase noise
56Yasuaki Sumi, Shigeki Obote, Naoki Kitai, Ryousuke Furuhashi, Yoshitaka Matsuda, Yutaka Fukui PLL frequency synthesizer with an auxiliary programmable divider. Search on Bibsonomy ISCAS (2) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
55Jaehong Ko, Wookwan Lee, Soo-Won Kim 2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF jitter, PLL, output buffer, charge-pump
55John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF adaptive bandwidth, clock multiplication, frequency synthesis, self biased, analog circuits, PLL, phase-locked loop, clock generation
54Sounil Biswas, R. D. (Shawn) Blanton Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data. Search on Bibsonomy VTS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF pass-fail test data, boolean minimization, minimum constrained subset cover, Mixed-signal test, test compaction
53Lei Yang 0019, Cherry Wakayama, C.-J. Richard Shi Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF jitter noise, PLL, phase noise, frequency synthesizer
53Charlotte Y. Lau, Michael H. Perrott Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF fractional-N, sigma, design, PLL, frequency, delta, synthesizer
53Seongwon Kim, Mani Soma, Dilip Risbud An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops. Search on Bibsonomy VTS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Defect-oriented testing, Built-In Self-Test (BIST), Design for Testability, PLL, Self-Checking Circuits
45Chin-Cheng Kuo, Pei-Syun Lin, Chien-Nan Jimmy Liu A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
45Adnan Gundel, William N. Carr Ultra Low Power CMOS PLL Clock Synthesizer for Wireless Sensor Nodes. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Baoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang 0001 A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Vijay Khawshe, Pravin V. Kumar, Renu Rangnekar, Kapil Vyas, Kashi Prabu, Mahabaleshwara, Manish Jain, Navin K. Mishra, Abhijit Abhyankar A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
45Shujin Chen, Baozhu Ma, Zhengyun Ran, Fei Guo, Huade Li A New Initial Rotor Position Detection Technology Based on HF Injection and Software PLL. Search on Bibsonomy ICICIC (1) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Xiaolue Lai, Jaijeet S. Roychowdhury TP-PPV: piecewise nonlinear, time-shifted oscillator macromodel extraction for fast, accurate PLL simulation. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Jiefeng Yan, Lei Xie, Xiaoyang Zeng, Tingao Tang Adaptive bandwidth PLL with compact current mode filter. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
45Eva Tatschl-Unterberger, Sasan Cyrusian, Michael Ruegg A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch. Search on Bibsonomy ISCAS (6) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
45Salvatore Levantino, Luca Romanò, Carlo Samori, Andrea L. Lacaita Fast-switching analog PLL with finite-impulse response. Search on Bibsonomy ISCAS (4) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
45Wen-Chi Wu, Chih-Chien Huang, Chih-Hsiung Chang, Nai-Heng Tseng Low-power CMOS PLL for clock generator. Search on Bibsonomy ISCAS (1) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
45Kasin Vichienchom, Wentai Liu Analysis of phase noise due to bang-bang phase detector in PLL-based clock and data recovery circuits. Search on Bibsonomy ISCAS (1) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
45Yi-Cheng Chang, Edwin W. Greeneich CMOS auto-ranging PLL for low-voltage wideband systems. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
45Debapriya Sahu A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
45Ian Brynjolfson, Zeljko Zilic A new PLL design for clock management applications. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
45Stephen K. Sunter, Aubin Roy Noise-Insensitive Digital BIST for any PLL or DLL. Search on Bibsonomy J. Electron. Test. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF BIST, Jitter, Design for test, PLL, Mixed-signal test, DLL
45Martin John Burbidge, Ian Andrew Grout Evolution of a Remote Access Facility for a PLL Measurement Course. Search on Bibsonomy e-Science The full citation details ... 2006 DBLP  DOI  BibTeX  RDF test, PLL, Remote laboratory
45Michael H. Perrott Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF fractional-N, sigma, PLL, frequency, delta, DLL, synthesizer
43Kandeepan Sithamparanathan, Radoslaw Piesiewicz Frequency Tracking Performance Using a Hyperbolic Digital-Phase Locked Loop for Ka-Band Communication in Rain Fading Channels. Search on Bibsonomy PSATS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Frequency tracking, digital-phase locked loops, hyperbolic phase detector, Ka-band frequency tracking
43Angel Abusleme, Boris Murmann Predictive control algorithm for phase-locked loops. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Ping-Ying Wang, Hsiu-Ming Chang 0001 A charge pump-based direct frequency modulator. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Jiri Haze, Radimir Vrba, Roman Prokop Design of Phase Locked-Loop for Very Slow Sine-Wave Signals. Search on Bibsonomy ICONS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF sine wave signal, phase locked-loop
43Tetsuro Endo, Jun Yokota Generation of White Noise by Using Chaos in Practical Phase-Locked Loop Integrated Circuit Module. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Richard Geisler, John C. Liobe, Martin Margala Process and Temperature Calibration of PLLs with BiST Capabilities. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Li Zhang 0023, Baoyong Chi, Zhihua Wang 0001, Hongyi Chen, Jinke Yao, Ende Wu A 2-GHz 6.1-mA Fully-Differential CMOS Phase-Locked Loop. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Aravind R. Nayak, John R. Barry, German S. Feyh, Steven W. McLaughlin Timing Recovery With Frequency Offset and Random Walk: Cramer-Rao Bound and a Phase-Locked Loop Postprocessor. Search on Bibsonomy IEEE Trans. Commun. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Aravind R. Nayak, John R. Barry, German S. Feyh, Steven W. McLaughlin Timing Recovery With Frequency Offset and Random Walk: Cramér-Rao Bound and a Phase- Locked Loop Postprocessor. Search on Bibsonomy IEEE Trans. Commun. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Sadeka Ali, Martin Margala A 2.4-GHz auto-calibration frequency synthesizer with on-chip built-in-self-test solution. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Tian Xia, Stephen Wyatt, Rupert Ho Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration. Search on Bibsonomy DFT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Jun Zou, Daniel Mueller 0001, Helmut E. Graeb, Ulf Schlichtmann A CPPLL hierarchical optimization methodology considering jitter, power and locking time. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF hierarchical optimization, pareto-optimal fronts
43Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop. Search on Bibsonomy ISCAS (1) The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
43Yonghui Tang, Randall L. Geiger Transient bit error rate analysis of data recovery systems using jitter models. Search on Bibsonomy ISCAS (3) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
43Youcef Fouzar, Yvon Savaria, Mohamad Sawan A new controlled gain phase-locked loop technique. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
43Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop. Search on Bibsonomy ISCAS (2) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
42Yifei Luo, Gang Chen, Kuan Zhou A picosecond TDC architecture for multiphase PLLs. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF time-to-digital converter, vdl, vernier delay line, PLL, soi, tdc
39Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur. Search on Bibsonomy ISSCC The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
35Régis Roubadia, Sami Ajram, Guy Cathébras Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Adnan Gundel, William N. Carr A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
35Arnaldo Spalvieri Optimal Loop Filter of the Discrete-time PLL in the Presence of Phase Noise. Search on Bibsonomy ISCC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Quentin Diduck, John C. Liobe, Sadeka Ali, Martin Margala Process tolerant calibration circuit for PLL applications with BIST. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Volnei A. Pedroni, Ricardo U. Pedroni PLL-less clock multiplier with self-adjusting phase symmetry. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Jens Anders, Wolfgang Mathis Simulation techniques for noise-analysis in the PLL design process. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35Omid Oliaei Synchronization and phase synthesis using PLL neural networks. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
35B. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni Application of Alpha Power Law Models to PLL Design Methodology. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
35Hung Tien Bui, Yvon Savaria 10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS. Search on Bibsonomy IWSOC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
35Ayman Mounir, Ahmed Mostafa, Maged Fikry Automatic Behavioural Model Calibration for Efficient PLL System Verification. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35Marco Cassia, Peter Shah, Erik Bruun A spur-free fractional-N ΣΔ PLL for GSM applications: linear model and simulations. Search on Bibsonomy ISCAS (1) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35Qishan Huang, Hua Xu, Jiangtao Yu, Hui Zheng Parameters Adjusting of Third-Order PLL Used in LEO Mobile Satellite Communication Systems. Search on Bibsonomy AINA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
35Yiwu Tang, Mohammed Ismail 0001, Steven Bibyk A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
35Robin R.-B. Sheen, Oscal T.-C. Chen A CMOS PLL-based frequency synthesizer for wireless communication systems at 0.9, 1.8, 1.9 and 2.4 GHz. Search on Bibsonomy ISCAS (4) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
35Yonghui Tang, Randall L. Geiger A 2.5 Gbit/s CMOS PLL for data/clock recovery without frequency divider. Search on Bibsonomy ISCAS (1) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
35Yi-Chang, Edwin W. Greeneich A current-controlled oscillator coarse-steering acquisition-aid for high frequency SOI CMOS PLL circuits. Search on Bibsonomy ISCAS (2) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
35Shigeki Obote, Yasuaki Sumi, Naoki Kitai, Yutaka Fukui, Yoshio Itoh Performance improvement in a binary phase comparator type PLL frequency synthesizer. Search on Bibsonomy ISCAS (4) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
35Yasuaki Sumi, Shigeki Obote, Naoki Kitai, Ryousuke Furuhashi, Hidekazu Ishii, Yoshitaka Matsuda, Yutaka Fukui Dead-zone-less PLL frequency synthesizer by hybrid phase detectors. Search on Bibsonomy ISCAS (4) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
34Suchitav Khadanga Synchronous programmable divider design for PLL Using 0.18 um cmos technology. Search on Bibsonomy IWSOC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF programmable divider, CMOS integrated circuits, phase locked loop, PLL, Prescaler, frequency synthesizers
33Zhongtao Fu, John Lee, Alyssa B. Apsel A 6.8GHz low-power and low-phase-noise phase-locked loop design. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
33Hari Vijay Venkatanarayanan, Michael L. Bushnell A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
33Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis. Search on Bibsonomy J. Electron. Test. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Automatic layout generation, Transient fault injection, Phase-locked loop
33Rui Fa, Bayan S. Sharif, Charalampos Tsimenidis Iterative Detection and Phase Recovery for Downlink DS and MC-CDMAFlat Rayleigh Fading Channels. Search on Bibsonomy VTC Spring The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
33Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick D. Wolf Design Methodology and CAD Tools for Prototyping Delta-Sigma Fractional-N Frequency Synthesizers. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
33Kunhyuk Kang, Keejong Kim, Kaushik Roy 0001 Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop. Search on Bibsonomy DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
33Prashant Goyal, Xiaolue Lai, Jaijeet S. Roychowdhury A fast methodology for first-time-correct design of PLLs using nonlinear phase-domain VCO macromodels. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Kuo-Hsing Cheng, Kai-Fei Chang, Yu-Lung Lo, Ching-Wen Lai, Yuh-Kuang Tseng A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study. Search on Bibsonomy IOLTS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
33Peter R. Wilson, Reuben Wilcock, Bashir M. Al-Hashimi A novel switched-current phase locked loop. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
33Chien-Hung Kuo, Yi-Shun Shih A frequency synthesizer using two different delay feedbacks. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
33S. Wanchana, T. Benjanarasuth, D. Isarakorn, J. Ngamwiwit, N. Komine Phase-locked loop process control system using LQR approach. Search on Bibsonomy ICARCV The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
33Zhenhua Wang A virtually jitter-free fractional-N divider for a Bluetooth radio. Search on Bibsonomy ISCAS (2) The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
33A. E. Hussein, Mohamed I. Elmasry Fractional-N frequency synthesizer for wireless communications. Search on Bibsonomy ISCAS (4) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
33Jinghui Lu, Bernard Grung, Stephen Anderson, Shahriar Rokhsaz Discrete z-domain analysis of high order phase locked loops. Search on Bibsonomy ISCAS (1) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
33Tom Egan, Samiha Mourad Verification of Embedded Phase-Locked Loops. Search on Bibsonomy ISQED The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
33Pascal Acco, Michael Peter Kennedy, Christian Mira, Brian Morley, Bela A. Frigyik Behavioral modeling of charge pump phase locked loops. Search on Bibsonomy ISCAS (1) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
33Woogeun Rhee Design of low-jitter 1-GHz phase-locked loops for digital clock generation. Search on Bibsonomy ISCAS (2) The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
32Jaehyun Park 0005, Donghwa Shin, Naehyuck Chang, Massoud Pedram Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF DVS overhead model, PLL, DVFS, DC-DC converter
32Ranran Yi, Bangcheng Han, Wei Sheng Design on the Driving Mode of MEMS Vibratory Gyroscope. Search on Bibsonomy ICIRA (2) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF self-oscillation, Multisim, fixed amplitude, MEMS, PLL
32Xiaolue Lai, Jaijeet S. Roychowdhury Advanced tools for simulation and design of oscillators/PLLs. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF jitter analysis, automated oscillator, macromodeling technique, amplitude macromodels, injection locking prediction, coupled oscillating systems, SPICE, PLL
32Rashed Zafar Bhatti, Monty Denneau, Jeff Draper 2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2006 DBLP  DOI  BibTeX  RDF CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection
32Maneesha Dalmia, André Ivanov, Sassan Tabatabaei Power supply current monitoring techniques for testing PLLs. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF power supply current monitoring, PLL testing, digital IC, VCO testing, analogue circuit testing, fault detection, phase locked loops, phase-locked loops, current testing, nonlinear circuits, mixed-signal ICs
32Sangho Jin, Ichiro Kimura, Keigo Watanabe Controls of servomotors for carry hospital robots. Search on Bibsonomy J. Intell. Robotic Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF Carry hospital robot, computer control, DC servomotor control, PLL control, mobile robot, PI control
26Nabil Mohammed, Weihua Zhou, Behrooz Bahrani Comparison of PLL-Based and PLL-Less Control Strategies for Grid-Following Inverters Considering Time and Frequency Domain Analysis. Search on Bibsonomy IEEE Access The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
26Elbert Bechthum, Johan Dijkhuis, Ming Ding 0003, Yuming He, Johan H. C. van den Heuvel, Paul Mateman, Gert-Jan van Schaik, Kenichi Shibata, Minyoung Song, Evgenii Tiurin, Stefano Traferro, Yao-Hong Liu, Christian Bachmann 30.6 A Low-Power BLE Transceiver with Support for Phase-Based Ranging, Featuring 5µs PLL Locking Time and 5.3ms Ranging Time, Enabled by Staircase-Chirp PLL with Sticky-Lock Channel-Switching. Search on Bibsonomy ISSCC The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
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