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Searching for phrase Dual-VDD (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
2003-2005 (18) 2006-2007 (20) 2008-2009 (15) 2010-2016 (15) 2017-2023 (6)
Publication types (Num. hits)
article(20) inproceedings(54)
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The graphs summarize 86 occurrences of 46 keywords

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Found 74 publication records. Showing 74 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
215Fei Li 0003, Yan Lin 0001, Lei He 0001, Jason Cong Low-power FPGA using pre-defined dual-Vdd/dual-Vt fabrics. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF FPGA, low power, power efficient, dual-Vdd, dual-Vt
148Yan Lin 0001, Lei He 0001 Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF programmable-Vdd, time slack, FPGA, low power
146Yan Lin 0001, Lei He 0001 Dual-Vdd Interconnect With Chip-Level Time Slack Allocation for FPGA Power Reduction. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
139Fei Li 0003, Yan Lin 0001, Lei He 0001 FPGA power reduction using configurable dual-Vdd. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF FPGA, low power, configurable, power efficient, dual-Vdd
130Harmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka A dual-VDD boosted pulsed bus technique for low power and low leakage operation. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF pulsed bus, leakage, repeaters, Dual-VDD
117Himanshu Kaul, Dennis Sylvester A novel buffer circuit for energy efficient signaling in dual-VDD systems. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF on-chip signaling, low-power, repeaters, dual-VDD
111Sarvesh H. Kulkarni, Dennis Sylvester Power distribution techniques for dual VDD circuits. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
111Yu Hu 0002, Yan Lin 0001, Lei He 0001, Tim Tuan Simultaneous time slack budgeting and retiming for dual-Vdd FPGA power reduction. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF FPGA, low power, retiming
106Kiyoo Itoh 0001 Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF 0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
104Deming Chen, Jason Cong, Fei Li 0003, Lei He 0001 Low-power technology mapping for FPGA architectures with dual supply voltages. Search on Bibsonomy FPGA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF low-power FPGA, technology mapping, dual supply voltage
103King Ho Tam, Lei He 0001 Power optimal dual-Vdd buffered tree considering buffer stations and blockages. Search on Bibsonomy DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF low power, buffer insertion, detail routing
102Yu Hu 0002, King Ho Tam, Tong Jing, Lei He 0001 Fast dual-vdd buffering based on interconnect prediction and sampling. Search on Bibsonomy SLIP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF routing, low power, interconnect, buffer insertion, dual-Vdd
95Deming Chen, Jason Cong Delay optimal low-power circuit clustering for FPGAs with dual supply voltages. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF circuit clustering, low-power FPGA, dual supply voltage
90Aswath Oruganti, Nagarajan Ranganathan Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. Search on Bibsonomy VLSI Design The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
89Fei Li 0003, Yan Lin 0001, Lei He 0001 Field Programmability of Supply Voltages for FPGA Power Reduction. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
87Rajarshi Mukherjee, Song Liu, Seda Ogrenci Memik, Somsubhra Mondal A high-level clustering algorithm targeting dual Vdd FPGAs. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF clustering, field programmable gate arrays, partitioning, placement, voltage scaling, Dynamic power
83Aman Gayasen, K. Lee, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan A Dual-VDD Low Power FPGA Architecture. Search on Bibsonomy FPL The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
82Yu Ching Chang, King Ho Tam, Lei He 0001 Power-optimal repeater insertion considering Vdd and Vth as design freedoms. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF low power, buffer insertion
81Yu Hu 0002, Yan Lin 0001, Lei He 0001, Tim Tuan Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FPGA, Low power, retiming
76Sarvesh H. Kulkarni, Ashish Srivastava, Dennis Sylvester A new algorithm for improved VDD assignment in low power dual VDD systems. Search on Bibsonomy ISLPED The full citation details ... 2004 DBLP  DOI  BibTeX  RDF ECVS, dual VDD design, low power design algorithms, CVS, level converters
76Insup Shin, Seungwhun Paik, Youngsoo Shin Register allocation for high-level synthesis using dual supply voltages. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF low power, high-level synthesis, register allocation, dual supply voltage
75Ashish Srivastava, Dennis Sylvester, David T. Blaauw Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF optimization, power dissipation, multiple voltages
73Mohammad Reza Kakoee, Ashoka Visweswara Sathanur, Antonio Pullini, Jos Huisken, Luca Benini Automatic synthesis of near-threshold circuits with fine-grained performance tunability. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF near threshold, sub-threshold performance, variability compensation, low power, ultra low power, dual VDD, sub-threshold
72Yan Lin 0001, Lei He 0001 Interactive presentation: Statistical dual-Vdd assignment for FPGA interconnect power reduction. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
69Xiaoming Chen 0003, Yu Wang 0002, Yu Cao 0001, Yuchun Ma, Huazhong Yang Variation-aware supply voltage assignment for minimizing circuit degradation and leakage. Search on Bibsonomy ISLPED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF dynamic vdd scaling, leakage power, negative bias temperature instability (NBTI), dual vdd
61Stephen Bijansky, Sae Kyu Lee, Adnan Aziz TuneLogic: Post-silicon tuning of dual-Vdd designs. Search on Bibsonomy ISQED The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
59Stephen Bijansky, Adnan Aziz TuneFPGA: post-silicon tuning of dual-Vdd FPGAs. Search on Bibsonomy DAC The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FPGA, delay, process variation, yield, tuning
59Deming Chen, Jason Cong, Junjuan Xu Optimal module and voltage assignment for low-power. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
56Sherif A. Tawfik, Volkan Kursun Dual signal frequencies and voltage levels for low power and temperature-gradient tolerant clock distribution. Search on Bibsonomy ISLPED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF dual-Vth, supply voltage scaling, temperature variations, clock skew, frequency scaling, dual-VDD
51Bruce Tseng, Hung-Ming Chen Blockage and voltage island-aware dual-vdd buffered tree construction under fixed buffer locations. Search on Bibsonomy ISPD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF voltage island architecture, low power, buffer insertion
44Shouyi Yin, Jiangyuan Gu, Dajiang Liu, Leibo Liu, Shaojun Wei Joint Modulo Scheduling and Vdd Assignment for Loop Mapping on Dual- Vdd CGRAs. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
44Bin Liu 0007, Yici Cai, Qiang Zhou 0001, Xianlong Hong Power driven placement with layout aware supply voltage assignment for voltage island generation in Dual-Vdd designs. Search on Bibsonomy ASP-DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Saihua Lin, Huazhong Yang, Rong Luo A New Family of Sequential Elements With Built-in Soft Error Tolerance for Dual-VDD Systems. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
40Mihir R. Choudhury, Quming Zhou, Kartik Mohanram Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. Search on Bibsonomy ICCAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
40Jinn-Shyan Wang, Yu-Juey Chang, Chingwei Yeh, Yuan-Hua Chu Design of STR level converters for SoCs using the multi-island dual-VDD design technique. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
34Sherif A. Tawfik, Volkan Kursun Low-Power Low-Voltage Hot-Spot Tolerant Clocking with Suppressed Skew. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
34Sherif A. Tawfik, Volkan Kursun Dual-V_DD Clock Distribution for Low Power and Minimum Temperature Fluctuations Induced Skew. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
32Yan Lin 0001, Fei Li 0003, Lei He 0001 Power modeling and architecture evaluation for FPGA with novel circuits for Vdd programmability. Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF FPGA power model, Vdd programmability, low power, FPGA architecture, dual-Vdd
30Somsubhra Mondal, Seda Ogrenci Memik Power Optimization Techniques for SRAM-Based FPGAs. Search on Bibsonomy FPL The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
30Kazuei Hironaka, Hideharu Amano Power Centric Application Mapping for Dynamically Reconfigurable Processor Array with Dual Vdd and Dual Vth. Search on Bibsonomy ReConFig The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
30Kun-Lin Tsai, Szu-Wei Chaung, Feipei Lai, Shanq-Jang Ruan A low power scheduling method using dual Vdd and dual Vth. Search on Bibsonomy ISCAS (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
30Yuvraj Singh Dhillon, Abdulkadir Utku Diril, Abhijit Chatterjee, Adit D. Singh Low-power dual Vth pseudo dual Vdd domino circuits. Search on Bibsonomy SBCCI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF NMOS pull-up, low power, domino logic, dual supply voltages, dual threshold voltages
25Bo Liu 0019, Anfeng Xue, Ziyu Wang, Na Xie, Xuetao Wang, Zhen Wang 0019, Hao Cai A Reconfigurable Approximate Computing Architecture With Dual-VDD for Low-Power Binarized Weight Network Deployment. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
25Abhay S. Vidhyadharan, Kasthuri Bha, Sanjay Vidhyadharan CNFET-Based Ultra-Low-Power Dual-VDD Ternary Half Adder. Search on Bibsonomy Circuits Syst. Signal Process. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
25Abhay S. Vidhyadharan, Sanjay Vidhyadharan An ultra-low-power CNFET based dual VDD ternary dynamic Half Adder. Search on Bibsonomy Microelectron. J. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
25Ching-Hwa Cheng, Tang-Chieh Liu Digitalized-Management Voltage-Domain Programmable Mechanisms for Dual-Vdd Low-Power Embedded Digital Systems. Search on Bibsonomy DDECS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
25François Stas, David Bol Integration of level shifting in a TSPC flip-flop for low-power robust timing closure in dual-Vdd ULV circuits. Search on Bibsonomy ISCAS The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
25Kaijian Yuan, Xingming Zhang 0002 Low power mapping optimization of loops for dual-Vdd CGRAs. Search on Bibsonomy ASICON The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
25Ming Chen, Po-Tsang Huang, Shang-Lin Wu, Wei Hwang, Ching-Te Chuang Area-power-efficient 11-bit hybrid dual-Vdd ADC with self-calibration for neural sensing application. Search on Bibsonomy SoCC The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
25Hua Xiang 0001, Lakshmi N. Reddy, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu Gate movement for timing improvement on row based Dual-VDD designs. Search on Bibsonomy ISQED The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
25Bing Xu, Shouyi Yin, Leibo Liu, Shaojun Wei Low-Power Loop Parallelization onto CGRA Utilizing Variable Dual VDD. Search on Bibsonomy IEICE Trans. Inf. Syst. The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
25Bing Xu, Shouyi Yin, Leibo Liu, Shaojun Wei Low-power loop pipelining mapping onto CGRA utilizing variable dual VDD. Search on Bibsonomy MWSCAS The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
25Hua Xiang 0001, Haifeng Qian, Ching Zhou, Yu-Shiang Lin, Fanchieh Yee, Andrew Sullivan, Pong-Fei Lu Row Based Dual-VDD Island Generation and Placement. Search on Bibsonomy DAC The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
25 Row-Based Dual Vdd Assignment, for a Level Converter Free CSA Design and Its Near-Threshold Operation. Search on Bibsonomy CoRR The full citation details ... 2013 DBLP  BibTeX  RDF
25Jianfeng Zhu 0001, Leibo Liu, Shouyi Yin, Shaojun Wei Low-Power Reconfigurable Processor Utilizing Variable Dual VDD. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
25Insup Shin, Seungwhun Paik, Dongwan Shin, Youngsoo Shin HLS-dv: A High-Level Synthesis Framework for Dual-Vdd Architectures. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
25Haiqi Wang, Sheqin Dong, Tao Lin, Song Chen 0001, Satoshi Goto Novel Voltage Choice and Min-Cut Based Assignment for Dual-VDD System. Search on Bibsonomy IEICE Trans. Fundam. Electron. Commun. Comput. Sci. The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
25Jianfeng Zhu 0001, Dong Wu, Yaru Yan, Xiao Yu, Hu He 0001, Liyang Pan A chip-level path-delay-distribution based Dual-VDD method for low power FPGA (abstract only). Search on Bibsonomy FPGA The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
25Qing Gao, Orly Yadid-Pecht Dual VDD block based CMOS image sensor - preliminary evaluation. Search on Bibsonomy ISCAS The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
25Joseph F. Ryan 0002, Benton H. Calhoun A sub-threshold FPGA with low-swing dual-VDD interconnect in 90nm CMOS. Search on Bibsonomy CICC The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
25Thomas Schweizer, Julio A. de Oliveira Filho, Tommy Kuhn, Wolfgang Rosenstiel Low Energy Voltage Dithering in Dual VDD Circuits. Search on Bibsonomy PATMOS The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
25Prasanth Mangalagiri, Vijaykrishnan Narayanan Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs. Search on Bibsonomy ISVLSI The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
25King Ho Tam, Yu Hu 0002, Lei He 0001, Tom Tong Jing, Xinyi Zhang Dual-Vdd Buffer Insertion for Power Reduction. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
25Yici Cai, Bin Liu 0007, Qiang Zhou 0001, Xianlong Hong Voltage Island Generation in Cell Based Dual-Vdd Design. Search on Bibsonomy IEICE Trans. Fundam. Electron. Commun. Comput. Sci. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
25Yasuhiro Morita, Hidehiro Fujiwara, Hiroki Noguchi, Yusuke Iguchi, Koji Nii, Hiroshi Kawaguchi 0001, Masahiko Yoshimoto Area Comparison between 6T and 8T SRAM Cells in Dual-Vdd Scheme and DVS Scheme. Search on Bibsonomy IEICE Trans. Fundam. Electron. Commun. Comput. Sci. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
25Sarvesh H. Kulkarni, Dennis Sylvester Power Distribution Techniques for Dual VDD Circuits. Search on Bibsonomy J. Low Power Electron. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
25Yan Lin 0001, Yu Hu 0002, Lei He 0001, Vijay Raghunat An efficient chip-level time slack allocation algorithm for Dual-Vdd FPGA power reduction. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF time slack, FPGA, low power
25Rajarshi Mukherjee, Seda Ogrenci Memik Evaluation of dual VDD fabrics for low power FPGAs. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
25Sarvesh H. Kulkarni, Dennis Sylvester High performance level conversion for dual VDD design. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
25Robert Bai, Dennis Sylvester Analysis and design of level-converting flip-flops for dual-Vdd/Vth integrated circuits. Search on Bibsonomy SoC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
19Behnam Ghavami, Mehrshad Khosraviani, Hossein Pedram Power Optimization of Asynchronous Circuits through Simultaneous Vdd and Vth Assignment and Template Sizing. Search on Bibsonomy DSD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
15Prateek Mishra, Anish Muttreja, Niraj K. Jha Low-power FinFET circuit synthesis using multiple supply and threshold voltages. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Low-power, linear programming, synthesis, TCMS
15Anish Muttreja, Prateek Mishra, Niraj K. Jha Threshold Voltage Control through Multiple Supply Voltages for Power-Efficient FinFET Interconnects. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
15Liangpeng Guo, Yici Cai, Qiang Zhou 0001, Xianlong Hong Logic and Layout Aware Voltage Island Generation for Low Power Design. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
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