Search results for "Floating-Point"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
170	Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even	Pipelined Packet-Forwarding Floating Point: II. An Adder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, floating point addition algorithm, adder pipeline design, packet forwarding pipeline paradigm, data hazards, deeply pipelined floating point pipelines, four stage execution phase pipeline, short clock period, fifteen logic levels, addition algorithm, standard binary floating point format, standard IEEE 754 rounded result, two cycle latency, cooperating multiplier pipeline, packet forwarding operand, IEEE 754 binary floating point compatibility, pipeline arithmetic
146	David W. Matula, Asger Munk Nielsen	Pipelined Packet-Forwarding Floating Point: I. Foundations and a Rounder.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	pipelined packet forwarding floating point, packet forwarding floating point format, rounder design, packet forwarding format, standard binary IEEE 754 floating point format, multiplication algorithms, ALU pipeline paradigm, data hazards, pipelined floating point operations, execution phases, multiplier packet forwarding pipelines, execution phase, logic levels, multiplier pipelines, forwarding pipelines, IEEE 754 binary floating point compatibility, pipeline arithmetic, data dependent operations
122	Asger Munk Nielsen, David W. Matula, Chung Nan Lyu, Guy Even	An IEEE Compliant Floating-Point Adder that Conforms with the Pipelined Packet-Forwarding Paradigm.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	IEEE floating-point rounding, Floating-point arithmetic, redundant number representations, floating-point addition
117	Brigitte Verdonk, Annie A. M. Cuyt, Dennis Verschaeren	A precision- and range-independent tool for testing floating-point arithmetic II: conversions.	ACM Trans. Math. Softw.	2001	DBLP DOI BibTeX RDF	IEEE floating-point standard, multiprecision, validation, conversion, floating-point, arithmetic, decimal
105	Lance Saldanha, Roman L. Lysecky	Hardware/software partitioning of floating point software applications to fixed-pointed coprocessor circuits.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	floating point to fixed conversion, floating point, fixed point, hardware/software partitioning
98	Guy Even, Wolfgang J. Paul	On the Design of IEEE Compliant Floating Point Units.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	floating-point rounding, floating-point arithmetic, IEEE 754 Standard, floating-point addition
98	Geoff Barrett	Formal Methods Applied to a Floating-Point Number System.	IEEE Trans. Software Eng.	1989	DBLP DOI BibTeX RDF	floating-point number system, binary floating-point arithmetic, ANSI/IEEE Std. 754-1985, set-theoretic specification language, sequential components, unpack, operands, proven rules, mathematically rigorous method, Inmos IMS T800 transputer, formal specification, formal methods, specification languages, digital arithmetic, Z, formalization, round, pack, program development, IEEE standard, floating-point unit, internal representations
97	Yirng-An Chen, Randal E. Bryant	PHDD: an efficient graph representation for floating point circuit verification.	ICCAD	1997	DBLP DOI BibTeX RDF	KFDD, BMD, HDD, KBMD, Verification, Formal Verifications, BDD, Floating Point, FDD, BMD
91	Zhanpeng Jin, Richard Neil Pittman, Alessandro Forin	Reconfigurable custom floating-point instructions (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	emips, reconfigurable, extension, floating-point, partial reconfiguration
91	Hiromichi Yamada, Takashi Hotta, Takahiro Nishiyama, Fumio Murabayashi, Tatsumi Yamauchi, Hideo Sawamoto	A 13.3ns double-precision floating-point ALU and multiplier.	ICCD	1995	DBLP DOI BibTeX RDF	double-precision floating-point ALU, floating-point multiplier, carry select addition, prerounding techniques, noise tolerant precharge circuit, two-cycle latency, 13.3 ns, 0.3 micron, 2.5 V, 150 MHz, normalization, floating point arithmetic, CMOS integrated circuits, multiplying circuits, CMOS technology, arithmetic logic unit
86	Brigitte Verdonk, Annie A. M. Cuyt, Dennis Verschaeren	A precision- and range-independent tool for testing floating-point arithmetric I: basic operations, square root, and remainder.	ACM Trans. Math. Softw.	2001	DBLP DOI BibTeX RDF	IEEE floating-point standard, multiprecision, validation, floating-point, arithmetic
86	Kevin P. Acken, Mary Jane Irwin, Robert Michael Owens, Amulya K. Garga	Architectural Optimizations For A Floating Point Multiply-Accumulate Unit In A Graphics Pipeline.	ASAP	1996	DBLP DOI BibTeX RDF	floating point multiply-accumulate unit, three-dimensional graphics engines, normalized space, virtual reality, virtual reality, parallelism, computer graphics, scientific visualization, matrix multiplication, matrix multiplications, data visualisation, floating point arithmetic, architectural optimizations, graphics pipeline
85	Liang-Kai Wang, Michael J. Schulte	Decimal Floating-Point Adder and Multifunction Unit with Injection-Based Rounding.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
83	Hosahalli R. Srinivas, Keshab K. Parhi	A floating point radix 2 shared division/square root chip.	ICCD	1995	DBLP DOI BibTeX RDF	floating point radix 2 shared division/square root chip, full-custom 1.2 micron CMOS VLSI chip, single precision IEEE 754 std. floating point numbers, square root algorithm, digit-by-digit schemes, quotient/root digit selection, 5.0 V, 66 MHz, VLSI, floating point arithmetic, CMOS integrated circuits, IEEE standards, dividing circuits, 1.2 micron, division algorithm
81	Yee Jern Chong, Sri Parameswaran	Flexible multi-mode embedded floating-point unit for field programmable gate arrays.	FPGA	2009	DBLP DOI BibTeX RDF	dual-precision, embedded block, fpu, fpga, floating-point, fpga architecture
81	Mikio Takeuchi, Hideaki Komatsu, Toshio Nakatani	A new speculation technique to optimize floating-point performance while preserving bit-by-bit reproducibility.	ICS	2003	DBLP DOI BibTeX RDF	bit-by-bit reproducibility, floating-point speculation, fused multiply-add, reassociation, striding, Java, prefetching, accuracy, instruction-level parallelism, software pipelining, just-in-time compiler, loop unrolling, privatization, IA-64, IEEE 754
81	Ahmet Akkas	A Combined Interval and Floating-Point Comparator/Selector.	ASAP	2002	DBLP DOI BibTeX RDF	VLSI design, Interval arithmetic, floating-point arithmetic, comparator, specialized hardware, selector
80	Guenter Gerwig, Holger Wetter, Eric M. Schwarz, Juergen Haess	High Performance Floating-Point Unit with 116 Bit Wide Divider.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
78	Corporate Floating Point Systems	T series hypercube.	C³P	1988	DBLP DOI BibTeX RDF
78	J. Dido, N. Géraudie, L. Loiseau, O. Payeur, Yvon Savaria, D. Poirier	A flexible floating-point format for optimizing data-paths and operators in FPGA based DSPs.	FPGA	2002	DBLP DOI BibTeX RDF	data-path optimization, floating-point/fixed-point conversion, hardware division, hyardware optimization, FPGA, floating-point, video-processing
77	Marius Cornea, John Harrison 0001, Cristina Anderson, Ping Tak Peter Tang, Eric Schneider, Evgeny Gvozdev	A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
77	Xiaojun Wang, Sherman Braganza, Miriam Leeser	Advanced Components in the Variable Precision Floating-Point Library.	FCCM	2006	DBLP DOI BibTeX RDF
76	Michael J. Flynn, Kevin J. Nowka, Gary Bewick, Eric M. Schwarz, Nhon T. Quach	The SNAP Project: Towards Sub-Nanosecond Arithmetic.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	floating-point multiplication, computer arithmetic, floating-point arithmetic, wave pipelining, floating-point addition
75	S. Subramanya Sastry, Subbarao Palacharla, James E. Smith 0001	Exploiting Idle Floating-Point Resources for Integer Execution.	PLDI	1998	DBLP DOI BibTeX RDF
74	Florent de Dinechin, Jérémie Detrey, Octavian Cret, Radu Tudoran	When FPGAs are better at floating-point than microprocessors.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, floating-point, arithmetic
72	Brian J. Hickmann, Andrew Krioukov, Michael J. Schulte, Mark A. Erle	A parallel IEEE P754 decimal floating-point multiplier.	ICCD	2007	DBLP DOI BibTeX RDF
71	Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert	Architectural Modifications to Enhance the Floating-Point Performance of FPGAs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
70	Guy Even, Wolfgang J. Paul	On the Design of IEEE Compliant Floating Point Units.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	floating point arithmetic, rounding, floating point unit
70	H. Dhanesha, K. Falakshahi, Mark Horowitz	Array-of-arrays architecture for parallel floating point multiplication.	ARVLSI	1995	DBLP DOI BibTeX RDF	array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron
69	Eric Quinnell, Earl E. Swartzlander Jr., Carl Lemonds	Bridge Floating-Point Fused Multiply-Add Design.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
69	Ronald Scrofano, Ling Zhuo, Viktor K. Prasanna	Area-Efficient Arithmetic Expression Evaluation Using Deeply Pipelined Floating-Point Cores.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
69	Marius Cornea, Cristina Anderson, John Harrison 0001, Ping Tak Peter Tang, Eric Schneider, Charles Tsen	A Software Implementation of the IEEE 754R Decimal Floating-Point Arithmetic Using the Binary Encoding Format.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
69	Gongqiong Li, Zhaolin Li	Optimized design of a double-precision floating-point multiply-add-dused unit for data dependence.	ICCD	2007	DBLP DOI BibTeX RDF
69	Jian Liang, Russell Tessier, Oskar Mencer	Floating Point Unit Generation and Evaluation for FPGAs.	FCCM	2003	DBLP DOI BibTeX RDF
68	Javier D. Bruguera, Tomás Lang	Floating-Point Fused Multiply-Add: Reduced Latency for Floating-Point Addition.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
66	Bowei Zhang, Guochang Gu, Lin Sun, Yanxia Wu	32-bit floating-point FPGA gaussian elimination.	FPGA	2009	DBLP DOI BibTeX RDF	fpga., floating-point, gaussian elimination
66	Diego F. Sánchez, Daniel M. Muñoz, Carlos H. Llanos, Mauricio Ayala-Rincón	Parameterizable floating-point library for arithmetic operations in FPGAs.	SBCCI	2009	DBLP DOI BibTeX RDF	goldschmidt, FPGA, computer arithmetic, floating-point
66	Yee Jern Chong, Sri Parameswaran	Rapid application specific floating-point unit generation with bit-alignment.	DAC	2008	DBLP DOI BibTeX RDF	bit-alignment, datapath merging, floating-point
66	Liang-Kai Wang, Michael J. Schulte	A Decimal Floating-Point Divider Using Newton-Raphson Iteration.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	Newton-Raphson iteration, initial approximation, computer arithmetic, floating-point, division, hardware design, decimal
66	Andrew Beaumont-Smith, Neil Burgess, S. Lefrere, Cheng-Chew Lim	Reduced Latency IEEE Floating-Point Standard Adder Architectures.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF	VLSI, floating-point, adder, arithmetic
63	Kingshuk Karuri, Rainer Leupers, Gerd Ascheid, Heinrich Meyr, Monu Kedia	Design and implementation of a modular and portable IEEE 754 compliant floating-point unit.	DATE Designers' Forum	2006	DBLP DOI BibTeX RDF
63	Guy Even, Peter-Michael Seidel	A Comparison of Three Rounding Algorithms for IEEE Floating-Point Multiplication.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	floating-point multiplication, IEEE rounding, Floating-point arithmetic, IEEE 754 Standard
61	Nachiket Kapre, André DeHon	Optimistic Parallelization of Floating-Point Accumulation.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
61	Bryan Catanzaro, Brent E. Nelson	Higher Radix Floating-Point Representations for FPGA-Based Arithmetic.	FCCM	2005	DBLP DOI BibTeX RDF
61	Avi Ziv, Merav Aharoni, Sigal Asaf	Solving Range Constraints for Binary Floating-Point Instructions.	IEEE Symposium on Computer Arithmetic	2003	DBLP DOI BibTeX RDF
59	Yongkang Zhu, Jun-Hai Yong, Guo-Qin Zheng	Line Segment Intersection Testing.	Computing	2005	DBLP DOI BibTeX RDF	Intersection testing for line segments, dot product summation, floating-point arithmetic, rounding error
59	Yongkang Zhu, Jun-Hai Yong, Guo-Qin Zheng	Computing the Sign of a Dot Product Sum.	CIS	2004	DBLP DOI BibTeX RDF	Floating-point arithmetic, Interval analysis, Rounding error
58	Sanghamitra Roy, Prithviraj Banerjee	An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design.	DAC	2004	DBLP DOI BibTeX RDF	quantization, quantizer, floating point, fixed point
58	Enyi Tang, Earl T. Barr, Xuandong Li, Zhendong Su 0001	Perturbing numerical calculations for statistical analysis of floating-point program (in)stability.	ISSTA	2010	DBLP DOI BibTeX RDF	testing, stability, floating-point, perturbation, numerical code
58	Mustafa Gök, Metin Mete Özbilen	Evaluation of Sticky-Bit Generation Methods for Floating-Point Multipliers.	J. Signal Process. Syst.	2009	DBLP DOI BibTeX RDF	Floating-point multiplier, Sticky-bit, Rounding
58	David Monniaux	The pitfalls of verifying floating-point computations.	ACM Trans. Program. Lang. Syst.	2008	DBLP DOI BibTeX RDF	AMD64, FPU, IA32, x87, Verification, Static analysis, Abstract interpretation, Program testing, Embedded software, Floating point, Safety-Critical Software, Rounding, PowerPC, IEEE-754
58	Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert	Embedded floating-point units in FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	FPU, FPGA, floating-point, FPGA architecture
58	K. Scott Hemmert, Keith D. Underwood	Open Source High Performance Floating-Point Modules.	FCCM	2006	DBLP DOI BibTeX RDF	IEEE floating point, FPGA, reconfigurable computing
58	Xu Zhou, Zhimin Tang	A New Architecture of a Fast Floating-Point Multiplier.	APPT	2003	DBLP DOI BibTeX RDF	Floating-point Multiplier, Processor
58	Keith O. Geddes, Wei Wei Zheng	Exploiting fast hardware floating point in high precision computation.	ISSAC	2003	DBLP DOI BibTeX RDF	arbitrary precision, floating point, least squares, nonlinear systems, linear systems, iterative refinement, multiple precision
58	R. V. K. Pillai, Dhamin Al-Khalili, Asim J. Al-Khalili, S. Y. A. Shah	A Low Power Approach to Floating Point Adder Design for DSP Applications.	J. VLSI Signal Process.	2001	DBLP DOI BibTeX RDF	digital-CMOS, power-consumption-model, VLSI, low-power-design, computer-arithmetic, floating-point, switching-activity
58	R. V. K. Pillai, Asim J. Al-Khalili, Dhamin Al-Khalili	A Low Power Floating Point Accumulator.	VLSI Design	1998	DBLP DOI BibTeX RDF	low power CMOS, Digital arithmetic, VLSI architecture, floating point
56	Daniel Ménard, Daniel Chillet, François Charot, Olivier Sentieys	Automatic floating-point to fixed-point conversion for DSP code generation.	CASES	2002	DBLP DOI BibTeX RDF	digital signal processing systems, floating-point to fixed-point conversion, quantization noise, code generation, DSP, fixed-point
55	Jason Lee, Lesley Shannon, Matthew J. Yedlin, Gary F. Margrave	A multi-FPGA application-specific architecture for accelerating a floating point Fourier Integral Operator.	ASAP	2008	DBLP DOI BibTeX RDF
55	Fernando E. Ortiz, John R. Humphrey, James P. Durbano, Dennis W. Prather	A Study on the Design of Floating-Point Functions in FPGAs.	FPL	2003	DBLP DOI BibTeX RDF
55	Gerd Bohlender	Floating-Point Computation of Functions with Maximum Accuracy.	IEEE Trans. Computers	1977	DBLP DOI BibTeX RDF	multiple-length mantissas, roots of floating-point numbers, Accuracy, errors, rounding, floating-point computations
54	Yong Dou, Yuanwu Lei, Guiming Wu, Song Guo 0003, Jie Zhou 0007, Li Shen	FPGA accelerating double/quad-double high precision floating-point applications for ExaScale computing.	ICS	2010	DBLP DOI BibTeX RDF	double-double precision, high precision floating-point multiplication and accumulation (HP-MAC), quad-double precision, FPGA
53	Dimitri Tan, Carl Lemonds, Michael J. Schulte	Low-Power Multiple-Precision Iterative Floating-Point Multiplier with SIMD Support.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
53	Charles Tsen, Sonia González-Navarro, Michael J. Schulte, Brian J. Hickmann, Katherine Compton	A Combined Decimal and Binary Floating-Point Multiplier.	ASAP	2009	DBLP DOI BibTeX RDF
53	Ivan D. Castellanos, James E. Stine	A 64-bit Decimal Floating-Point Comparator.	ASAP	2006	DBLP DOI BibTeX RDF
53	Ali Malik, Seok-Bum Ko	A Study on the Floating-Point Adder in FPGAS.	CCECE	2006	DBLP DOI BibTeX RDF
53	John D. Thompson, Nandini Karra, Michael J. Schulte	A 64-bit Decimal Floating-Point Adder.	ISVLSI	2004	DBLP DOI BibTeX RDF
53	Woo-Chan Park, Tack-Don Han, Sung-Bong Yang	A Floating Point Divider Performing IEEE Rounding and Quotient Conversion in Parallel.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
53	Eric Roesler, Brent E. Nelson	Novel Optimizations for Hardware Floating-Point Units in a Modern FPGA Architecture.	FPL	2002	DBLP DOI BibTeX RDF
53	Chun Hok Ho, Monk-Ping Leong, Philip Heng Wai Leong, Jürgen Becker 0001, Manfred Glesner	Rapid Prototyping of FPGA Based Floating Point DSP Systems.	IEEE International Workshop on Rapid System Prototyping	2002	DBLP DOI BibTeX RDF
53	Zaher Abdulkarim Baidas, Andrew D. Brown, Alan Christopher Williams	Floating-point behavioral synthesis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
53	Cheol-Ho Jeong, Woo-Chan Park, Tack-Don Han, Moon Key Lee, Sang-Woo Kim	In-Order Issue Out-of-Order Execution Floating-Point Coprocessor for CalmRISC32.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
53	Shiro Kobayashi, Gerhard P. Fettweis	A Hierarchical Block-Floating-Point Arithmetic.	J. VLSI Signal Process.	2000	DBLP DOI BibTeX RDF
53	Eric M. Schwarz, Ronald M. Smith, Christopher A. Krygowski	The S/390 G5 Floating Point Unit Supporting Hex and Binary Architectures.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
53	Marius A. Cornea-Hasegan, Roger A. Golliver, Peter W. Markstein	Correctness Proofs Outline for Newton-Raphson Based Floating-Point Divide and Square Root Algorithms.	IEEE Symposium on Computer Arithmetic	1999	DBLP DOI BibTeX RDF
53	Gerben J. Hekstra, Ed F. Deprettere	Floating point Cordic.	IEEE Symposium on Computer Arithmetic	1993	DBLP DOI BibTeX RDF
51	Ling Zhuo, Viktor K. Prasanna	Sparse Matrix-Vector multiplication on FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, reconfigurable architecture, high performance, floating-point, sparse matrix
51	Zizhong Chen, Graham E. Fagg, Edgar Gabriel, Julien Langou, Thara Angskun, George Bosilca, Jack J. Dongarra	Fault tolerant high performance computing by a coding approach.	PPoPP	2005	DBLP DOI BibTeX RDF	floating-point arithmetic coding, fault tolerance, message passing interface, high performance computing
51	Chun Te Ewe, Peter Y. K. Cheung, George A. Constantinides	Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation.	FPL	2004	DBLP DOI BibTeX RDF
50	Florian Loitsch	Printing floating-point numbers quickly and accurately with integers.	PLDI	2010	DBLP DOI BibTeX RDF	dtoa, floating-point printing
50	Jérémie Detrey, Florent de Dinechin, Xavier Pujol	Return of the hardware floating-point elementary function.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF	Floating-point elementary functions, hardware operator, FPGA, exponential, logarithm
50	Julio Villalba, Tomás Lang, Mario A. González	Double-Residue Modular Range Reduction for Floating-Point Hardware Implementations.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Range-reduction, elementary function evaluation, floating-point arithmetic
50	Ahmet Akkas	Dual-Mode Quadruple Precision Floating-Point Adder.	DSD	2006	DBLP DOI BibTeX RDF	Quadruple precision, dualmode, computer arithmetic, floating-point, adder, double precision
50	Anuja Jayraj Thakkar, Abdel Ejnioui	Pipelining of double precision floating point division and square root operations.	ACM Southeast Regional Conference	2006	DBLP DOI BibTeX RDF	FPGA, pipelining, floating point, division, square root
50	K. Scott Hemmert, Keith D. Underwood	An Analysis of the Double-Precision Floating-Point FFT on FPGAs.	FCCM	2005	DBLP DOI BibTeX RDF	IEEE floating point, FPGA, FFT, Fast Fourier Transform, reconfigurable computing
50	Keith D. Underwood, K. Scott Hemmert	Closing the Gap: CPU and FPGA Trends in Sustainable Floating-Point BLAS Performance.	FCCM	2004	DBLP DOI BibTeX RDF	IEEE floating point, re-configurable computing, FPGA, arithmetic
50	Tay-Jyi Lin, Hung-Yueh Lin, Chie-Min Chao, Chih-Wei Liu, Chein-Wei Jen	A compact DSP core with static floating-point unit & its microcode generation.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	DSP core, digital signal processor, floating-point units
50	Álvaro Vázquez, Elisardo Antelo	Implementation of the Exponential Function in a Floating-Point Unit.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	exponential function, computer arithmetic, floating-point unit, transcendental functions
50	Ahmet Akkas, Michael J. Schulte	A Quadruple Precision and Dual Double Precision Floating-Point Multiplier.	DSD	2003	DBLP DOI BibTeX RDF	Quadruple precision, computer arithmetic, normalization, floating-point, multiplier, rounding, double precision
50	Henrik Koy, Claus-Peter Schnorr	Segment LLL-Reduction with Floating Point Orthogonalization.	CaLC	2001	DBLP DOI BibTeX RDF	LLL-reduction, Householder reflexion, scaled basis, segment LLL-reduction, local LLL-reduction, stability, floating point arithmetic
50	James E. Stine, Michael J. Schulte	A Combined Interval and Floating Point Multiplier.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	computer arithmetic, accuracy, multiplication, floating point, hardware design, rounding, Interval, double precision
50	Stuart F. Oberman, Hesham A. Al-Twaijry, Michael J. Flynn	The SNAP Project: Design of Floating Point Arithmetic Unit.	IEEE Symposium on Computer Arithmetic	1997	DBLP DOI BibTeX RDF	performance-area tradeoffs, computer arithmetic, multiplication, division, Addition, floating point unit
50	John R. Hauser	Handling Floating-Point Exceptions in Numeric Programs.	ACM Trans. Program. Lang. Syst.	1996	DBLP DOI BibTeX RDF	exception handling, floating-point, arithmetic
50	Robert G. Burger, R. Kent Dybvig	Printing Floating-Point Numbers Quickly and Accurately.	PLDI	1996	DBLP DOI BibTeX RDF	floating-point printing, run-time systems
50	Mark D. Aagaard, Carl-Johan H. Seger	The formal verification of a pipelined double-precision IEEE floating-point multiplier.	ICCAD	1995	DBLP DOI BibTeX RDF	ANSI/IEEE Std 754-1985, model checking, theorem proving, floating-point arithmetic, Hardware verification
50	René de Vogelaere	Algorithms: Algorithm 335: a set of basic input-output procedures.	Commun. ACM	1968	DBLP DOI BibTeX RDF	ALGOL 60, Berkeley style, decompose integer, decompose real, equivalent ALGOL statements, fixed point representation, input echo, input outpur array, input output Boolean, input output procedures, integer format, out integer, output channel interpretation, output documentation, procedures relationship, quality output, read real, real format, ALGOL, style, transput, input output, floating point representation, floating point representational
49	Pavle Belanovic, Miriam Leeser	A Library of Parameterized Floating-Point Modules and Their Use.	FPL	2002	DBLP DOI BibTeX RDF
48	Sanghamitra Roy, Prith Banerjee	An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	field programmable gate arrays, Automation, quantization, floating-point arithmetic, fixed-point arithmetic
48	Jean-Claude Bajard, Laurent-Stéphane Didier, Jean-Michel Muller	A New Euclidean Division Algorithm For Residue Number Systems.	ASAP	1996	DBLP DOI BibTeX RDF	Euclidean division algorithm, large moduli, very large integers, high-radix division method, parallel computer, computational geometry, digital arithmetic, residue number systems, residue number systems, floating point arithmetic, floating-point arithmetic, modular arithmetic, special-purpose architecture
48	A. Houelle, Habib Mehrez, Nicolas Vaucher, Luis A. Montalvo, Alain Guyot	Application of fast layout synthesis environment to dividers evaluation.	IEEE Symposium on Computer Arithmetic	1995	DBLP DOI BibTeX RDF	layout synthesis environment, dividers evaluation, GenOptim, IEEE 754 floating-point macro-cell generators, programming environments, generator programs, division, floating point arithmetic, square root, dividing circuits