Search results for "HSPICE"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
66	Fengming Zhang, Rui Tang, Yong-Bin Kim	SET-based nano-circuit simulation and design method using HSPICE.	ACM Great Lakes Symposium on VLSI	2004	DBLP DOI BibTeX RDF	SET circuit design, SET modeling, SET simulation with HSPICE
45	Jie Deng, Albert Lin, Gordon C. Wan, H.-S. Philip Wong	Carbon nanotube transistor compact model for circuit design and performance optimization.	ACM J. Emerg. Technol. Comput. Syst.	2008	DBLP DOI BibTeX RDF	VerilogA, carbon nanotube FET, compact model, CNT, HSPICE
41	Asim Salim, Tajinder Manku, Arokia Nathan	Modeling of magnetic field sensitivity of bipolar magnetotransistors using HSPICE.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
40	Yarallah Koolivand, Omid Shoaei, Ali Fotowat-Ahmady, Ali Zahabi, Parviz Jabedar Maralani	Nonlinearity Analysis in ISD CMOS LNA's Using Volterra Series.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	CMOS LNA, cascode, inductively source degenerated (ISD), intermodulation (IM), second order interception point (IIP2), third order interception point (IIP3), volterra kernels, volterra series, linearity, distortion
35	Hideaki Kimura 0002, Norihito Iyenaga	A Unified Technique for PCB/MCM Design by Combining Electromagnetic Field Analysis with Circuit Simulator.	DATE	1998	DBLP DOI BibTeX RDF	small signal operation, large signaloperation, Simulator, MCM, FDTD, PCB, HSPICE
35	Charles E. Molnar, Ian W. Jones, William S. Coates, Jon K. Lexau	A FIFO Ring Performance Experiment.	ASYNC	1997	DBLP DOI BibTeX RDF	FIFO ring performance experiment, high-speed FIFO circuit, asynchronous FIFO, clocked shift register, pulse-like protocol, two-phase clocked design, MOSIS, internal FIFO stages, 3.3 V, 1.67 to 4.8 V, 0.6 micron, pipeline, SPICE, data path, hSpice, circuit delays
35	Haluk Konuk, F. Joel Ferguson	An unexpected factor in testing for CMOS opens: the die surface.	VTS	1996	DBLP DOI BibTeX RDF	surface phenomena, electric charge, CMOS opens, die surface, RC interconnect, HSPICE simulations, trapped charge, floating gates, VLSI, integrated circuit testing, CMOS integrated circuits, integrated circuit modelling, circuit model
35	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
35	Chung-Len Lee, Horng Nan Chern, Min Shung Liao, Hui Min Wang	On Designing of 4-Valued Memory with Double-Gate TFT.	ISMVL	1995	DBLP DOI BibTeX RDF	thin film transistors, 4-valued memory, double-gate TFT, 4 valued memory cell, double gate thin film transistor, double gate TFT, HSPICE simulation, resistor load, CMOS load basic block circuit, memory cell circuits, SRAM cell circuit, memory architecture, integrated circuit design, multivalued logic, SPICE, circuit design, multivalued logic circuits, SRAM chips, CMOS memory circuits, equivalent circuits, equivalent circuit
35	H. Dhanesha, K. Falakshahi, Mark Horowitz	Array-of-arrays architecture for parallel floating point multiplication.	ARVLSI	1995	DBLP DOI BibTeX RDF	array-of-arrays architecture, parallel floating point multiplication, mantissa path, IEEE standard 754, dual-rail domino, HSpice simulation, capacitive load model, 53 bit, 10 ns, 4.3 V, 120 C, parallel architectures, trees, latency, floating point arithmetic, multiplying circuits, CMOS technology, Verilog, synergy, 1 micron
35	Samy Makar, Edward J. McCluskey	Checking experiments to test latches.	VTS	1995	DBLP DOI BibTeX RDF	exhaustive functional tests, 2-state latches, minimum-length checking, D-latch, HSpice implementation, transmission gate latch, detectable shorted interconnects, open interconnects, short-to-power faults, short-to-ground faults, pin fault test set, multiplexer-based test set, sequential elements, 2-state state machines, simulation, fault diagnosis, logic testing, finite state machines, integrated circuit testing, sequential circuits, CMOS, circuit analysis computing, CMOS logic circuits, SPICE, stuck open faults, checking experiments, stuck-on faults
31	Ahmad Slo, Sukanya Bhowmik, Kurt Rothermel	hSPICE: State-Aware Event Shedding in Complex Event Processing.	CoRR	2020	DBLP BibTeX RDF
31	Ahmad Slo, Sukanya Bhowmik, Kurt Rothermel	hSPICE: state-aware event shedding in complex event processing.	DEBS	2020	DBLP DOI BibTeX RDF
31	Kento Suzuki, Nobukazu Takai, Masato Kato, Hiroaki Seki, Yoshiki Sugawara, Haruo Kobayashi 0001	Comparator circuits automation by combination of distributed genetic algorithm and HSPICE optimization.	ASICON	2015	DBLP DOI BibTeX RDF
31	Wei Wei 0034, Jie Han 0001, Fabrizio Lombardi	Robust HSPICE modeling of a single electron turnstile.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
31	Linbin Chen, Fabrizio Lombardi, Jie Han 0001	An enhanced HSPICE macromodel of a PCM cell with threshold switching and recovery behavior.	MWSCAS	2014	DBLP DOI BibTeX RDF
31	Pilin Junsangsri, Fabrizio Lombardi, Jie Han 0001	HSPICE macromodel of a Programmable Metallization Cell (PMC) and its application to memory design.	NANOARCH	2014	DBLP DOI BibTeX RDF
31	Farshad Merrikh-Bayat, Nafiseh Mirebrahimi, Farhad Bayat	Circuit proposition for copying the value of a resistor into a memristive device supported by HSPICE simulation	CoRR	2013	DBLP BibTeX RDF
31	Subrata Biswas, Kazi Muhammad Jameel, Rahmanul Haque, Md. Abul Hayat	A Novel Design and Simulation of a Compact and Ultra Fast CNTFET Multi-valued Inverter Using HSPICE.	UKSim	2012	DBLP DOI BibTeX RDF
31	Pilin Junsangsri, Fabrizio Lombardi, Jie Han 0001	Macromodeling a phase change memory (PCM) cell by HSPICE.	NANOARCH	2012	DBLP DOI BibTeX RDF
31	Fabrizio Lombardi, Wei Wei 0034, Jie Han 0001	Modeling a single electron turnstile in HSPICE.	ACM Great Lakes Symposium on VLSI	2012	DBLP DOI BibTeX RDF
31	Nobuo Akou, Tetsuya Asai, Takeshi Yanagida, Tomoji Kawai, Yoshihito Amemiya	A behavioral model of unipolar resistive RAMs and its application to HSPICE integration.	IEICE Electron. Express	2010	DBLP DOI BibTeX RDF
31	Tom J. Kazmierski, Dafeng Zhou, Bashir M. Al-Hashimi	HSPICE implementation of a numerically efficient model of CNT transistor.	FDL	2009	DBLP BibTeX RDF
31	Thomas Noulis, Stylianos Siskos, Gérard Sarrabayrouse	Comparison between BSIM4.X and HSPICE flicker noise models in NMOS and PMOS transistors in all operating regions.	Microelectron. Reliab.	2007	DBLP DOI BibTeX RDF
31	Jin-Gu Lee, Dae Hwan Kim, Jaegab Lee, Dong Myong Kim, Kyeong-Sik Min	A compact HSPICE macromodel of resistive RAM.	IEICE Electron. Express	2007	DBLP DOI BibTeX RDF
31	Fengming Zhang, Rui Tang, Yong-Bin Kim	SET-based nano-circuit simulation and design method using HSPICE.	Microelectron. J.	2005	DBLP DOI BibTeX RDF
31	Aravind R. Valkodai, Tajinder Manku	Modeling and designing silicon thin-film inductors and transformers using HSPICE for RFIC applications.	Integr.	1997	DBLP DOI BibTeX RDF
30	Junlin Zhou, Mengzhang Cheng, Leonard Forbes	SPICE models for flicker noise in p-MOSFETs in the saturationregion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
30	Dingming Xie, Leonard Forbes	Phase noise on a 2-GHz CMOS LC oscillator.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
30	Shiyou Zhao, Kaushik Roy 0001	Estimation of Switching Noise on Power Supply Lines in Deep Sub-micron CMOS Circuits.	VLSI Design	2000	DBLP DOI BibTeX RDF	switching noise, Ldi/dt noise, maximum switching current, IR voltage drop
25	Lei Wang 0003, Lei Chen 0010, Zhiping Wen 0001, Huabo Sun, Shuo Wang	A Novel High-Density Single-Event Upset Hardened Configurable SRAM Applied to FPGA.	ReConFig	2009	DBLP DOI BibTeX RDF	Heavy ion, CSRAM, Medici, FPGA, HSPICE
25	Richard Trihy	Addressing library creation challenges from recent Liberty extensions.	DAC	2008	DBLP DOI BibTeX RDF	Liberty, Liberty NCX, composite current source (CCS) models, nonlinear delay model (NLDM), nonlinear power model (NLPM), HSPICE
20	Karthikeyan Lingasubramanian, Sanjukta Bhanja	An Error Model to Study the Behavior of Transient Errors in Sequential Circuits.	VLSI Design	2009	DBLP DOI BibTeX RDF
20	Hao Xu 0010, Wen-Ben Jone, Ranga Vemuri	Accurate energy breakeven time estimation for run-time power gating.	ICCAD	2008	DBLP DOI BibTeX RDF
20	Rajesh Garg, Peng Li 0001, Sunil P. Khatri	Modeling dynamic stability of SRAMS in the presence of single event upsets (SEUs).	ISCAS	2008	DBLP DOI BibTeX RDF
20	Tatsuya Koyagi, Masahiro Fukui, Resve A. Saleh	Delay macromodeling and estimation for RTL.	ISCAS	2008	DBLP DOI BibTeX RDF
20	Paulo F. Butzen, Leomar S. da Rosa Jr., Erasmo J. D. Chiappetta Filho, Dionatan S. Moura, André Inácio Reis, Renato P. Ribas	Simple and accurate method for fast static currentestimation in cmos complex gates with interaction ofleakage mechanisms.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	leakage estimation, logic design, cmos gates
20	Wanping Zhang, Ling Zhang, Rui Shi 0003, He Peng, Zhi Zhu, Lew Chua-Eoan, Rajeev Murgai, Toshiyuki Shibuya, Noriyuki Ito, Chung-Kuan Cheng	Fast power network analysis with multiple clock domains.	ICCD	2007	DBLP DOI BibTeX RDF
20	Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen	Analytical model for crosstalk and intersymbol interference in point-to-point buses.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
20	Daisuke Atuti, Takashi Morie, Kazuyuki Aihara	A Current-Sampling-Mode Arbitrary Chaos Generator Circuit Using Pulse Modulation Approach Driven by Quantized Nonlinear Waveforms.	APCCAS	2006	DBLP DOI BibTeX RDF
20	H. Kondou, Sumio Fukai, Yohei Ishikawa	Multiple-valued SRAM with FG-MOSFETs.	APCCAS	2006	DBLP DOI BibTeX RDF
20	Suvodeep Gupta, Srinivas Katkoori	Intrabus crosstalk estimation using word-level statistics.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
20	Ahmad Yazdi, Payam Heydari	The Design and Analysis of Non-Uniform Down-Sized Differential Distributed Amplifiers.	ISQED	2004	DBLP DOI BibTeX RDF
20	Makram M. Mansour, Mohammad M. Mansour, Amit Mehrotra	Modified Sakurai-Newton Current Model and its Applications to CMOS Digital Circuit Design.	ISVLSI	2003	DBLP DOI BibTeX RDF
20	Martin Omaña 0001, Giacinto Papasso, Daniele Rossi 0001, Cecilia Metra	A Model for Transient Fault Propagation in Combinatorial Logic.	IOLTS	2003	DBLP DOI BibTeX RDF
20	Keerthi Heragu, Manish Sharma, Rahul Kundu, Ronald D. Blanton	Test vector generation for charge sharing failures in dynamic logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
20	Li Ding 0002, Pinaki Mazumder	Accurate Estimating Simultaneous Switching Noises by Using Application Specific Device Modeling.	DATE	2002	DBLP DOI BibTeX RDF
20	Ashok K. Murugavel, N. Ranganathan	A Real Delay Switching Activity Simulator Based on Petri Net Modeling.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
20	Chien-Cheng Yu, Weiping Wang, Bin-Da Liu	A new level converter for low-power applications.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
20	Suhwan Kim, Conrad H. Ziesler, Marios C. Papaefthymiou	Design, Verification, and Test of a True Single-Phase 8-bit Adiabatic Multiplier.	ARVLSI	2001	DBLP DOI BibTeX RDF
20	Keerthi Heragu, Manish Sharma, Rahul Kundu, R. D. (Shawn) Blanton	Testing of Dynamic Logic Circuits Based on Charge Sharing.	VTS	2001	DBLP DOI BibTeX RDF
20	Dingming Xie, Mengzhang Cheng, Leonard Forbes	SPICE models for flicker noise in n-MOSFETs from subthreshold tostrong inversion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
20	Ram K. Krishnamurthy, L. Richard Carley	Exploring the design space of mixed swing quadrail for low-power digital circuits.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
20	Sherif H. K. Embabi, R. Damodaran	Delay models for CMOS, BiCMOS and BiNMOS circuits and their applications for timing simulations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
10	Shrikanth Ganapathy, Ramon Canal, Antonio González 0001, Antonio Rubio 0001	MODEST: a model for energy estimation under spatio-temporal variability.	ISLPED	2010	DBLP DOI BibTeX RDF	dsm scaling, spatio-temporal variability, cache design
10	Prateek Mishra, Anish Muttreja, Niraj K. Jha	Low-power FinFET circuit synthesis using multiple supply and threshold voltages.	ACM J. Emerg. Technol. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Low-power, linear programming, synthesis, TCMS
10	Zhimin Chen 0002, Syed Haider, Patrick Schaumont	Side-Channel Leakage in Masked Circuits Caused by Higher-Order Circuit Effects.	ISA	2009	DBLP DOI BibTeX RDF
10	Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria	An interconnect-aware delay model for dynamic voltage scaling in NM technologies.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	dynamic voltage scaling (dvs), interconnects, delay model
10	Palanichamy Manikandan, Bjørn B. Larsen, Einar J. Aas	Design of novel CAM core cell structures for an efficient implementation of low power BCAM system.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	binary content addressable memory (bcam), core cell, match line scheme, low power
10	Soheil Ziabakhsh, Hosein Alavi-Rad, Mohammad Alavi-Rad, Mohammad Mortazavi	The design of a low-power high-speed current comparator in 0.35-m CMOS technology.	ISQED	2009	DBLP DOI BibTeX RDF
10	Shan Zeng, Wenjian Yu, Wanping Zhang, Jian Wang, Xianlong Hong, Chung-Kuan Cheng	Efficient power network analysis with complete inductive modeling.	ISQED	2009	DBLP DOI BibTeX RDF
10	Chenyue Ma, Bo Li, Lining Zhang, Jin He 0003, Xing Zhang 0002, Xinnan Lin, Mansun Chan	A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability.	ISQED	2009	DBLP DOI BibTeX RDF
10	Amirali Shayan Arani, Xiang Hu, He Peng, Wenjian Yu, Wanping Zhang, Chung-Kuan Cheng, Mikhail Popovich, Xiaoming Chen, Lew Chua-Eoan, Xiaohua Kong	Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network.	ISQED	2009	DBLP DOI BibTeX RDF
10	Qian Ying Tang, Qiang Chen, Niloy Chatterjee, Vedank Tripathi, Natarajan Nandagopalan, Sridhar Tirumala	Phenomenological model for gate length bias dependent inverter delay change with emphasis on library characterization.	ISQED	2009	DBLP DOI BibTeX RDF
10	Bardia Bozorgzadeh, Ali Afzali-Kusha	Novel MOS Decoupling Capacitor Optimization Technique for Nanotechnologies.	VLSI Design	2009	DBLP DOI BibTeX RDF
10	Ravikishore Gandikota, Li Ding 0002, Peivand Tehrani, David T. Blaauw	Worst-case aggressor-victim alignment with current-source driver models.	DAC	2009	DBLP DOI BibTeX RDF	CSM, delay noise, crosstalk
10	Yan Li 0029, Vladimir Stojanovic	Yield-driven iterative robust circuit optimization algorithm.	DAC	2009	DBLP DOI BibTeX RDF	robust circuit optimization, variability, yield, analog circuits
10	Pallav Gupta, Rui Zhang, Niraj K. Jha	Automatic Test Generation for Combinational Threshold Logic Networks.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	Sampo Tuuna, Li-Rong Zheng 0001, Jouni Isoaho, Hannu Tenhunen	Modeling of On-Chip Bus Switching Current and Its Impact on Noise in Power Supply Grid.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
10	Gülin Tulunay, Sina Balkir	A Synthesis Tool for CMOS RF Low-Noise Amplifiers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
10	Natasa Miskov-Zivanov, Diana Marculescu	Modeling and Optimization for Soft-Error Reliability of Sequential Circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
10	Edmund Lee 0002, Guy Lemieux, Shahriar Mirabbasi	Interconnect Driver Design for Long Wires in Field-Programmable Gate Arrays.	J. Signal Process. Syst.	2008	DBLP DOI BibTeX RDF	routing design, FPGA, computer-aided design, interconnect design, FPGA interconnect
10	Andrea Calimera, Luca Benini, Enrico Macii	Optimal MTCMOS Reactivation Under Power Supply Noise and Performance Constraints.	DATE	2008	DBLP DOI BibTeX RDF
10	Morteza Saheb Zamani, Maryam Taajobian, Mehdi Saeedi	An Efficient Non-Tree Clock Routing Algorithm for Reducing Delay Uncertainty.	DSD	2008	DBLP DOI BibTeX RDF
10	Zhenghong Wang, Ruby B. Lee	A novel cache architecture with enhanced performance and security.	MICRO	2008	DBLP DOI BibTeX RDF
10	Jorge Oliveros, Dwight Cabrera, Elkim Roa, Wilhelmus A. M. Van Noije	An improved and automated design tool for the optimization of CMOS OTAs using geometric programming.	SBCCI	2008	DBLP DOI BibTeX RDF	OTA design, analog CAD, analog circuit optimization, design methodologies, geometric programming
10	Hongbo Zeng, Jun Wang, Ge Zhang 0007, Weiwu Hu	An interconnect-aware power efficient cache coherence protocol for CMPs.	IPDPS	2008	DBLP DOI BibTeX RDF
10	Xiaoxiao Wang 0001, Mohammad Tehranipoor, Ramyanshu Datta	Path-RO: a novel on-chip critical path delay measurement under process variations.	ICCAD	2008	DBLP DOI BibTeX RDF
10	Tasuku Nagai, Naoya Onizawa, Takahiro Hanyu	High-Speed Timing Verification Scheme Using Delay Tables for a Large-Scaled Multiple-Valued Current-Mode Circuit.	ISMVL	2008	DBLP DOI BibTeX RDF	Verilog-AMS, Static timing analysis, Look-up table
10	Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu	Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices.	ISMVL	2008	DBLP DOI BibTeX RDF	differential-pair circuit, radix-2 signed-digit adder, reliability
10	Angan Das, Ranga Vemuri	ATLAS: An adaptively formed hierarchical cell library based analog synthesis framework.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Sedigheh Hashemi, Omid Shoaei	A 0.9V 10-bit 100 MS/s switched-RC pipelined ADC without using a front-end S/H in 90nm CMOS.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Tong Ge, Joseph Sylvester Chang, Wei Shu	PSRR of bridge-tied load PWM Class D Amps.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Abinash Roy, Masud H. Chowdhury	Analysis of the impacts of signal rise/fall time and skew variations in coupled-RLC interconnects.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Jingye Xu, Pervez Khaled, Masud H. Chowdhury	Full waveform accuracy to estimate delay in coupled digital circuits.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Gülin Tulunay, Sina Balkir	Synthesis of RF CMOS Low Noise Amplifiers.	ISCAS	2008	DBLP DOI BibTeX RDF
10	Yue Chi, Zhushi Xie, Kewen Xia, Xin Liu	Static Power Optimization for CMOS Combinational Circuit Based on Bacterial Colony Chemotaxis Algorithm.	CSSE (5)	2008	DBLP DOI BibTeX RDF
10	Minglang Lin, Ahmet T. Erdogan, Tughrul Arslan, Adrian Stoica	A novel CMOS exponential approximation circuit.	SoCC	2008	DBLP DOI BibTeX RDF
10	Mu-Shun Matt Lee, Chin-Hsun Lin, Chien-Nan Jimmy Liu, Shih-Che Lin	Quick supply current waveform estimation at gate level using existed cell library information.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	current waveform estimation, gate-level
10	Kimish Patel, Wonbok Lee, Massoud Pedram	In-order pulsed charge recycling in off-chip data buses.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	data buses, power, charge recycling
10	Jingye Xu, Pervez Khaled, Masud H. Chowdhury	Fast bus waveform estimation at the presence of coupling noise.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	coupling noise, global interconnect
10	Ricky Yiu-kee Choi, Chi-Ying Tsui	A Low Energy Two-Step Successive Approximation Algorithm for ADC Design.	ISQED	2008	DBLP DOI BibTeX RDF	Successive Approximation Register ADC, Low Power
10	Ling Zhang, Wenjian Yu, Haikun Zhu, Wanping Zhang, Chung-Kuan Cheng	Clock Skew Analysis via Vector Fitting in Frequency Domain.	ISQED	2008	DBLP DOI BibTeX RDF	vector fitting, clock skew, frequency domain
10	Krishnan Ramakrishnan, R. Rajaraman, Narayanan Vijaykrishnan, Yuan Xie 0001, Mary Jane Irwin, Kenan Unlu	Hierarchical Soft Error Estimation Tool (HSEET).	ISQED	2008	DBLP DOI BibTeX RDF	Reliability, Soft Errors, Flip-Flop, Combinational Logic
10	Dong-Shong Liang, Kwang-Jow Gan	New D-Type Flip-Flop Design Using Negative Differential Resistance Circuits.	DELTA	2008	DBLP DOI BibTeX RDF	negative differential resistance(NDR), monostable-bistable transition logic elements(MOBILE)
10	Sampo Tuuna, Jouni Isoaho, Hannu Tenhunen	Analysis of Delay Variation in Encoded On-Chip Bus Signaling under Process Variation.	VLSI Design	2008	DBLP DOI BibTeX RDF
10	Wei Pei, Wen-Ben Jone, Yiming Hu	Fault Modeling and Detection for Drowsy SRAM Caches.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
10	Hao-Chiao Hong	A Fully-Settled Linear Behavior Plus Noise Model for Evaluating the Digital Stimuli of the Design-for-Digital-Testability Sigma-Delta Modulators.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Design-for-digital-testability, Stimulus evaluation, ?-? modulator, Behavioral model
10	Kyung Ki Kim, Yong-Bin Kim, Minsu Choi, Nohpill Park	Leakage Minimization Technique for Nanoscale CMOS VLSI.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	nanometer CMOS, cell characterization, gate-tunneling current, input pattern generation, leakage power, subthreshold leakage current
10	Shuming Chen, Xiangyuan Liu	A Low-Latency and Low-Power Hybrid Insertion Methodology for Global Interconnects in VDSM Designs.	NOCS	2007	DBLP DOI BibTeX RDF	differential-signaling, insertion methodology, on-chip interconnects, low-swing