Search results for "PI-Bus"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
102	Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen	Design theory and implementation for low-power segmented bus systems.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	OLA tree, bus graph model, bus segmentation, bus segmentation cell, low-power design flow, low-power design, ASIC design
95	Kyeong Keol Ryu, Vincent John Mooney	Automated Bus Generation for Multiprocessor SoC Design.	DATE	2003	DBLP DOI BibTeX RDF
94	Bo-Shiun Wu, Tsung-Yi Ho	Bus-pin-aware bus-driven floorplanning.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	bus planning, floorplanning
92	Hon Wai Chun	A distributed constraint-based search architecture for bus timetabling and duty assignment.	APSEC	1997	DBLP DOI BibTeX RDF	distributed constraint-based search architecture, bus timetabling, duty assignment, bus company, bus assignment, driver assignment, bus driver resource allocation, labour constraints, scheduling, software prototype, service industries
92	Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington	A high performance bus and cache controller for PowerPC multiprocessing systems.	ICCD	1995	DBLP DOI BibTeX RDF	high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor
86	Je-Hoon Lee, Young-Sin Cho, Seok-Man Kim, Kyoung-Rok Cho	On-Chip Bus Modeling for Power and Performance Estimation.	SAMOS	2007	DBLP DOI BibTeX RDF	bus modeling, bus latency, SoC, on-chip bus
84	Alexandre Brandwajn	A note on SCSI bus waits.	SIGMETRICS Perform. Evaluation Rev.	2002	DBLP DOI BibTeX RDF
83	Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Teruo Higashino	A real time budgeting method for module-level-pipelined bus based system using bus scenarios.	DAC	2006	DBLP DOI BibTeX RDF	bus based systems, cycle budgeting, real-time systems, pipelined processing, multimedia processing
81	Yasumasa Hayashi, Takashi Matsubara 0002, Yoshiaki Koga	Implementation and evaluation for dependable bus control using CPLD.	PRDC	2000	DBLP DOI BibTeX RDF	phase control, dependable bus control, bus systems, dependable bus operations, bus phase control, reliability, dependability, sequential circuits, system buses, CPLD, asynchronous sequential logic, asynchronous sequential circuit
80	Kazunori Toshioka, Takao Kawamura, Kazunori Sugahara	Web Application to Generate Route Bus Timetables.	ICIW	2008	DBLP DOI BibTeX RDF	Bus Timetable, Bus route system, web application
79	Ruibing Lu, Aiqun Cao, Cheng-Kok Koh	Improving the scalability of SAMBA bus architecture.	ASP-DAC	2005	DBLP DOI BibTeX RDF
79	Kyeong Keol Ryu, Vincent John Mooney III	Automated bus generation for multiprocessor SoC design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
78	Ke Ning, David R. Kaeli	Bus Power Estimation and Power-Efficient Bus Arbitration for System-on-a-Chip Embedded Systems.	PACS	2004	DBLP DOI BibTeX RDF	Embedded System, Power-Aware, External Memory, Media Processor, Bus Arbitration
78	Ruibing Lu, Aiqun Cao, Cheng-Kok Koh	SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
78	Seiichi Saito	A novel analysis method of bus signal transmission and a proposal for high-speed low-power bus circuit.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
73	Gang-Hoon Seo, Won-Yong Jung, Seongsoo Lee, Jae-Kyung Wee	Pipelined Bidirectional Bus Architecture for Embedded Multimedia SoCs.	EUC	2005	DBLP DOI BibTeX RDF
73	Kyeong Keol Ryu, Eung S. Shin, Vincent John Mooney III	A Comparison of Five Different Multiprocessor SoC Bus Architectures.	DSD	2001	DBLP DOI BibTeX RDF
69	Avnish R. Brahmbhatt, Jingyi Zhang, Qing Wu 0002, Qinru Qiu	Low-power bus encoding using an adaptive hybrid algorithm.	DAC	2006	DBLP DOI BibTeX RDF	data probabilistic distribution, delayed bus, weighted code mapping, window based change detection, low power, adaptive algorithm, bus encoding
68	Anders Landin, Fredrik Dahlgren	Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors.	HPCA	1996	DBLP DOI BibTeX RDF	bus-based COMA, standard UMA architecture, program-driven simulation, SPLASH, cache only memory architecture, shared-memory multiprocessors, shared memory systems, memory architecture, cache storage, shared-bus multiprocessors
68	J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, Tien-Fu Chen	Segmented bus design for low-power systems.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
66	Syed Masud Mahmud	Performance Analysis of Multilevel Bus Networks for Hierarchical Multiprocessors.	IEEE Trans. Computers	1994	DBLP DOI BibTeX RDF	multilevel bus networks, hierarchical multiprocessors, partial multiple bus system, bus architecture, hierarchical multiprocessor design, synchronous multilevel bus systems, asynchronous multilevel bus systems, hierarchical reference model, MVA algorithm, performance evaluation, fault tolerance, performance analysis, parallel architectures, connections, queueing theory, multiprocessing systems, analytical models, bandwidth, queueing networks, switches, simulation models, memory bandwidth, packet-switched networks, cost-effectiveness, system buses, local computations, memory modules
65	Carlos Fernández, Rajkumar K. Raval, Chris J. Bleakley	GALS SoC interconnect bus for wireless sensor network processor platforms.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	SoC bus, application specific bus, system on chip bus, WSN, wireless sensor network, low power, GALS
65	Chiung-San Lee, Tai-Ming Parng	A Subsystem-Oriented Performance Analysis Methodology for Shared-Bus Multiprocessors.	IEEE Trans. Parallel Distributed Syst.	1996	DBLP DOI BibTeX RDF	Bottleneck analysis, DMA transfer, separated address bus and data bus, shared-bus multiprocessor system, subsystem access time modeling, subsystem interferences, performance analysis
64	Young-Sin Cho, Eun-Ju Choi, Kyoung-Rok Cho	Modeling and analysis of the system bus latency on the SoC platform.	SLIP	2006	DBLP DOI BibTeX RDF	multi-layer bus, system bus, SoC, latency, platform
63	Ke Ning, David R. Kaeli	Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems.	Trans. High Perform. Embed. Archit. Compil.	2007	DBLP DOI BibTeX RDF	embedded systems, power-aware, external memory, media processor, bus arbitration
63	Sascha Mühlbach, Sebastian Wallner	Secure and Authenticated Communication in Chip-Level Microcomputer Bus Systems with Tree Parity Machines.	ICSAMOS	2007	DBLP DOI BibTeX RDF
63	Kyoung-Sun Jhang, Kang Yi, Soo Yun Hwang	A Two-Level On-Chip Bus System Based on Multiplexers.	Asia-Pacific Computer Systems Architecture Conference	2004	DBLP DOI BibTeX RDF
60	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar, Laxmi N. Bhuyan	Power efficient encoding techniques for off-chip data buses.	CASES	2003	DBLP DOI BibTeX RDF	FV, FV-MSB-LSB, data bus, low power, bus encoding
60	Roman L. Lysecky, Frank Vahid, Tony Givargis	Experiments with the Peripheral Virtual Component Interface.	ISSS	2000	DBLP DOI BibTeX RDF	VCI, bus wrappers, interfacing, system-on-a-chip, intellectual property, Cores, on-chip bus
59	Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang, Scott Lerner, Pavel Kornilovich, Neal Meyer, Robert Bicknell, Charles Otis, Len Seals	A High-Speed Optical Multi-Drop Bus for Computer Interconnections.	Hot Interconnects	2008	DBLP DOI BibTeX RDF	Computer interconnections, Multi-drop Bus, Optical Interconnects, Optical Bus
58	Ke Ning, David R. Kaeli	Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems.	HiPEAC	2005	DBLP DOI BibTeX RDF	embedded systems, Power-aware, external memory, media processor, bus arbitration
58	Shi-Jinn Horng, Horng-Ren Tsai, Yi Pan 0001, Jennifer Seitzer	Optimal Algorithms for the Channel-Assignment Problem on a Reconfigurable Array of Processors with Wider Bus Networks.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	minimum coloring problem, reconfigurable array of processors with wider bus networks, parallel algorithm, interval graph, list ranking, integer sorting, Channel-assignment problem
56	Ruibing Lu, Cheng-Kok Koh	A high performance bus communication architecture through bus splitting.	ASP-DAC	2004	DBLP DOI BibTeX RDF
56	Ruibing Lu, Cheng-Kok Koh	SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips.	ICCAD	2003	DBLP DOI BibTeX RDF
56	Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi	Partial bus-invert coding for power optimization of system level bus.	ISLPED	1998	DBLP DOI BibTeX RDF
54	Stephen K. Sunter	A low cost 100 MHz analog test bus.	VTS	1995	DBLP DOI BibTeX RDF	analog test bus, on-chip analog bus, digital three-state inverter, low-input capacitance, signal bandwidth, bus input, design for testability, DFT, integrated circuit design, mixed-signal circuits, capacitance, mixed analogue-digital integrated circuits, IC design, 100 MHz
53	Jun-hee Yoo, Dongwook Lee, Sungjoo Yoo, Kiyoung Choi	Communication Architecture Synthesis of Cascaded Bus Matrix.	ASP-DAC	2007	DBLP DOI BibTeX RDF	AMBA3 AXI, cascaded bus matrix, on-chip communication architecture, bus topology, encoding method, traffic group encoding, simulated annealing, design space exploration
53	Wei-Chung Cheng, Jian-Lin Liang, Massoud Pedram	Software-Only Bus Encoding Techniques for an Embedded System.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	memory bus encoding, bus activity minimization, CompactFlash, low power, Flash memory, LCD
53	Sharath Jayaprakash, Nihar R. Mahapatra	Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses.	VLSI Design	2007	DBLP DOI BibTeX RDF
53	Constantine Katsinis, Bahram Nabet	A Scalable Interconnection Network Architecture for Petaflops Computing.	J. Supercomput.	2004	DBLP DOI BibTeX RDF	petaflops computing, performance analysis, interconnection networks, computer architecture
53	H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask	An SBus Monitor Board.	FPGA	1995	DBLP DOI BibTeX RDF
53	Lee-Juan Fan, Chang-Biau Yang, Shyue-Horng Shiau	Routing Algorithms on the Bus-Based Hypercube Network.	IEEE Trans. Parallel Distributed Syst.	2005	DBLP DOI BibTeX RDF	Multiple-bus network, fault tolerance, hypercube, routing algorithm, diameter
53	Yan Zhang 0028, John C. Lach, Kevin Skadron, Mircea R. Stan	Odd/even bus invert with two-phase transfer for buses with coupling.	ISLPED	2002	DBLP DOI BibTeX RDF	bus invert, buses with coupling, coding for low-power I/O
53	Hung-Kuei Ku, John P. Hayes	Connective Fault Tolerance in Multiple-Bus Systems.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	interconnection methods, fault tolerance, multiprocessors, graph models, Multiple-bus systems
52	Yi-Ting Lin, Chien-Chou Wang, Ing-Jer Huang	AMBA AHB bus potocol checker with efficient debugging mechanism.	ISCAS	2008	DBLP DOI BibTeX RDF
52	Sujan Pandey, Manfred Glesner	Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
52	Sanghun Lee, Chanho Lee	A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
52	Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada	Transaction Level Error Susceptibility Model for Bus Based SoC Architectures.	ISQED	2006	DBLP DOI BibTeX RDF
52	Chang Hee Pyoun, Chi-Ho Lin, Hi-Seok Kim, Jong-Wha Chong	The Efficient Bus Arbitration Scheme in SoC Environment.	IWSOC	2003	DBLP DOI BibTeX RDF
52	Cheng-Ta Hsieh, Massoud Pedram	Architectural energy optimization by bus splitting.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
49	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar	A tunable bus encoder for off-chip data buses.	ISLPED	2005	DBLP DOI BibTeX RDF	TUBE, data bus, data bus encoding, tunable bus encoder
48	Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar	Energy-efficient encoding techniques for off-chip data buses.	ACM Trans. Embed. Comput. Syst.	2009	DBLP DOI BibTeX RDF	Low-power data buses, bus switching, internal capacitances, encoding
48	Wissam Hlayhel, Daniel Litaize, Laurent Fesquet, Jacques Henri Collet	Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures.	IEEE PACT	1998	DBLP DOI BibTeX RDF	Bandwidth requirement, SMP architecture, optical bus, shared bus
48	Saied Hosseini-Khayat, Andreas D. Bovopoulos	A Simple and Efficient Bus Management Scheme that Supports Continuous Streams	ACM Trans. Comput. Syst.	1995	DBLP DOI BibTeX RDF	bus management, continuous stream, multimedia workstation, bus arbitration
47	Hui Kong 0002, Tan Yan, Martin D. F. Wong	Automatic bus planner for dense PCBs.	DAC	2009	DBLP DOI BibTeX RDF	PCB routing, bus planning, topological routing, layer assignment
47	Lan Gao, Jun Yang 0002, Marek Chrobak, Youtao Zhang, San Nguyen, Hsien-Hsin S. Lee	A low-cost memory remapping scheme for address bus protection.	PACT	2006	DBLP DOI BibTeX RDF	address bus leakage protection, secure processor
47	Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt	System-level power-performance trade-offs in bus matrix communication architecture synthesis.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	bus matrix synthesis, system-on-chip, power estimation, communication architectures, power-performance trade-offs
47	Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King	Hierarchical value cache encoding for off-chip data bus.	ISLPED	2006	DBLP DOI BibTeX RDF	data bus encoding, hierarchical value cache, energy
47	Harmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka	A dual-VDD boosted pulsed bus technique for low power and low leakage operation.	ISLPED	2006	DBLP DOI BibTeX RDF	pulsed bus, leakage, repeaters, Dual-VDD
47	Ann T. Tai, Savio N. Chau, Leon Alkalai	COTS-Based Fault Tolerance in Deep Space: Qualitative and Quantitative Analyses of a Bus Network Architecture.	HASE	1999	DBLP DOI BibTeX RDF	COTS-based fault tolerance, deep-space applications, bus network reliability, tree topology, IEEE 1394
47	Huan-Yu Tu, Lois Wright Hawkes	Network Simulations of a General Class of Partial-Connection Multiple-Bus Systems.	MASCOTS	1999	DBLP DOI BibTeX RDF	multiple-bus, fault-tolerant, routing, CSMA/CD
47	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
47	Hua Xiang 0001, Liang Deng, Li-Da Huang, Martin D. F. Wong	OPC-Friendly Bus Driven Floorplanning.	ISQED	2007	DBLP DOI BibTeX RDF
47	Hui Guo, Ying Jiang	Application Layer Definition and Analyses of Controller Area Network Bus for Wire Harness Assembly Machine.	CIMCA/IAWTIC	2006	DBLP DOI BibTeX RDF
47	Lin Xie, Peiliang Qiu, Qinru Qiu	Partitioned bus coding for energy reduction.	ASP-DAC	2005	DBLP DOI BibTeX RDF
47	Liang Deng, Martin D. F. Wong	Energy optimization in memory address bus structure for application-specific systems.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF
47	Hua Xiang 0001, Xiaoping Tang, Martin D. F. Wong	Bus-driven floorplanning.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
47	Constantine Katsinis, Diana Hecht	Fault-Tolerant DSM on the SOME-Bus Multiprocessor Architecture with Message Combining.	IPDPS	2004	DBLP DOI BibTeX RDF
47	Hua Xiang 0001, Xiaoping Tang, Martin D. F. Wong	Bus-Driven Floorplanning.	ICCAD	2003	DBLP DOI BibTeX RDF
47	Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, Theodore S. Papatheodorou	Scheduling Algorithms with Bus Bandwidth Considerations for SMPs.	ICPP	2003	DBLP DOI BibTeX RDF
47	Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi	Partial bus-invert coding for power optimization of application-specific systems.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
47	Cheng-Ta Hsieh, Massoud Pedram	Architectural Power Optimization by Bus Splitting.	DATE	2000	DBLP DOI BibTeX RDF
47	Woo-Jong Hahn, Ando Ki, Kee-Wook Rim, Soo-Won Kim	Electronics and Telecommunications Research Institute: A Multiprocessor Server with a New Highly Pipelined Bus.	IPPS	1996	DBLP DOI BibTeX RDF
47	T. Pattabhiraman, Nick Cercone	Representing and Using Protosemantic Information in Generating Bus Route Descriptions.	KBCS	1989	DBLP DOI BibTeX RDF
46	Brian J. d'Auriol	The systems edge of the Parameterized Linear Array with a Reconfigurable Pipelined Bus System (LARPBS(p)) optical bus parallel computing model.	J. Supercomput.	2009	DBLP DOI BibTeX RDF	Parallel computing model, Optical bus
46	Sujan Pandey, Nurten Utlu, Manfred Glesner	Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
44	Krishnan Sundaresan, Nihar R. Mahapatra	Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses.	ISQED	2008	DBLP DOI BibTeX RDF	Bus Energy, Self Heating, Wire Permutation, Optimization, Interconnect, Layout, Temperature, On-Chip Bus
44	Basem A. Nayfeh, Kunle Olukotun, Jaswinder Pal Singh	The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors.	HPCA	1996	DBLP DOI BibTeX RDF	shared-cache clustering, small-scale shared-memory multiprocessors, shared global bus, low-latency interconnections, performance evaluation, shared memory systems, cache storage, memory system, multichip module, L2 cache, processor performance, high-bandwidth, bus contention
43	Hong Jiang, Kenneth C. Smith	PPMB: A Partial-Multiple-Bus Multiprocessor Architecture with Improved Cost-Effectiveness.	IEEE Trans. Computers	1992	DBLP DOI BibTeX RDF	PPMB, partial-multiple-bus multiprocessor architecture, processor-oriented partial-multiple-bus, memory-oriented partial-multiple-bus, system bandwidth, simulation, performance evaluation, design, performance analysis, interconnection networks, computer architecture, multiprocessor interconnection networks, cost-effectiveness, arbitration
43	Tan Yan, Martin D. F. Wong	Theories and algorithms on single-detour routing for untangling twisted bus.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	printed circuit board (PCB), single-detour routing, twisted bus, dynamic programming, Bus routing
43	Hettihe P. Dharmasena, Ramachandran Vaidyanathan	Lower Bounds on the Loading of Multiple Bus Networks for Binary Tree Algorithms.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF	Multiple bus networks, binary tree algorithms, bus loading, interconnection networks, lower bounds
43	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Fast exploration of bus-based on-chip communication architectures.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	bus cycle accurate modeling, fast communication architecture exploration, shared bus architectures, transaction level modeling, AMBA
43	Roman L. Lysecky, Frank Vahid	Prefetching for improved bus wrapper performance in cores.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	Bus wrapper, PVCI, VSIA, interfacing, system-on-a-chip, intellectual property, cores, design reuse, on-chip bus
43	Roman L. Lysecky, Frank Vahid, Tony Givargis	Techniques for Reducing Read Latency of Core Bus Wrappers.	DATE	2000	DBLP DOI BibTeX RDF	bus wrapper, interfacing, system-on-a-chip, intellectual property, Cores, design reuse, on-chip bus
43	Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger	A Synthesis System For Bus-Based Wavefront Array Architectures.	ASAP	1996	DBLP DOI BibTeX RDF	synthesis system, bus-based wavefront array architectures, datapath synthesis system, reconfigurable datapath architecture, internal data bus, automatic mapping, datapath units, high speed datapaths, parallel architectures, rapid prototyping, reconfigurable architectures, software prototyping, fine grained parallelism, data manipulations
43	Thin-Fong Tsuei, Mary K. Vernon	A Multiprocessor Bus Design Model Validated by System Measurement.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	commercial multiprocessor bus, bus design, asynchronous memorywrite operations, in-order delivery, processor read requests, memoryresponses, outstanding processor requests, two-level hierarchical model, mean value analysis techniques, measured system performance, parallel program workloads, memory access characteristics, analytic queueing models, model tractability, detailed simulation, system design tradeoffs, parallel programming, formal verification, Markov chain, Markov processes, queueing theory, multiprocessing systems, queueing networks, system buses, priority scheduling, performanceevaluation, system measurement
43	Carlos G. Bilich, Zaijun Hu	Experiences with the Certification of a Generic Functional Safety Management Structure According to IEC 61508.	SAFECOMP	2009	DBLP DOI BibTeX RDF	Functional Safety, reusable components, IEC 61508
43	Bas Breijer, Filipa Duarte, Stephan Wong	An OCM based shared Memory controller for Virtex 4.	FPL	2007	DBLP DOI BibTeX RDF
43	Srinivasa R. Sridhara, Naresh R. Shanbhag	Coding for system-on-chip networks: a unified framework.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
43	Sujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mühlhäuser	High level hardware/software communication estimation in shared memory architecture.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
42	Ricardo Bedin França, Leandro Buss Becker, Jean-Paul Bodeveix, Jean-Marie Farines, Mamoun Filali	Towards Safe Design of Synchronous Bus Protocols in Event-B.	SBMF	2009	DBLP DOI BibTeX RDF	synchronous systems, Event-B, parameterized systems, bus protocols
42	Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng	Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications.	DAC	2009	DBLP DOI BibTeX RDF	Steiner graph, gated bus, power efficiency
42	Kriangsak Vanitchakornpong, Nakorn Indra-Payoong, Agachai Sumalee, Pairoj Raothanachonkun	Constrained Local Search Method for Bus Fleet Scheduling Problem with Multi-depot with Line Change.	EvoWorkshops	2008	DBLP DOI BibTeX RDF	Bus scheduling, Multi-depot and line change, Constrained local search
42	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects.	ISQED	2008	DBLP DOI BibTeX RDF	bus coding, delay, process variation
42	Jill H. Y. Law, Evangeline F. Y. Young	Multi-bend bus driven floorplanning.	ISPD	2005	DBLP DOI BibTeX RDF	bus planning, floorplanning, VLSI CAD
42	Massimo Conti, Marco Caldari, Giovanni B. Vece, Simone Orcioni, Claudio Turchetti	Performance analysis of different arbitration algorithms of the AMBA AHB bus.	DAC	2004	DBLP DOI BibTeX RDF	AMBA AHB BUS, arbitration algorithm, performance, systemC
42	Ching-Chih Han, Chao-Ju Hou, Kar Shun Tsoi, Sean Ho	Dynamic Establishment and Termination of Real-Time Message Streams in Dual-Bus Networks.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Dual-bus networks, $(C,D){hbox{-}}{rm smooth}$ message model, message stream setup and tear-down, temporal QoS guarantee, distance constraint
42	Ramachandran Vaidyanathan, Sudharani Nadella	Fault-Tolerant Multiple Bus Networks for Fan-In Algorithms.	IPPS	1996	DBLP DOI BibTeX RDF	Multiple bus networks, Fan-in algorithms, Fault-tolerance, Parallel processing, Interconnection networks
42	K. C. Lee	A Virtual Bus Architecture for Dynamic Parallel Processing.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	virtual bus architecture, dynamic parallel processing, parallel/distributed machine, end-to-end communication bandwidth, communicationpatterns, data collection operations, nonuniformtraffic, open system parallel interface, open system communication backbone, scheduling, interconnection network, delays, multiprocessor interconnection networks, open systems, dynamic load balancing, network interfaces, queuing delay
42	Guenter Klas	Protocol Optimization for a Packet-Switched Bus in Case of Burst Traffic by Means of GSPN.	Application and Theory of Petri Nets	1993	DBLP DOI BibTeX RDF	Bus Pipeline, Performance Modeling, Multiprocessor Systems, GSPN