Search results for "PLL"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
120	Martin John Burbidge	Detection and Evaluation of Deterministic Jitter Causes in CP-PLL's Due to Macro Level Faults and Pre-Detection Using Simple Methods.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	CP-PLL, deterministic jitter, jitter, PLL
118	Martin John Burbidge, Jim Tijou, Andrew Richardson 0001	Techniques for Automatic On Chip Closed Loop Transfer Function Monitoring For Embedded Charge Pump Phase Locked Loops.	DATE	2003	DBLP DOI BibTeX RDF	CP-PLL, TEST, DfT, BIST, PLL
89	Takeo Yasuda, Hiroaki Fujita, Hidetoshi Onodera	A dynamically phase adjusting PLL with a variable delay.	ASP-DAC	2001	DBLP DOI BibTeX RDF	phase adjust, variable delay, lock-up, PLL
89	Chanwoo Park, Jinbeom Lee, Younglok Kim	Modified Reduced Constellation PLL for Higher Order QAM.	ISCAS	2007	DBLP DOI BibTeX RDF
89	Martin John Burbidge, Frédéric Poullet, Jim Tijou, Andrew Richardson 0001	Investigations for Minimum Invasion Digital Only Built-In "Ramp" Based Test Techniques for Charge Pump PLL's.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	test, DfT, BIST, jitter, phase locked loop
78	T. M. Almaida, Moisés Simões Piedade	High performance analog and digital PLL design.	ISCAS (4)	1999	DBLP DOI BibTeX RDF
67	Ching-Lung Ti, Yao-Hong Liu, Tsung-Hsien Lin	A 2.4-GHz fractional-N PLL with a PFD/CP linearization and an improved CP circuit.	ISCAS	2008	DBLP DOI BibTeX RDF
67	Xiaolue Lai, Yayun Wan, Jaijeet S. Roychowdhury	Fast PLL simulation using nonlinear VCO macromodels for accurate prediction of jitter and cycle-slipping due to loop non-idealities and supply noise.	ASP-DAC	2005	DBLP DOI BibTeX RDF
67	Thomas Olsson 0001, Peter Nilsson 0001	A digitally controlled PLL for digital SOCs.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
65	Prakash Easwaran, Prasenjit Bhowmik, Rupak Ghayal	Specification Driven Design of Phase Locked Loops.	VLSI Design	2009	DBLP DOI BibTeX RDF
65	Abdelohahab Djemouai, Mohamad Sawan	Fast-locking low-jitter integrated CMOS phase-locked loop.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
56	Jaehong Ko, Wookwan Lee, Soo-Won Kim	2.5GHz PLL with current matching charge-pump for 10Gbps transmitter design.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	jitter, PLL, output buffer, charge-pump
56	John G. Maneatis, Jaeha Kim, Iain McClatchie, Jay Maxey, Manjusha Shankaradas	Self-biased high-bandwidth low-jitter 1-to-4096 multiplier clock generator PLL.	DAC	2003	DBLP DOI BibTeX RDF	adaptive bandwidth, clock multiplication, frequency synthesis, self biased, analog circuits, PLL, phase-locked loop, clock generation
56	Yang Liu, Ashok Kumar Srivastava, Yao Xu	A switchable PLL frequency synthesizer and hot carrier effects.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cmos phase-locked loop, hot carrier effects, jitter, voltage-controlled oscillator, phase noise
56	Yasuaki Sumi, Shigeki Obote, Naoki Kitai, Ryousuke Furuhashi, Yoshitaka Matsuda, Yutaka Fukui	PLL frequency synthesizer with an auxiliary programmable divider.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
54	Lei Yang 0019, Cherry Wakayama, C.-J. Richard Shi	Noise aware behavioral modeling of the E-Delta fractional-N frequency synthesizer.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	jitter noise, PLL, phase noise, frequency synthesizer
54	Charlotte Y. Lau, Michael H. Perrott	Fractional-N frequency synthesizer design at the transfer function level using a direct closed loop realization algorithm.	DAC	2003	DBLP DOI BibTeX RDF	fractional-N, sigma, design, PLL, frequency, delta, synthesizer
54	Seongwon Kim, Mani Soma, Dilip Risbud	An Effective Defect-Oriented BIST Architecture for High-Speed Phase-Locked Loops.	VTS	2000	DBLP DOI BibTeX RDF	Defect-oriented testing, Built-In Self-Test (BIST), Design for Testability, PLL, Self-Checking Circuits
54	Sounil Biswas, R. D. (Shawn) Blanton	Test Compaction for Mixed-Signal Circuits Using Pass-Fail Test Data.	VTS	2008	DBLP DOI BibTeX RDF	pass-fail test data, boolean minimization, minimum constrained subset cover, Mixed-signal test, test compaction
46	Stephen K. Sunter, Aubin Roy	Noise-Insensitive Digital BIST for any PLL or DLL.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	BIST, Jitter, Design for test, PLL, Mixed-signal test, DLL
46	Martin John Burbidge, Ian Andrew Grout	Evolution of a Remote Access Facility for a PLL Measurement Course.	e-Science	2006	DBLP DOI BibTeX RDF	test, PLL, Remote laboratory
46	Michael H. Perrott	Fast and accurate behavioral simulation of fractional-N frequency synthesizers and other PLL/DLL circuits.	DAC	2002	DBLP DOI BibTeX RDF	fractional-N, sigma, PLL, frequency, delta, DLL, synthesizer
45	Chin-Cheng Kuo, Pei-Syun Lin, Chien-Nan Jimmy Liu	A SCORE macromodel for PLL designs to analyze supply noise interaction issues at behavioral level.	ASP-DAC	2009	DBLP DOI BibTeX RDF
45	Adnan Gundel, William N. Carr	Ultra Low Power CMOS PLL Clock Synthesizer for Wireless Sensor Nodes.	ISCAS	2007	DBLP DOI BibTeX RDF
45	Baoyong Chi, Xueyi Yu, Woogeun Rhee, Zhihua Wang 0001	A Fractional-N PLL for Digital Clock Generation With an FIR-Embedded Frequency Divider.	ISCAS	2007	DBLP DOI BibTeX RDF
45	Vijay Khawshe, Pravin V. Kumar, Renu Rangnekar, Kapil Vyas, Kashi Prabu, Mahabaleshwara, Manish Jain, Navin K. Mishra, Abhijit Abhyankar	A 2.5Gbps Quad CMOS Transceiver Cell Using Regulated Supply Low Jitter PLL.	VLSI Design	2007	DBLP DOI BibTeX RDF
45	Shujin Chen, Baozhu Ma, Zhengyun Ran, Fei Guo, Huade Li	A New Initial Rotor Position Detection Technology Based on HF Injection and Software PLL.	ICICIC (1)	2006	DBLP DOI BibTeX RDF
45	Xiaolue Lai, Jaijeet S. Roychowdhury	TP-PPV: piecewise nonlinear, time-shifted oscillator macromodel extraction for fast, accurate PLL simulation.	ICCAD	2006	DBLP DOI BibTeX RDF
45	Jiefeng Yan, Lei Xie, Xiaoyang Zeng, Tingao Tang	Adaptive bandwidth PLL with compact current mode filter.	ISCAS	2006	DBLP DOI BibTeX RDF
45	Eva Tatschl-Unterberger, Sasan Cyrusian, Michael Ruegg	A 2.5GHz phase-switching PLL using a supply controlled 2-delay-stage 10GHz ring oscillator for improved jitter/mismatch.	ISCAS (6)	2005	DBLP DOI BibTeX RDF
45	Chin-Cheng Kuo, Yu-Chien Wang, Chien-Nan Jimmy Liu	An efficient bottom-up extraction approach to build accurate PLL behavioral models for SOC designs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF
45	Salvatore Levantino, Luca Romanò, Carlo Samori, Andrea L. Lacaita	Fast-switching analog PLL with finite-impulse response.	ISCAS (4)	2004	DBLP DOI BibTeX RDF
45	Wen-Chi Wu, Chih-Chien Huang, Chih-Hsiung Chang, Nai-Heng Tseng	Low-power CMOS PLL for clock generator.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
45	Kasin Vichienchom, Wentai Liu	Analysis of phase noise due to bang-bang phase detector in PLL-based clock and data recovery circuits.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
45	Yi-Cheng Chang, Edwin W. Greeneich	CMOS auto-ranging PLL for low-voltage wideband systems.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
45	Debapriya Sahu	A Completely Integrated Low Jitter CMOS PLL for Analog Front Ends in Systems on Chip Environment.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
45	Ian Brynjolfson, Zeljko Zilic	A new PLL design for clock management applications.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
43	Yifei Luo, Gang Chen, Kuan Zhou	A picosecond TDC architecture for multiphase PLLs.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	time-to-digital converter, vdl, vernier delay line, PLL, soi, tdc
43	Kandeepan Sithamparanathan, Radoslaw Piesiewicz	Frequency Tracking Performance Using a Hyperbolic Digital-Phase Locked Loop for Ka-Band Communication in Rain Fading Channels.	PSATS	2009	DBLP DOI BibTeX RDF	Frequency tracking, digital-phase locked loops, hyperbolic phase detector, Ka-band frequency tracking
43	Angel Abusleme, Boris Murmann	Predictive control algorithm for phase-locked loops.	ISCAS	2008	DBLP DOI BibTeX RDF
43	Ping-Ying Wang, Hsiu-Ming Chang 0001	A charge pump-based direct frequency modulator.	ISCAS	2008	DBLP DOI BibTeX RDF
43	Jiri Haze, Radimir Vrba, Roman Prokop	Design of Phase Locked-Loop for Very Slow Sine-Wave Signals.	ICONS	2008	DBLP DOI BibTeX RDF	sine wave signal, phase locked-loop
43	Tetsuro Endo, Jun Yokota	Generation of White Noise by Using Chaos in Practical Phase-Locked Loop Integrated Circuit Module.	ISCAS	2007	DBLP DOI BibTeX RDF
43	Richard Geisler, John C. Liobe, Martin Margala	Process and Temperature Calibration of PLLs with BiST Capabilities.	ISCAS	2007	DBLP DOI BibTeX RDF
43	Li Zhang 0023, Baoyong Chi, Zhihua Wang 0001, Hongyi Chen, Jinke Yao, Ende Wu	A 2-GHz 6.1-mA Fully-Differential CMOS Phase-Locked Loop.	ISCAS	2007	DBLP DOI BibTeX RDF
43	Aravind R. Nayak, John R. Barry, German S. Feyh, Steven W. McLaughlin	Timing Recovery With Frequency Offset and Random Walk: Cramer-Rao Bound and a Phase-Locked Loop Postprocessor.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
43	Aravind R. Nayak, John R. Barry, German S. Feyh, Steven W. McLaughlin	Timing Recovery With Frequency Offset and Random Walk: Cramér-Rao Bound and a Phase- Locked Loop Postprocessor.	IEEE Trans. Commun.	2006	DBLP DOI BibTeX RDF
43	Sadeka Ali, Martin Margala	A 2.4-GHz auto-calibration frequency synthesizer with on-chip built-in-self-test solution.	ISCAS	2006	DBLP DOI BibTeX RDF
43	Tian Xia, Stephen Wyatt, Rupert Ho	Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration.	DFT	2006	DBLP DOI BibTeX RDF
43	Jun Zou, Daniel Mueller 0001, Helmut E. Graeb, Ulf Schlichtmann	A CPPLL hierarchical optimization methodology considering jitter, power and locking time.	DAC	2006	DBLP DOI BibTeX RDF	hierarchical optimization, pareto-optimal fronts
43	Kuo-Hsing Cheng, Wei-Bin Yang, Shu-Chang Kuo	A dual-slope phase frequency detector and charge pump architecture to achieve fast locking of phased-locked loop.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
43	Yonghui Tang, Randall L. Geiger	Transient bit error rate analysis of data recovery systems using jitter models.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
43	Youcef Fouzar, Yvon Savaria, Mohamad Sawan	A new controlled gain phase-locked loop technique.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
43	Chua-Chin Wang, Yu-Tsun Chien, Ying-Pei Chen	A practical load-optimized VCO design for low-jitter 5 V 500 MHz digital phase-locked loop.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
39	Tsung-Hsien Tsai, Ruey-Bin Sheen, Sheng-Yun Hsu, Ya-Tin Chang, Chih-Hsien Chang, Robert Bogdan Staszewski	A Cascaded PLL (LC-PLL + RO-PLL) with a Programmable Double Realignment Achieving 204fs Integrated Jitter (100kHz to 100MHz) and -72dB Reference Spur.	ISSCC	2022	DBLP DOI BibTeX RDF
35	Suchitav Khadanga	Synchronous programmable divider design for PLL Using 0.18 um cmos technology.	IWSOC	2003	DBLP DOI BibTeX RDF	programmable divider, CMOS integrated circuits, phase locked loop, PLL, Prescaler, frequency synthesizers
35	Régis Roubadia, Sami Ajram, Guy Cathébras	Design of a Low Jitter Multi-Phase Realigned PLL in submicronic CMOS technology.	ISCAS	2007	DBLP DOI BibTeX RDF
35	Adnan Gundel, William N. Carr	A Low Jitter CMOS PLL Clock Synthesizer with 20-400 MHz Locking Range.	ISCAS	2007	DBLP DOI BibTeX RDF
35	Arnaldo Spalvieri	Optimal Loop Filter of the Discrete-time PLL in the Presence of Phase Noise.	ISCC	2006	DBLP DOI BibTeX RDF
35	Quentin Diduck, John C. Liobe, Sadeka Ali, Martin Margala	Process tolerant calibration circuit for PLL applications with BIST.	ISCAS	2006	DBLP DOI BibTeX RDF
35	Volnei A. Pedroni, Ricardo U. Pedroni	PLL-less clock multiplier with self-adjusting phase symmetry.	ISCAS	2006	DBLP DOI BibTeX RDF
35	Jens Anders, Wolfgang Mathis	Simulation techniques for noise-analysis in the PLL design process.	ISCAS	2006	DBLP DOI BibTeX RDF
35	Omid Oliaei	Synchronization and phase synthesis using PLL neural networks.	ISCAS	2006	DBLP DOI BibTeX RDF
35	B. Suresh, V. Visvanathan, R. S. Krishnan, H. S. Jamadagni	Application of Alpha Power Law Models to PLL Design Methodology.	VLSI Design	2005	DBLP DOI BibTeX RDF
35	Hung Tien Bui, Yvon Savaria	10 GHz PLL Using Active Shunt-Peaked MCML Gates and Improved Frequency Acquisition XOR Phase Detector in 0.18 µm CMOS.	IWSOC	2004	DBLP DOI BibTeX RDF
35	Ayman Mounir, Ahmed Mostafa, Maged Fikry	Automatic Behavioural Model Calibration for Efficient PLL System Verification.	DATE	2003	DBLP DOI BibTeX RDF
35	Marco Cassia, Peter Shah, Erik Bruun	A spur-free fractional-N ΣΔ PLL for GSM applications: linear model and simulations.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
35	Qishan Huang, Hua Xu, Jiangtao Yu, Hui Zheng	Parameters Adjusting of Third-Order PLL Used in LEO Mobile Satellite Communication Systems.	AINA	2003	DBLP DOI BibTeX RDF
35	Yiwu Tang, Mohammed Ismail 0001, Steven Bibyk	A new fast-settling gearshift adaptive PLL to extend loop bandwidth enhancement in frequency synthesizers.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
35	Robin R.-B. Sheen, Oscal T.-C. Chen	A CMOS PLL-based frequency synthesizer for wireless communication systems at 0.9, 1.8, 1.9 and 2.4 GHz.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
35	Yonghui Tang, Randall L. Geiger	A 2.5 Gbit/s CMOS PLL for data/clock recovery without frequency divider.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
35	Yi-Chang, Edwin W. Greeneich	A current-controlled oscillator coarse-steering acquisition-aid for high frequency SOI CMOS PLL circuits.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
35	Shigeki Obote, Yasuaki Sumi, Naoki Kitai, Yutaka Fukui, Yoshio Itoh	Performance improvement in a binary phase comparator type PLL frequency synthesizer.	ISCAS (4)	1999	DBLP DOI BibTeX RDF
35	Yasuaki Sumi, Shigeki Obote, Naoki Kitai, Ryousuke Furuhashi, Hidekazu Ishii, Yoshitaka Matsuda, Yutaka Fukui	Dead-zone-less PLL frequency synthesizer by hybrid phase detectors.	ISCAS (4)	1999	DBLP DOI BibTeX RDF
33	Jaehyun Park 0005, Donghwa Shin, Naehyuck Chang, Massoud Pedram	Accurate modeling and calculation of delay and energy overheads of dynamic voltage scaling in modern high-performance microprocessors.	ISLPED	2010	DBLP DOI BibTeX RDF	DVS overhead model, PLL, DVFS, DC-DC converter
33	Ranran Yi, Bangcheng Han, Wei Sheng	Design on the Driving Mode of MEMS Vibratory Gyroscope.	ICIRA (2)	2008	DBLP DOI BibTeX RDF	self-oscillation, Multisim, fixed amplitude, MEMS, PLL
33	Xiaolue Lai, Jaijeet S. Roychowdhury	Advanced tools for simulation and design of oscillators/PLLs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	jitter analysis, automated oscillator, macromodeling technique, amplitude macromodels, injection locking prediction, coupled oscillating systems, SPICE, PLL
33	Rashed Zafar Bhatti, Monty Denneau, Jeff Draper	2 Gbps SerDes design based on IBM Cu-11 (130nm) standard cell technology.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	CDR, CML driver, LVDS, SerDes, duty cycle correction (DCC), jitter and skew compensation, standard cell based serializer and deserializer circuits for high speed signaling, PLL, DLL, phase detection
33	Zhongtao Fu, John Lee, Alyssa B. Apsel	A 6.8GHz low-power and low-phase-noise phase-locked loop design.	ISCAS	2008	DBLP DOI BibTeX RDF
33	Hari Vijay Venkatanarayanan, Michael L. Bushnell	A Jitter Reduction Circuit Using Autocorrelation for Phase-Locked Loops and Serializer-Deserializer (SERDES) Circuits.	VLSI Design	2008	DBLP DOI BibTeX RDF
33	Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel	A Case Study on Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Automatic layout generation, Transient fault injection, Phase-locked loop
33	Rui Fa, Bayan S. Sharif, Charalampos Tsimenidis	Iterative Detection and Phase Recovery for Downlink DS and MC-CDMAFlat Rayleigh Fading Channels.	VTC Spring	2007	DBLP DOI BibTeX RDF
33	Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick D. Wolf	Design Methodology and CAD Tools for Prototyping Delta-Sigma Fractional-N Frequency Synthesizers.	IEEE International Workshop on Rapid System Prototyping	2007	DBLP DOI BibTeX RDF
33	Kunhyuk Kang, Keejong Kim, Kaushik Roy 0001	Variation Resilient Low-Power Circuit Design Methodology using On-Chip Phase Locked Loop.	DAC	2007	DBLP DOI BibTeX RDF
33	Prashant Goyal, Xiaolue Lai, Jaijeet S. Roychowdhury	A fast methodology for first-time-correct design of PLLs using nonlinear phase-domain VCO macromodels.	ASP-DAC	2006	DBLP DOI BibTeX RDF
33	Kuo-Hsing Cheng, Kai-Fei Chang, Yu-Lung Lo, Ching-Wen Lai, Yuh-Kuang Tseng	A 100MHz-1GHz adaptive bandwidth phase-locked loop in 90nm process.	ISCAS	2006	DBLP DOI BibTeX RDF
33	Cristiano Lazzari, Ricardo A. L. Reis, Lorena Anghel	Phase-Locked Loop Automatic Layout Generation and Transient Fault Injection Analysis: A Case Study.	IOLTS	2006	DBLP DOI BibTeX RDF
33	Peter R. Wilson, Reuben Wilcock, Bashir M. Al-Hashimi	A novel switched-current phase locked loop.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
33	Chien-Hung Kuo, Yi-Shun Shih	A frequency synthesizer using two different delay feedbacks.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
33	S. Wanchana, T. Benjanarasuth, D. Isarakorn, J. Ngamwiwit, N. Komine	Phase-locked loop process control system using LQR approach.	ICARCV	2004	DBLP DOI BibTeX RDF
33	Zhenhua Wang	A virtually jitter-free fractional-N divider for a Bluetooth radio.	ISCAS (2)	2003	DBLP DOI BibTeX RDF
33	A. E. Hussein, Mohamed I. Elmasry	Fractional-N frequency synthesizer for wireless communications.	ISCAS (4)	2002	DBLP DOI BibTeX RDF
33	Jinghui Lu, Bernard Grung, Stephen Anderson, Shahriar Rokhsaz	Discrete z-domain analysis of high order phase locked loops.	ISCAS (1)	2001	DBLP DOI BibTeX RDF
33	Tom Egan, Samiha Mourad	Verification of Embedded Phase-Locked Loops.	ISQED	2001	DBLP DOI BibTeX RDF
33	Pascal Acco, Michael Peter Kennedy, Christian Mira, Brian Morley, Bela A. Frigyik	Behavioral modeling of charge pump phase locked loops.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
33	Woogeun Rhee	Design of low-jitter 1-GHz phase-locked loops for digital clock generation.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
32	Maneesha Dalmia, André Ivanov, Sassan Tabatabaei	Power supply current monitoring techniques for testing PLLs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	power supply current monitoring, PLL testing, digital IC, VCO testing, analogue circuit testing, fault detection, phase locked loops, phase-locked loops, current testing, nonlinear circuits, mixed-signal ICs
32	Sangho Jin, Ichiro Kimura, Keigo Watanabe	Controls of servomotors for carry hospital robots.	J. Intell. Robotic Syst.	1993	DBLP DOI BibTeX RDF	Carry hospital robot, computer control, DC servomotor control, PLL control, mobile robot, PI control
26	Nabil Mohammed, Weihua Zhou, Behrooz Bahrani	Comparison of PLL-Based and PLL-Less Control Strategies for Grid-Following Inverters Considering Time and Frequency Domain Analysis.	IEEE Access	2022	DBLP DOI BibTeX RDF
26	Elbert Bechthum, Johan Dijkhuis, Ming Ding 0003, Yuming He, Johan H. C. van den Heuvel, Paul Mateman, Gert-Jan van Schaik, Kenichi Shibata, Minyoung Song, Evgenii Tiurin, Stefano Traferro, Yao-Hong Liu, Christian Bachmann	30.6 A Low-Power BLE Transceiver with Support for Phase-Based Ranging, Featuring 5µs PLL Locking Time and 5.3ms Ranging Time, Enabled by Staircase-Chirp PLL with Sticky-Lock Channel-Switching.	ISSCC	2020	DBLP DOI BibTeX RDF