Search results for "SOC-test"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
84	Sandeep Kumar Goel, Erik Jan Marinissen	SOC test architecture design for efficient utilization of test bandwidth.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	TAM and wrapper design, idle bits, lower bound, test scheduling, SOC test, bandwidth utilization
82	Chih-Yen Lo, Chen-Hsing Wang, Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Shin-Moe Wang, Cheng-Wen Wu	STEAC: A Platform for Automatic SOC Test Integration.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
65	Kuo-Liang Cheng, Jing-Reng Huang, Chih-Wea Wang, Chih-Yen Lo, Li-Ming Denq, Chih-Tsun Huang, Shin-Wei Hung, Jye-Yuan Lee	An SOC Test Integration Platform and Its Industrial Realization.	ITC	2004	DBLP DOI BibTeX RDF
60	Anuja Sehgal, Sudarshan Bahukudumbi, Krishnendu Chakrabarty	Power-aware SoC test planning for effective utilization of port-scalable testers.	ACM Trans. Design Autom. Electr. Syst.	2008	DBLP DOI BibTeX RDF	port-scalable testers, test access architecture, integer linear programming, SoC test
57	Yu Huang 0005, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy	On Concurrent Test of Core-Based SOC Design.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	concurrent SOC test, pin mapping, 2-dimensional bin-packing, test scheduling
55	Anuja Sehgal, Vikram Iyengar, Krishnendu Chakrabarty	SOC test planning using virtual test access architectures.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
54	Dan Zhao, Ronghua Huang, Tomokazu Yoneda, Hideo Fujiwara	Power-Aware Multi-Frequency Heterogeneous SoC Test Framework Design with Floor-Ceiling Packing.	ISCAS	2007	DBLP DOI BibTeX RDF
53	Sandeep Koranne, Vikram Iyengar	On the Use of k-tuples for SoC Test Schedule Representation.	ITC	2002	DBLP DOI BibTeX RDF
53	Qiang Xu 0001, Nicola Nicolici	Modular SOC testing with reduced wrapper count.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
51	Erik Larsson, Zebo Peng	An Integrated Framework for the Design and Optimization of SOC Test Solutions.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	test access mechanism design, test resource placement, test conflicts, power consumption, test scheduling, SOC test, test resource partitioning
50	Hiroshi Date, Toshinori Hosokawa, Michiaki Muraoka	A SoC Test Strategy Based on a Non-Scan DFT Method.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	non-scan DFT, high level design and test, SoC test
50	Jung-Been Im, Sunghoon Chun, Geunbae Kim, Jin-Ho Ahn, Sungho Kang	RAIN (RAndom Insertion) Scheduling Algorithm for SoC Test.	Asian Test Symposium	2004	DBLP DOI BibTeX RDF
45	Sandeep Kumar Goel, Erik Jan Marinissen	Effective and Efficient Test Architecture Design for SOCs.	ITC	2002	DBLP DOI BibTeX RDF
45	Sandeep Koranne	Formulating SoC test scheduling as a network transportation problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
44	Anuja Sehgal, Krishnendu Chakrabarty	Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Full-chip testing, dual-speed TAM, TAM optimization, test scheduling, test access mechanism, SOC testing
44	Anuja Sehgal, Krishnendu Chakrabarty	Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures.	DATE	2004	DBLP DOI BibTeX RDF
44	Praveen Bhojwani, Rabi N. Mahapatra	An Infrastructure IP for Online Testing of Network-on-Chip Based SoCs.	ISQED	2007	DBLP DOI BibTeX RDF
43	Thomas Edison Yu, Tomokazu Yoneda, Krishnendu Chakrabarty, Hideo Fujiwara	Test infrastructure design for core-based system-on-chip under cycle-accurate thermal constraints.	ASP-DAC	2009	DBLP DOI BibTeX RDF	TAM design, thermal-aware test, wrapper design, test scheduling, SOC test
41	Quming Zhou, Kedarnath J. Balakrishnan	Test cost reduction for SoC using a combined approach to test data compression and test scheduling.	DATE	2007	DBLP DOI BibTeX RDF
41	Chandan Giri, Dilip Kumar Reddy Tipparthi, Santanu Chattopadhyay	Genetic Algorithm Based Approach for Hierarchical SOC Test Scheduling.	ICCTA	2007	DBLP DOI BibTeX RDF
41	Jen-Yi Wuu, Tung-Chieh Chen, Yao-Wen Chang	SoC test scheduling using the B-tree based floorplanning technique.	ASP-DAC	2005	DBLP DOI BibTeX RDF
41	Sandeep Koranne	Design of reconfigurable access wrappers for embedded core based SoC test.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
40	Srivaths Ravi 0001, Niraj K. Jha	Synthesis of System-on-a-chip for Testability.	VLSI Design	2001	DBLP DOI BibTeX RDF
40	Qiang Xu 0001, Yubin Zhang, Krishnendu Chakrabarty	SOC test-architecture optimization for the testing of embedded cores and signal-integrity faults on core-external interconnects.	ACM Trans. Design Autom. Electr. Syst.	2009	DBLP DOI BibTeX RDF	Core-based system-on-chip, test scheduling, test-access mechanism (TAM), interconnect testing
40	Ozgur Sinanoglu, Alex Orailoglu	Test power reductions through computationally efficient, decoupled scan chain modifications.	IEEE Trans. Reliab.	2005	DBLP DOI BibTeX RDF
39	Sandeep Kumar Goel, Erik Jan Marinissen	Layout-Driven SOC Test Architecture Design for Test Time and Wire Length Minimization.	DATE	2003	DBLP DOI BibTeX RDF
38	Dan Zhao 0001, Yi Wang 0007	MTNet: Design of a Wireless Test Framework for Heterogeneous Nanometer Systems-on-Chip.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
38	Jin-Ho Ahn, Sungho Kang	SoC Test Scheduling Algorithm Using ACO-Based Rectangle Packing.	ICIC (2)	2006	DBLP DOI BibTeX RDF
38	Sandeep Koranne	Design of Reconfigurable Access Wrappers for Embedded Core Based SoC Test.	ISQED	2002	DBLP DOI BibTeX RDF
37	Ozgur Sinanoglu, Alex Orailoglu	Partial Core Encryption for Performance-Efficient Test of SOCs.	ICCAD	2003	DBLP DOI BibTeX RDF
37	Qiang Xu 0001, Yubin Zhang, Krishnendu Chakrabarty	SOC Test Architecture Optimization for Signal Integrity Faults on Core-External Interconnects.	DAC	2007	DBLP DOI BibTeX RDF
36	Sudarshan Bahukudumbi, Krishnendu Chakrabarty	Wafer-Level Modular Testing of Core-Based SoCs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
35	Sandeep Kumar Goel, Erik Jan Marinissen	A Test Time Reduction Algorithm for Test Architecture Design for Core-Based System Chips.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	TAM and wrapper design, test scheduling, SOC-test
35	Sandeep Kumar Goel, Erik Jan Marinissen, Anuja Sehgal, Krishnendu Chakrabarty	Testing of SoCs with Hierarchical Cores: Common Fallacies, Test Access Optimization, and Test Scheduling.	IEEE Trans. Computers	2009	DBLP DOI BibTeX RDF
35	Praveen Bhojwani, Rabi N. Mahapatra	Robust Concurrent Online Testing of Network-on-Chip-Based SoCs.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
34	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen	Test Access Mechanism Optimization, Test Scheduling, and Tester Data Volume Reduction for System-on-Chip.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	Core-based systems, test wrapper, system-on-a-chip, test scheduling, test access mechanism, testing time, rectangle packing
34	Sandeep Koranne	On Test Scheduling for Core-Based SOCs.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
34	Tomokazu Yoneda, Akiko Shuto, Hideyuki Ichihara, Tomoo Inoue, Hideo Fujiwara	TAM Design and Optimization for Transparency-Based SoC Test.	VTS	2007	DBLP DOI BibTeX RDF	TAM design, transparency, ILP, SoC test
32	Érika F. Cota, Luigi Carro, Marcelo Lubaszewski	Reusing an on-chip network for the test of core-based systems.	ACM Trans. Design Autom. Electr. Syst.	2004	DBLP DOI BibTeX RDF	TAM and wrapper design, test reuse, network-on-chip, test scheduling, SoC test, Core-based test
32	Ozgur Sinanoglu	Scan-in and Scan-out Transition Co-optimization Through Modelling Generalized Serial Transformations.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Test power reduction, Scan power reduction, Serial transformations, Scan chain modification, Design for testability, Core-based testing
32	Ozgur Sinanoglu, Alex Orailoglu	Scan Power Minimization through Stimulus and Response Transformations.	DATE	2004	DBLP DOI BibTeX RDF
31	Mounir Benabdenbi, Alain Greiner, François Pêcheux, Emmanuel Viaud, Matthieu Tuna	STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores.	DATE	2004	DBLP DOI BibTeX RDF
31	Cheng-Wen Wu	SOC Testing Methodology and Practice.	DATE	2005	DBLP DOI BibTeX RDF
31	Ozgur Sinanoglu, Alex Orailoglu	Autonomous Yet Deterministic Test of SOC Cores.	ITC	2004	DBLP DOI BibTeX RDF
31	Vikram Iyengar, Krishnendu Chakrabarty	System-on-a-chip test scheduling with precedence relationships, preemption, and power constraints.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
30	Yu Huang 0005, Sudhakar M. Reddy, Wu-Tung Cheng	Core - Clustering Based SOC Test Scheduling Optimization.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
30	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen	Wrapper/TAM co-optimization, constraint-driven test scheduling, and tester data volume reduction for SOCs.	DAC	2002	DBLP DOI BibTeX RDF
29	Sandeep Kumar Goel, Erik Jan Marinissen	On-Chip Test Infrastructure Design for Optimal Multi-Site Testing of System Chips.	DATE	2005	DBLP DOI BibTeX RDF
29	Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng	Buffer and Controller Minimisation for Time-Constrained Testing of System-On-Chip.	DFT	2003	DBLP DOI BibTeX RDF
29	Yu Huang 0005, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Omer Samman, Yahya Zaidan, Sudhakar M. Reddy	Resource Allocation and Test Scheduling for Concurrent Test of Core-Based SoC D.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
27	Vikram Iyengar, Krishnendu Chakrabarty	Precedence-Based, Preemptive, and Power-Constrained Test Scheduling for System-on-a-Chip.	VTS	2001	DBLP DOI BibTeX RDF
26	Lin Huang 0002, Feng Yuan, Qiang Xu 0001	On reliable modular testing with vulnerable test access mechanisms.	DAC	2008	DBLP DOI BibTeX RDF	modular testing, test access mechanisms, reliable test
26	Amir Nahir, Avi Ziv, Roy Emek, Tal Keidar, Nir Ronen	Scheduling-based test-case generation for verification of multimedia SoCs.	DAC	2006	DBLP DOI BibTeX RDF	test generation, system on a chip, functional verification
26	James Chin, Mehrdad Nourani	SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance.	DATE	2004	DBLP DOI BibTeX RDF
26	Alfredo Benso, Stefano Di Carlo, Paolo Prinetto, Yervant Zorian	A Hierarchical Infrastructure for SoC Test Management.	IEEE Des. Test Comput.	2003	DBLP DOI BibTeX RDF
26	Wei Zou, Sudhakar M. Reddy, Irith Pomeranz, Yu Huang 0005	SOC Test Scheduling Using Simulated Annealing.	VTS	2003	DBLP DOI BibTeX RDF
26	Hari Vijay Venkatanarayanan, Michael L. Bushnell	An Area Efficient Mixed-Signal Test Architecture for Systems-on-a-Chip.	VLSI Design	2006	DBLP DOI BibTeX RDF
26	Seongmoon Wang, Srimat T. Chakradhar, Kedarnath J. Balakrishnan	Re-configurable embedded core test protocol.	ASP-DAC	2004	DBLP DOI BibTeX RDF
26	Ozgur Sinanoglu, Tsvetomir Petrov	A non-intrusive isolation approach for soft cores.	DATE	2007	DBLP DOI BibTeX RDF
25	V. R. Devanathan, C. P. Ravikumar, V. Kamakoti 0001	Reducing SoC Test Time and Test Power in Hierarchical Scan Test : Scan Architecture and Algorithms.	VLSI Design	2007	DBLP DOI BibTeX RDF
25	K. Nikila, Rubin A. Parekhji	DFT for Test Optimisations in a Complex Mixed-Signal SOC - Case Study on TI's TNETD7300 ADSL Modem Device.	ITC	2004	DBLP DOI BibTeX RDF
24	Huan-Shan Hsu, Jing-Reng Huang, Kuo-Liang Cheng, Chih-Wea Wang, Chih-Tsun Huang, Cheng-Wen Wu, Youn-Long Lin	Test Scheduling and Test Access Architecture Optimization for System-on-Chip.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
24	Krishnendu Chakrabarty, Vikram Iyengar, Mark D. Krasniewski	Test planning for modular testing of hierarchical SOCs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
24	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen	Efficient test access mechanism optimization for system-on-chip.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
24	Paul Theo Gonciari, Bashir M. Al-Hashimi, Nicola Nicolici	Test Data Compression: The System Integrator's Perspective.	DATE	2003	DBLP DOI BibTeX RDF
24	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen	Efficient Wrapper/TAM Co-Optimization for Large SOCs.	DATE	2002	DBLP DOI BibTeX RDF
23	Sudarshan Bahukudumbi, Krishnendu Chakrabarty	Test-Length and TAM Optimization for Wafer-Level Reduced Pin-Count Testing of Core-Based SoCs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2009	DBLP DOI BibTeX RDF
23	Sudarshan Bahukudumbi, Krishnendu Chakrabarty	Test-Length Selection and TAM Optimization for Wafer-Level, Reduced Pin-Count Testing of Core-Based Digital SoCs.	VLSI Design	2007	DBLP DOI BibTeX RDF
23	Qiang Xu 0001, Nicola Nicolici	Multifrequency TAM design for hierarchical SOCs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
23	Sandeep Kumar Goel, Kuoshu Chiu, Erik Jan Marinissen, Toan Nguyen, Steven Oostdijk	Test Infrastructure Design for the Nexperia? Home Platform PNX8550 System Chip.	DATE	2004	DBLP DOI BibTeX RDF
22	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen	Test Wrapper and Test Access Mechanism Co-Optimization for System-on-Chip.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	test wrapper, integer linear programming, test access mechanism (TAM), testing time, Embedded core testing
21	Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan Marinissen	Recent Advances in Test Planning for Modular Testing of Core-Based SOCs.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF
21	Shigeki Tomishima, Hiroaki Tanizaki, Mitsutaka Niiro, Masanao Maruta, Hideto Hidaka, T. Tada, Kenji Gamo	A Variable Drivability (VD) Output Buffer for the System In a Package (SIP) and High Frequency Wafer Test.	ITC	2002	DBLP DOI BibTeX RDF
21	Martin Schrader, Roderick McConnell	SoC Design and Test Considerations.	DATE	2003	DBLP DOI BibTeX RDF
21	Vikram Iyengar, Krishnendu Chakrabarty, Mark D. Krasniewski, Gopind N. Kumar	Design and Optimization of Multi-level TAM Architectures for Hierarchical SOCs.	VTS	2003	DBLP DOI BibTeX RDF
20	Ying Zhang 0040, Li Ling, Jianhui Jiang, Jie Xiao 0003	Thermal-aware SoC Test Scheduling with Voltage/Frequency Scaling and Test Partition.	J. Electron. Test.	2018	DBLP DOI BibTeX RDF
20	Chunlei Mei, Maoxiang Yi, Zhifei Shen	Decreasing SoC Test Power Dissipation and Test Data Volume Based on Pattern Recombination.	TrustCom	2011	DBLP DOI BibTeX RDF
20	Soheil Samii, Mikko Selkälä, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng	Cycle-Accurate Test Power Modeling and Its Application to SoC Test Architecture Design and Scheduling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
20	Hong-Sik Kim, Sungho Kang 0001, Michael S. Hsiao	A New Scan Architecture for Both Low Power Testing and Test Volume Compression Under SOC Test Environment.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Keyword System on a chip, Test compression, Low power testing, Scan testing
20	Zhiyuan He 0002, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi	Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	Thermal-aware testing, Test scheduling, SoC testing
20	Jingbo Shao, Guangsheng Ma, Zhi Yang, Ruixue Zhang	Process Algebra Based SoC Test Scheduling for Test Time Minimization.	ISVLSI	2008	DBLP DOI BibTeX RDF
20	Tong-Yu Hsieh, Kuen-Jong Lee, Jian-Jhih You	Test Efficiency Analysis and Improvement of SOC Test Platforms.	ATS	2007	DBLP DOI BibTeX RDF
20	Zhiyuan He 0002, Zebo Peng, Petru Eles	Power constrained and defect-probability driven SoC test scheduling with test set partitioning.	DATE	2006	DBLP DOI BibTeX RDF
20	Zhiyuan He 0002, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi	Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving.	DFT	2006	DBLP DOI BibTeX RDF
20	Soheil Samii, Erik Larsson, Krishnendu Chakrabarty, Zebo Peng	Cycle-Accurate Test Power Modeling and its Application to SoC Test Scheduling.	ITC	2006	DBLP DOI BibTeX RDF
20	Anders Larsson, Erik Larsson, Petru Eles, Zebo Peng	SOC Test Scheduling with Test Set Sharing and Broadcasting.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
20	Chakunta Venkata Guru Rao, Dipanwita Roy Chowdhury	A new design-for-test technique for reducing SOC test time.	ASP-DAC	2003	DBLP DOI BibTeX RDF
20	Vikram Iyengar, Anshuman Chandra	A Uni.ed SOC Test Approach Based on Test Data Compression and TAM Design.	DFT	2003	DBLP DOI BibTeX RDF
20	Yu Huang 0005, Wu-Tung Cheng, Chien-Chung Tsai, Nilanjan Mukherjee 0001, Sudhakar M. Reddy	Static Pin Mapping and SOC Test Scheduling for Cores with Multiple Test Sets.	ISQED	2003	DBLP DOI BibTeX RDF
20	Mohammad Hosseinabady, Shervin Sharifi, Fabrizio Lombardi, Zainalabedin Navabi	A Selective Trigger Scan Architecture for VLSI Testing.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Delay Testing, Test Compression, Test Application Time, Scan Test, Test Data Volume, Test Power
20	Xiaoxia Wu, Yibo Chen, Krishnendu Chakrabarty, Yuan Xie 0001	Test-access mechanism optimization for core-based three-dimensional SOCs.	ICCD	2008	DBLP DOI BibTeX RDF
20	Rani S. Ghaida, Payman Zarkesh-Ha	Estimation of Electromigration-Aggravating Narrow Interconnects Using a Layout Sensitivity Model.	DFT	2007	DBLP DOI BibTeX RDF
20	Anuja Sehgal, Sandeep Kumar Goel, Erik Jan Marinissen, Krishnendu Chakrabarty	Hierarchy-aware and area-efficient test infrastructure design for core-based system chips.	DATE	2006	DBLP DOI BibTeX RDF
20	Masahide Miyazaki, Toshinori Hosokawa, Hiroshi Date, Michiaki Muraoka, Hideo Fujiwara	A DFT Selection Method for Reducing Test Application Time of System-on-Chips.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	wrapper, design for test, test scheduling, test access mechanism
20	Shervin Sharifi, Mohammad Hosseinabady, Pedram A. Riahi, Zainalabedin Navabi	Reducing Test Power, Time and Data Volume in SoC Testing Using Selective Trigger Scan Architecture.	DFT	2003	DBLP DOI BibTeX RDF
19	Jih-Jeen Chen, Chia-Kai Yang, Kuen-Jong Lee	Test pattern generation and clock disabling for simultaneous test time and power reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
19	Sandeep Koranne	A Novel Reconfigurable Wrapper for Testing of Embedded Core-Based SOCs and its Associated Scheduling Algorithm.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	embedded core based test scheduling, reconfigurable wrapper, parallel scheduling of malleable tasks, system-on-chip test, VLSI test
18	Yinhe Han 0001, Huawei Li 0001, Xiaowei Li 0001, Anshuman Chandra	Response compaction for system-on-a-chip based on advanced convolutional codes.	Sci. China Ser. F Inf. Sci.	2006	DBLP DOI BibTeX RDF	X bits masking, aliasing, convolutional code, SOC test, response compaction
18	Alexandre M. Amory, Érika F. Cota, Marcelo Lubaszewski, Fernando Gehm Moraes	Reducing test time with processor reuse in network-on-chip based systems.	SBCCI	2004	DBLP DOI BibTeX RDF	NoC testing, computer-aided test (CAT), software-based test, network-on-chip, SoC test, core-based test
18	Krishna Sekar, Sujit Dey	LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	LI-BIST, crosstalk test, BIST, SoC test, low-power test