Search results for "STT-MRAM"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
170	Jing Li 0073, Charles Augustine, Sayeef S. Salahuddin, Kaushik Roy 0001	Modeling of failure probability and statistical design of spin-torque transfer magnetic random access memory (STT MRAM) array for yield enhancement.	DAC	2008	DBLP DOI BibTeX RDF	STT MRAM, yield
152	Xiaochen Guo, Engin Ipek, Tolga Soyata	Resistive computation: avoiding the power wall with low-leakage, STT-MRAM based computing.	ISCA	2010	DBLP DOI BibTeX RDF	STT-MRAM, power-efficiency
152	Wei Xu 0021, Yiran Chen 0001, Xiaobin Wang, Tong Zhang 0002	Improving STT MRAM storage density through smaller-than-worst-case transistor sizing.	DAC	2009	DBLP DOI BibTeX RDF	STT MRAM, defect tolerance, transistor sizing
105	Yoshiaki Asao, Masayoshi Iwayama, Kenji Tsuchida, Akihiro Nitayama, Hiroaki Yoda, Hisanori Aikawa, Sumio Ikegawa, Tatsuya Kishi	A Statistical Model for Assessing the Fault Tolerance of Variable Switching Currents for a 1Gb Spin Transfer Torque Magnetoresistive Random Access Memory.	DFT	2008	DBLP DOI BibTeX RDF
66	Jing Li 0073, Patrick Ndai, Ashish Goel, Haixin Liu, Kaushik Roy 0001	An alternate design paradigm for robust spin-torque transfer magnetic RAM (STT MRAM) from circuit/architecture perspective.	ASP-DAC	2009	DBLP DOI BibTeX RDF
63	Mounia Kharbouche-Harrari	Hybridation CMOS/STT-MRAM des circuits intégrés pour la sécurité matérielle de l'internet des Objets. (CMOS/STT-MRAM hybridization of integrated circuits for the hardware security of the Internet of Things).		2019	RDF
47	Haris Suhail, Jiyue Yang, Haoran He, Kang L. Wang, Sudhakar Pamarti	Analytical Array-Level Comparison of Read/Write Performance Between Voltage Controlled-MRAM and STT-MRAM.	MWSCAS	2023	DBLP DOI BibTeX RDF
47	Jisu Kim, Kyungho Ryu, Seung-Hyuk Kang, Seong-Ook Jung	A Novel Sensing Circuit for Deep Submicron Spin Transfer Torque MRAM (STT-MRAM).	IEEE Trans. Very Large Scale Integr. Syst.	2012	DBLP DOI BibTeX RDF
47	Thi-Nhan Pham, Quang-Kien Trinh, Ik-Joon Chang, Massimo Alioto	STT-BNN: A Novel STT-MRAM In-Memory Computing Macro for Binary Neural Networks.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2022	DBLP DOI BibTeX RDF
47	Van-Tinh Nguyen, Quang-Kien Trinh, Renyuan Zhang, Yasuhiko Nakashima	STT-BSNN: An In-Memory Deep Binary Spiking Neural Network Based on STT-MRAM.	IEEE Access	2021	DBLP DOI BibTeX RDF
47	Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Fazal Hameed, Mehdi Baradaran Tahoori	VAET-STT: Variation Aware STT-MRAM Analysis and Design Space Exploration Tool.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2018	DBLP DOI BibTeX RDF
47	Sarath Mohanachandran Nair, Rajendra Bishnoi, Mohammad Saber Golanbari, Fabian Oboril, Mehdi Baradaran Tahoori	VAET-STT: A variation aware estimator tool for STT-MRAM based memories.	DATE	2017	DBLP DOI BibTeX RDF
31	De-Qi You, Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang	An 8b-Precision 8-Mb STT-MRAM Near-Memory-Compute Macro Using Weight-Feature and Input-Sparsity Aware Schemes for Energy-Efficient Edge AI Devices.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
31	Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono	A 22-nm 32-Mb Embedded STT-MRAM Macro Achieving 5.9-ns Random Read Access and 7.4-MB/s Write Throughput at up to 150 °C.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
31	Belal Jahannia, Seyed Ali Ghasemi, Hamed Farbeh	Multi-Retention STT-MRAM Architectures for IoT: Evaluating the Impact of Retention Levels and Memory Mapping Schemes.	IEEE Access	2024	DBLP DOI BibTeX RDF
31	Alaba Yusuf, Tosiron Adegbija, Dhruv Gajaria	Domain-Specific STT-MRAM-Based In-Memory Computing: A Survey.	IEEE Access	2024	DBLP DOI BibTeX RDF
31	Sureum Choi, Daejin Han, Chanyeong Choi, Yeongkyo Seo	Layout-Aware Area Optimization of Transposable STT-MRAM for a Processing-In-Memory System.	IEEE Trans. Very Large Scale Integr. Syst.	2024	DBLP DOI BibTeX RDF
31	Yongliang Zhou, Zixuan Zhou, Yiming Wei, Zhen Yang, Xiao Lin, Chenghu Dai, Licai Hao, Chunyu Peng, Hao Cai, Xiulong Wu	A CFMB STT-MRAM-Based Computing-in-Memory Proposal With Cascade Computing Unit for Edge AI Devices.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
31	Belal Jahannia, Seyed Ali Ghasemi, Hamed Farbeh	An Energy Efficient Multi-Retention STT-MRAM Memory Architecture for IoT Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
31	Chao Wang 0094, Zhaohao Wang, Zhongkui Zhang, Youguang Zhang, Weisheng Zhao	Area and Energy Efficient Short-Circuit-Logic-Based STT-MRAM Crossbar Array for Binary Neural Networks.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
31	Ku-Feng Lin, Hiroki Noguchi, Yi-Chun Shih, Perng-Fei Yuh, Yuan-Jen Lee, Tung-Cheng Chang, Sheng-Po Huang, Yu-Fan Lin, Chun-Ying Lee, Yen-Hsiang Huang, Jui-Che Tsai, Saman Adham, Peter Noel, Ramin Yazdi, Marat Gershoig, YangJae Shin, Vineet Joshi, Ted Wong, Meng-Ru Jiang, J. J. Wu, Chun-Tai Cheng, Yu-Jen Wang, Harry Chuang, Yu-Der Chih, Yih Wang, Tsung-Yung Jonathan Chang	15.9 A 16nm 16Mb Embedded STT-MRAM with a 20ns Write Time, a 1012 Write Endurance and Integrated Margin-Expansion Schemes.	ISSCC	2024	DBLP DOI BibTeX RDF
31	Tomoya Ogawa, Ken Matsubara, Yasuhiko Taito, Tomoya Saito, Masayuki Izuna, Koichi Takeda, Yoshinobu Kaneda, Takahiro Shimoi, Hidenori Mitani, Takashi Ito, Takashi Kono	15.8 A 22nm 10.8Mb Embedded STT-MRAM Macro Achieving over 200MHz Random-Read Access and a 10.4MB/s Write Throughput with an In-Field Programmable 0.3Mb MTJ-OTP for High-End MCUs.	ISSCC	2024	DBLP DOI BibTeX RDF
31	Tatiana Moposita, Esteban Garzón, Raffaele De Rose, Felice Crupi, Andrei Vladimirescu, Lionel Trojman, Marco Lanuzza	SIMPLY+: A Reliable STT-MRAM-Based Smart Material Implication Architecture for In-Memory Computing.	IEEE Access	2023	DBLP DOI BibTeX RDF
31	Tao Li 0005, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh	Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator.	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
31	Tao Li 0005, Yitao Ma, Ko Yoshikawa, Tetsuo Endoh	Corrections to "Hybrid Signed Convolution Module With Unsigned Divide-and-Conquer Multiplier for Energy-Efficient STT-MRAM-Based AI Accelerator".	IEEE Trans. Very Large Scale Integr. Syst.	2023	DBLP DOI BibTeX RDF
31	Arash Salahvarzi, Mohsen Khosroanjam, Amir Mahdi Hosseini Monazzah, Hakem Beitollahi, Ümit Y. Ogras, Mahdi Fazeli	WiSE: When Learning Assists Resolving STT-MRAM Efficiency Challenges.	IEEE Trans. Emerg. Top. Comput.	2023	DBLP DOI BibTeX RDF
31	An Yang, Zhilin Jiang, Zheng Huang, Zitong Zhang, Yanfeng Jiang	Double-Ended Superposition Anti-Noise Resistance Monitoring Write Termination Scheme for Reliable Write Operation in STT-MRAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
31	Byoungchan Oh, Nilmini Abeyratne, Nam Sung Kim, Jeongseob Ahn, Ronald G. Dreslinski, Trevor N. Mudge	Rethinking DRAM's Page Mode With STT-MRAM.	IEEE Trans. Computers	2023	DBLP DOI BibTeX RDF
31	Wei Zhao 0034, Dan Feng 0001, Wei Tong 0001, Jingning Liu, Zhangyu Chen, Bing Wu 0001, Chengning Wang	APPcache+: An STT-MRAM-Based Approximate Cache System With Low Power and Long Lifetime.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
31	Wei Zhao 0034, Jie Xu 0013, Xueliang Wei, Bing Wu 0001, Chengning Wang, Weilin Zhu, Wei Tong 0001, Dan Feng 0001, Jingning Liu	A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
31	Yueting Li, Wang Kang 0001, Kunyu Zhou, Keni Qiu, Weisheng Zhao	Experimental Demonstration of STT-MRAM-based Nonvolatile Instantly On/Off System for IoT Applications: Case Studies.	ACM Trans. Embed. Comput. Syst.	2023	DBLP DOI BibTeX RDF
31	Sourjya Roy, Cheng Wang, Anand Raghunathan	Evaluation of STT-MRAM as a Scratchpad for Training in ML Accelerators.	CoRR	2023	DBLP DOI BibTeX RDF
31	Hao Cai, Yaoru Hou, Mengdi Zhang, Bo Liu 0019, Lirida Alves de Barros Naviner	Dependable STT-MRAM With Emerging Approximation and Speculation Paradigms.	IEEE Des. Test	2023	DBLP DOI BibTeX RDF
31	Fernando García-Redondo, S. Rao, M. Gupta, Manu Perumkunnil, Y. Xiang, D. Abdi, Simon Van Beek, S. Couet, Marie Garcia Bardon	STT-MRAM Stochastic and Defects-aware DTCO for Last Level Cache at Advanced Process Nodes.	ESSDERC	2023	DBLP DOI BibTeX RDF
31	J. Tan, J. H. Lim, Jae Hyun Kwon, Vinayak Bharat Naik, Nagarajan Raghavan, Kin Leong Pey	Backhopping-based STT-MRAM Poisson Spiking Neuron for Neuromorphic Computation.	IRPS	2023	DBLP DOI BibTeX RDF
31	Hideo Sato, H. M. Shin, H. Jung, S. W. Lee, H. Bae, H. Kwon, K. H. Ryu, W. C. Lim, Y. S. Han, J. H. Jeong, J. M. Lee, D. S. Kim, K. Lee, J. H. Lee, J. H. Park, Y. J. Song, Y. Ji, B. I. Seo, J. W. Kim, H. H. Kim	Comprehensive study on prediction of endurance properties from breakdown voltage in high-reliable STT-MRAM.	IRPS	2023	DBLP DOI BibTeX RDF
31	Jinkai Wang, Zhengkun Gu, Hongyu Wang, Zuolei Hao, Bojun Zhang, Weisheng Zhao, Yue Zhang 0010	TAM: A Computing in Memory based on Tandem Array within STT-MRAM for Energy-Efficient Analog MAC Operation.	DATE	2023	DBLP DOI BibTeX RDF
31	Linjun Jiang, Sifan Sun, Jinming Ge, He Zhang 0011, Wang Kang 0001	An In-Memory-Computing STT-MRAM Macro with Analog ReLU and Pooling Layers for Ultra-High Efficient Neural Network.	NVMSA	2023	DBLP DOI BibTeX RDF
31	Yueting Li, He Zhang, Xueyan Wang, Hao Cai, Yundong Zhang, Shuqin Lv, Renguang Liu, Weisheng Zhao	Toward Energy-Efficient Sparse Matrix-Vector Multiplication with near STT-MRAM Computing Architecture.	ASP-DAC	2023	DBLP DOI BibTeX RDF
31	Santiago S. Pérez, Alessandro Bedoya, Luis-Miguel Prócel, Ramiro Taco	Performance Benchmarking of FinFET- and TFET-Based STT-MRAM Bitcells Operating at Ultra-Low Voltages.	LASCAS	2023	DBLP DOI BibTeX RDF
31	Esteban Garzón, Leonid Yavits, Adam Teman, Marco Lanuzza	STT-MRAM Technology For Energy-Efficient Cryogenic Memory Applications.	LASCAS	2023	DBLP DOI BibTeX RDF
31	Xinshu Xie, Jiongzhe Su, Hao Zhang, Hao Cai	A FinFET Integrated STT-MRAM with Triple Balanced Access Strategy.	ICTA	2023	DBLP DOI BibTeX RDF
31	Jeongdong Choe	Recent Technology Insights on STT-MRAM: Structure, Materials, and Process Integration.	IMW	2023	DBLP DOI BibTeX RDF
31	Yen-Cheng Chiu, Win-San Khwa, Chung-Yuan Li, Fang-Ling Hsieh, Yu-An Chien, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, De-Qi You, Fang-Yi Chen, Andrew Lee, Chung-Chuan Lo, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang	A 22nm 8Mb STT-MRAM Near-Memory-Computing Macro with 8b-Precision and 46.4-160.1TOPS/W for Edge-AI Devices.	ISSCC	2023	DBLP DOI BibTeX RDF
31	Po-Hao Lee, Chia-Fu Lee, Yi-Chun Shih, Hon-Jarn Lin, Yen-An Chang, Cheng-Han Lu, Yu-Lin Chen, Chieh-Pu Lo, Chung-Chieh Chen, Cheng-Hsiung Kuo, Tan-Li Chou, Chia-Yu Wang, J. J. Wu, Roger Wang, Harry Chuang, Yih Wang, Yu-Der Chih, Tsung-Yung Jonathan Chang	A 16nm 32Mb Embedded STT-MRAM with a 6ns Read-Access Time, a 1M-Cycle Write Endurance, 20-Year Retention at 150°C and MTJ-OTP Solutions for Magnetic Immunity.	ISSCC	2023	DBLP DOI BibTeX RDF
31	Hao Cai, Zhong-Jian Bian, Yaoru Hou, Yongliang Zhou, Jia-Le Cui, Yanan Guo 0004, Xiaoyun Tian, Bo Liu 0019, Xin Si, Zhen Wang, Jun Yang 0006, Weiwei Shan	A 28nm 2Mb STT-MRAM Computing-in-Memory Macro with a Refined Bit-Cell and 22.4 - 41.5TOPS/W for AI Inference.	ISSCC	2023	DBLP DOI BibTeX RDF
31	Lu Lu 0013, Aarthy Mani, Anh Tuan Do	A 129.83 TOPS/W Area Efficient Digital SOT/STT MRAM-Based Computing-In-Memory for Advanced Edge AI Chips.	ISCAS	2023	DBLP DOI BibTeX RDF
31	Yen-Cheng Chiu, Tung-Cheng Chang, Chun-Ying Lee, Je-Min Hung, Kuang-Tang Chang, Cheng-Xin Xue, Ssu-Yen Wu, Hui-Yao Kao, Peng Chen, Hsiao-Yu Huang, Shih-Hsih Teng, Chieh-Pu Lo, Yi-Chun Shih, Yu-Der Chih, Tsung-Yung Jonathan Chang, Yier Jin, Meng-Fan Chang	A 22-nm 1-Mb 1024-b Read Data-Protected STT-MRAM Macro With Near-Memory Shift-and-Rotate Functionality and 42.6-GB/s Read Bandwidth for Security-Aware Mobile Device.	IEEE J. Solid State Circuits	2022	DBLP DOI BibTeX RDF
31	Yongjun Kim, Yuze Chen, Yongho Lee, Limei Peng, Seokin Hong	Proactively Invalidating Dead Blocks to Enable Fast Writes in STT-MRAM Caches.	IEEE Access	2022	DBLP DOI BibTeX RDF
31	Nooshin Mahdavi, Farhad Razaghian, Hamed Farbeh	Data block manipulation for error rate reduction in STT-MRAM based main memory.	J. Supercomput.	2022	DBLP DOI BibTeX RDF
31	Hao Cai, Yanan Guo 0004, Bo Liu 0019, Mingyang Zhou 0002, Juntong Chen, Xinning Liu, Jun Yang 0006	Proposal of Analog In-Memory Computing With Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell.	IEEE Trans. Circuits Syst. I Regul. Pap.	2022	DBLP DOI BibTeX RDF
31	Yupeng Hu, Linjun Wu, Zhuojun Chen, Yun Huang, Xiaolin Xu, Keqin Li 0001, Jiliang Zhang 0002	STT-MRAM-Based Reliable Weak PUF.	IEEE Trans. Computers	2022	DBLP DOI BibTeX RDF
31	Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi 0001	3RSeT: Read Disturbance Rate Reduction in STT-MRAM Caches by Selective Tag Comparison.	IEEE Trans. Computers	2022	DBLP DOI BibTeX RDF
31	Mostafa Hadizadeh, Elham Cheshmikhani, Maysam Rahmanpour, Onur Mutlu, Hossein Asadi 0001	CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers.	IEEE Trans. Parallel Distributed Syst.	2022	DBLP DOI BibTeX RDF
31	Nooshin Mahdavi, Farhad Razaghian, Hamed Farbeh	An Architectural-Level Reliability Improvement Scheme in STT-MRAM Main Memory.	Microprocess. Microsystems	2022	DBLP DOI BibTeX RDF
31	Mahta Mayahinia, Mehdi B. Tahoori, Manu Perumkunnil Komalan, Houman Zahedmanesh, Kristof Croes, Tommaso Marinelli, José Ignacio Gómez Pérez, Timon Evenblij, Gouri Sankar Kar, Francky Catthoor	Time-Dependent Electromigration Modeling for Workload-Aware Design-Space Exploration in STT-MRAM.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
31	Jeongbin Kim 0001, Yongwoon Song, Kyungseon Cho, Hyukjun Lee, Hongil Yoon, Eui-Young Chung	STT-MRAM-Based Multicontext FPGA for Multithreading Computing Environment.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
31	Saravanan Sethuraman, Venkata Kalyan Tavva, M. B. Srinivas	Techniques to Improve Write and Retention Reliability of STT-MRAM Memory Subsystem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
31	Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui	MFA-MTJ Model: Magnetic-Field-Aware Compact Model of pMTJ for Robust STT-MRAM Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2022	DBLP DOI BibTeX RDF
31	Kazi Asifuzzaman, Rommel Sánchez Verdejo, Petar Radojkovic	Performance and Power Estimation of STT-MRAM Main Memory with Reliable System-level Simulation.	ACM Trans. Embed. Comput. Syst.	2022	DBLP DOI BibTeX RDF
31	Tommaso Marinelli, José Ignacio Gómez Pérez, Christian Tenllado, Manu Komalan, Mohit Gupta 0004, Francky Catthoor	Microarchitectural Exploration of STT-MRAM Last-level Cache Parameters for Energy-efficient Devices.	ACM Trans. Embed. Comput. Syst.	2022	DBLP DOI BibTeX RDF
31	Xinpeng Jiang, Junlin Bao, Li Zhang, Lei Bai 0012	A novel dual-reference sensing scheme for computing in memory within STT-MRAM.	Microelectron. J.	2022	DBLP DOI BibTeX RDF
31	Elham Cheshmikhani, Hamed Farbeh, Hossein Asadi 0001	A System-Level Framework for Analytical and Empirical Reliability Exploration of STT-MRAM Caches.	CoRR	2022	DBLP BibTeX RDF
31	Mostafa Hadizadeh, Elham Cheshmikhani, Maysam Rahmanpour, Onur Mutlu, Hossein Asadi 0001	CoPA: Cold Page Awakening to Overcome Retention Failures in STT-MRAM Based I/O Buffers.	CoRR	2022	DBLP BibTeX RDF
31	Elham Cheshmikhani, Hamed Farbeh, Seyed Ghassem Miremadi, Hossein Asadi 0001	TA-LRW: A Replacement Policy for Error Rate Reduction in STT-MRAM Caches.	CoRR	2022	DBLP BibTeX RDF
31	Chenji Liu, Lan Chen, Xiaoran Hao, Mao Ni	Optimized fast data migration for hybrid DRAM/STT-MRAM main memory.	IEICE Electron. Express	2022	DBLP DOI BibTeX RDF
31	Yueting Li, Bingluo Zhao, Xinyi Xu, Yundong Zhang, Jun Wang, Weisheng Zhao	Work-in-Progress: Toward Energy-efficient Near STT-MRAM Processing Architecture for Neural Networks.	CODES+ISSS	2022	DBLP DOI BibTeX RDF
31	Wu Yang, Amit Degada, Himanshu Thapliyal	Adiabatic Logic-based STT-MRAM Design for IoT.	ISVLSI	2022	DBLP DOI BibTeX RDF
31	Vinayak Bharat Naik, J. H. Lim, Kazutaka Yamane, J. Kwon, Behin-Aein B., N. L. Chung, S. K 0001, R. Chao, C. Chiang, Y. Huang, L. Pu, Yuichi Otani, Suk Hee Jang, Nivetha Balasankaran, Wah-Peng Neo, T. Ling, Jia Wen Ting, Hongsik Yoon, Johannes Müller, Bert Pfefferling, Oliver Kallensee, Thomas Merbeth, Chim Seng Seet, J. Wong, Y. S. You, Steven Soss, T. H. Chan, S. Y. Siah	Extended MTJ TDDB Model, and Improved STT-MRAM Reliability With Reduced Circuit and Process Variabilities.	IRPS	2022	DBLP DOI BibTeX RDF
31	Moritz Fieback, Christopher Münch, Anteneh Gebregiorgis, Guilherme Cardoso Medeiros, Mottaqiallah Taouil, Said Hamdioui, Mehdi B. Tahoori	PVT Analysis for RRAM and STT-MRAM-based Logic Computation-in-Memory.	ETS	2022	DBLP DOI BibTeX RDF
31	Ariana Musello, Santiago S. Pérez, Marco Villegas, Luis-Miguel Prócel, Ramiro Taco, Lionel Trojman	Energy-Efficient FinFET-Versus TFET-Based STT-MRAM Bitcells.	LASCAS	2022	DBLP DOI BibTeX RDF
31	Nathan Roussel, Olivier Potin, Gregory di Pendina, Jean-Max Dutertre, Jean-Baptiste Rigaud	CMOS/STT-MRAM Based Ascon LWC: a Power Efficient Hardware Implementation.	ICECS 2022	2022	DBLP DOI BibTeX RDF
31	Xiaoyun Tian, Zhong-Jian Bian, Hao Cai	Towards Near LLC Speed STT-MRAM Sensing Using Reconfigurable Clock Trimming.	ICTA	2022	DBLP DOI BibTeX RDF
31	Abhairaj Singh, Mahdi Zahedi, Taha Shahroodi, Mohit Gupta 0004, Anteneh Gebregiorgis, Manu Komalan, Rajiv V. Joshi, Francky Catthoor, Rajendra Bishnoi, Said Hamdioui	CIM-based Robust Logic Accelerator using 28 nm STT-MRAM Characterization Chip Tape-out.	AICAS	2022	DBLP DOI BibTeX RDF
31	Takahiro Shimoi, Ken Matsubara, Tomoya Saito, Tomoya Ogawa, Yasuhiko Taito, Yoshinobu Kaneda, Masayuki Izuna, Koichi Takeda, Hidenori Mitani, Takashi Ito, Takashi Kono	A 22nm 32Mb Embedded STT-MRAM Macro Achieving 5.9ns Random Read Access and 5.8MB/s Write Throughput at up to Tj of 150 °C.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
31	Z. Wei, W. Kim, Z. Wang, L. Hu, D. Jung, J. Zhang, Y. Huai	Accurate and Fast STT-MRAM Endurance Evaluation Using a Novel Metric for Asymmetric Bipolar Stress and Deep Learning.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
31	Kai Liu, Bi Wu, Haonan Zhu, Weiqiang Liu 0001	High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features.	NANOARCH	2022	DBLP DOI BibTeX RDF
31	Nishtha S. Gaul, Akhilesh Jaiswal 0002, Hongsik Yoon, Taeyoung Lee, Kazutaka Yamane, Joseph Versaggi, Rick Carter, Bipul C. Paul	A Physics based MTJ Compact Model for State-of-the-Art and Emerging STT-MRAM Failure Analysis and Yield Enhancement.	IMW	2022	DBLP DOI BibTeX RDF
31	Syed M. Alam, Dimitri Houssameddine, F. Neumeyer, I. Rahman, M. DeHerrera, S. Ikegawa, P. Sanchez, X. Zhang, Y. Wang, J. Williams, Dietmar Gogl, H. Xu, M. Farook, D. Aceves, H. K. Lee, Fred B. Mancoff, M. Chou, CH. Tan, B. Huang, S. Mukherjee, M. Lu, A. Shah, K. Nagel, Y. Kim, S. Aggarwal	Persistent xSPI STT-MRAM with up to 400MB/s Read and Write Throughput.	IMW	2022	DBLP DOI BibTeX RDF
31	Johannes Müller, Aleksandra Titova, Hongsik Yoon, Thomas Merbeth, Martin Weisheit, Georg Wolf, Sanjeeb Bharali, Bert Pfefferling, Yuichi Otani, Tetyana Shapoval, Alberto Cagliani, Ferenc Vajda, Pedram Sadeghi, Christiana Villas-Boas Grimm, Frank Krause, Ines Altendorf, Gabriele Congedo, Robert Binder, Joachim Metzger, Alexander Lajn, Markus Langner, Young Seon You, Oliver Kallensee, Vinayak Bharat Naik, Kazutaka Yamane, Steven Soss	From Emergence to Prevalence: 22FDX® Embedded STT-MRAM.	IMW	2022	DBLP DOI BibTeX RDF
31	Yen-Cheng Chiu, Chia-Sheng Yang, Shih-Hsih Teng, Hsiao-Yu Huang, Fu-Chun Chang, Yuan Wu 0009, Yu-An Chien, Fang-Ling Hsieh, Chung-Yuan Li, Guan-Yi Lin, Po-Jung Chen, Tsen-Hsiang Pan, Chung-Chuan Lo, Win-San Khwa, Ren-Shuo Liu, Chih-Cheng Hsieh, Kea-Tiong Tang, Chieh-Pu Lo, Yu-Der Chih, Tsung-Yung Jonathan Chang, Meng-Fan Chang	A 22nm 4Mb STT-MRAM Data-Encrypted Near-Memory Computation Macro with a 192GB/s Read-and-Decryption Bandwidth and 25.1-55.1TOPS/W 8b MAC for AI Operations.	ISSCC	2022	DBLP DOI BibTeX RDF
31	Chang Xue, Yihan Zhang 0002, Peiyu Chen, Mingwei Zhu, Tianqiao Wu, Meng Wu, Yandong He, Le Ye	Reliability-Improved Read Circuit and Self-Terminating Write Circuit for STT-MRAM in 16 nm FinFET.	ISCAS	2022	DBLP DOI BibTeX RDF
31	Dongsu Kim, Jongsun Park 0001	Distributed Accumulation based Energy Efficient STT-MRAM based Digital PIM Architecture.	ISOCC	2022	DBLP DOI BibTeX RDF
31	Yeseul Kim, Jongsun Park 0001	Energy-Efficient STT-MRAM based Digital PIM supporting Vertical Computations Using Sense Amplifier.	ISOCC	2022	DBLP DOI BibTeX RDF
31	Dong-Kil Yun, Jung-Hoon Chun	STT-MRAM Read and Write Circuit for High Reliability and Power Efficiency.	ISOCC	2022	DBLP DOI BibTeX RDF
31	Christopher Münch, Jongsin Yun, Martin Keim, Mehdi B. Tahoori	MBIST-based Trim-Search Test Time Reduction for STT-MRAM.	VTS	2022	DBLP DOI BibTeX RDF
31	Kaniz Mishty, Mehdi Sadi	Designing Efficient and High-Performance AI Accelerators With Customized STT-MRAM.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
31	Jinbo Chen, Chengcheng Lu, Jiacheng Ni, Xiaochen Guo, Patrick Girard 0001, Yuanqing Cheng	DOVA PRO: A Dynamic Overwriting Voltage Adjustment Technique for STT-MRAM L1 Cache Considering Dielectric Breakdown Effect.	IEEE Trans. Very Large Scale Integr. Syst.	2021	DBLP DOI BibTeX RDF
31	Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Guilherme Cardoso Medeiros, Moritz Fieback, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui	Defect and Fault Modeling Framework for STT-MRAM Testing.	IEEE Trans. Emerg. Top. Comput.	2021	DBLP DOI BibTeX RDF
31	Taehui Na, Seung-Hyuk Kang, Seong-Ook Jung	STT-MRAM Sensing: A Review.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
31	Hao Cai, Juntong Chen, Yongliang Zhou, Weisheng Zhao	Toward Energy-Efficient STT-MRAM Design With Multi-Modes Reconfiguration.	IEEE Trans. Circuits Syst. II Express Briefs	2021	DBLP DOI BibTeX RDF
31	Arash Salahvarzi, Amir Mahdi Hosseini Monazzah, Mahdi Fazeli, Kevin Skadron	NOSTalgy: Near-Optimum Run-Time STT-MRAM Quality-Energy Knob Management for Approximate Computing Applications.	IEEE Trans. Computers	2021	DBLP DOI BibTeX RDF
31	Mahdi Talebi, Arash Salahvarzi, Amir Mahdi Hosseini Monazzah, Kevin Skadron, Mahdi Fazeli	ROCKY: A Robust Hybrid On-Chip Memory Kit for the Processors With STT-MRAM Cache Technology.	IEEE Trans. Computers	2021	DBLP DOI BibTeX RDF
31	Kaniz Mishty, Mehdi Sadi	Designing Efficient and High-performance AI Accelerators with Customized STT-MRAM.	CoRR	2021	DBLP BibTeX RDF
31	Hao Cai, Yanan Guo 0004, Bo Liu 0019, Mingyang Zhou 0002, Juntong Chen, Xinning Liu, Jun Yang 0006	Proposal of Analog In-Memory Computing with Magnified Tunnel Magnetoresistance Ratio and Universal STT-MRAM Cell.	CoRR	2021	DBLP BibTeX RDF
31	Peng Zhou, Julie A. Smith, Laura Deremo, Stephen K. Heinrich-Barna, Joseph S. Friedman	Synchronous Unsupervised STDP Learning with Stochastic STT-MRAM Switching.	CoRR	2021	DBLP BibTeX RDF
31	Simon Van Beek, Siddharth Rao, Shreya Kundu, Woojin Kim, Barry J. O'Sullivan, Stefan Cosemans, Farrukh Yasin, Robert Carpenter, Sebastien Couet, Shamin H. Sharifi, Nico Jossart, Davide Crotti, Gouri Sankar Kar	Edge-induced reliability & performance degradation in STT-MRAM: an etch engineering solution.	IRPS	2021	DBLP DOI BibTeX RDF
31	Shinhee Han, Junghyuk Lee, Kiseok Suh, Kyungtae Nam, Daeeun Jeong, Sechung Oh, Sohee Hwang, Yongsung Ji, Kilho Lee, Kangho Lee, Yoonjong Song, Yeongki Hong, Gitae Jeong	Reliability of STT-MRAM for various embedded applications.	IRPS	2021	DBLP DOI BibTeX RDF
31	Wei Zhao 0034, Wei Tong 0001, Dan Feng 0001, Jingning Liu, Zhangyu Chen, Jie Xu 0013, Bing Wu 0001, Chengning Wang, Bo Liu	Improving the energy efficiency of STT-MRAM based approximate cache.	DATE	2021	DBLP DOI BibTeX RDF
31	Lizhou Wu, Siddharth Rao, Mottaqiallah Taouil, Erik Jan Marinissen, Gouri Sankar Kar, Said Hamdioui	Characterization and Fault Modeling of Intermediate State Defects in STT-MRAM.	DATE	2021	DBLP DOI BibTeX RDF