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Publication years (Num. hits)
2009-2011 (16) 2012-2013 (38) 2014 (24) 2015 (19) 2016 (45) 2017 (23) 2018 (24) 2019 (19) 2020 (15) 2021-2022 (16) 2023-2024 (7)
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article(104) inproceedings(142)
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Found 246 publication records. Showing 246 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
123Yiran Chen 0001, Hai Li 0001, Xiaobin Wang, Wenzhong Zhu, Wei Xu 0021, Tong Zhang 0002 Combined magnetic- and circuit-level enhancements for the nondestructive self-reference scheme of STT-RAM. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF STT-RAM, emerging memory, spintronic
97Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili An energy efficient cache design using spin torque transfer (STT) RAM. Search on Bibsonomy ISLPED The full citation details ... 2010 DBLP  DOI  BibTeX  RDF (STT)RAM, memory technologies, cache design
45Yuanhui Ni, Weiwen Chen, Lei Wang, Keni Qiu 面向MLC STT-RAM的寄存器分配策略优化研究 (Optimization of Register Allocation Strategy for MLC STT-RAM). Search on Bibsonomy 计算机科学 The full citation details ... 2018 DBLP  BibTeX  RDF
43Hyunwoo Park, Hyun So, Hyukjun Lee Application specific cache design using STT-RAM based block-RAM for FPGA-based soft processors. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
43Wujie Wen, Yaojun Zhang, Yiran Chen 0001, Yu Wang 0002, Yuan Xie 0001 PS3-RAM: A Fast Portable and Scalable Statistical STT-RAM Reliability/Energy Analysis Method. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
43Tiefei Zhang, Tianzhou Chen, Jianzhong Wu, Youtian Qu A Selective Read-before-Write Scheme for Energy-Aware Spin Torque Transfer RAM (STT-RAM) Cache Design. Search on Bibsonomy J. Circuits Syst. Comput. The full citation details ... 2013 DBLP  DOI  BibTeX  RDF
43Wujie Wen, Yaojun Zhang, Yiran Chen 0001, Yu Wang 0002, Yuan Xie 0001 PS3-RAM: a fast portable and scalable statistical STT-RAM reliability analysis method. Search on Bibsonomy DAC The full citation details ... 2012 DBLP  DOI  BibTeX  RDF
43Wei Xu 0021, Hongbin Sun 0001, Xiaobin Wang, Yiran Chen 0001, Tong Zhang 0002 Design of Last-Level On-Chip Cache Using Spin-Torque Transfer RAM (STT RAM). Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2011 DBLP  DOI  BibTeX  RDF
43Anurag Nigam, Clinton Wills Smullen IV, Vidyabhushan Mohan, Eugene Chen, Sudhanva Gurumurthi, Mircea R. Stan Delivering on the promise of universal memory for spin-transfer torque RAM (STT-RAM). Search on Bibsonomy ISLPED The full citation details ... 2011 DBLP  BibTeX  RDF
43Yiran Chen 0001, Xiaobin Wang, Hai Li 0001, Haiwen Xi, Yuan Yan, Wenzhong Zhu Design Margin Exploration of Spin-Transfer Torque RAM (STT-RAM) in Scaled Technologies. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
29Saeed Seyedfaraji, Markus Bichl, Asad Aftab, Semeen Rehman HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis. Search on Bibsonomy IEEE Access The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
29Saeed Seyedfaraji, Markus Bichl, Asad Aftab, Semeen Rehman HOPE: Holistic STT-RAM Architecture Exploration Framework for Future Cross-Platform Analysis. Search on Bibsonomy CoRR The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
29Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal, José María Llabería Reuse Detector: Improving the Management of STT-RAM SLLCs. Search on Bibsonomy CoRR The full citation details ... 2024 DBLP  DOI  BibTeX  RDF
29SatyaJaswanth Badri, Mukesh Saini, Neeraj Goel Efficient placement and migration policies for an STT-RAM based hybrid L1 cache for intermittently powered systems. Search on Bibsonomy Des. Autom. Embed. Syst. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
29Sheel Sindhu Manohar, Hemangee K. Kapoor CAPMIG: Coherence-Aware Block Placement and Migration in Multiretention STT-RAM Caches. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
29Jinzhi Lai, Jueping Cai, Jie Chu A congestion-aware hybrid SRAM and STT-RAM buffer design for network-on-chip router. Search on Bibsonomy IEICE Electron. Express The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
29Gwangeun Byeon, Seongwook Kim, Seokin Hong Improving Performance and Energy-efficiency of DNN Accelerators with STT-RAM Buffers. Search on Bibsonomy ISOCC The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
29Saeed Seyedfaraji, Javad Talafy Daryani, Mohamed M. Sabry Aly, Semeen Rehman EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit. Search on Bibsonomy IEEE Access The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
29An Yang, Yanfeng Jiang Leakage-Current-Canceling Current-Sampling Sense Amplifier for Deep Submicrometer STT-RAM. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
29Jen-Wei Hsieh, Yueh-Ting Hou, Tai-Chieh Chang Alternative Encoding: A Two-Step Transition Reduction Scheme for MLC STT-RAM Cache. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
29Sheel Sindhu Manohar, Sparsh Mittal, Hemangee K. Kapoor CORIDOR: Using COherence and TempoRal LocalIty to Mitigate Read Disurbance ErrOR in STT-RAM Caches. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
29Saeed Seyedfaraji, Javad Talafy, Mohamed M. Sabry, Semeen Rehman EXTENT: Enabling Approximation-Oriented Energy Efficient STT-RAM Write Circuit. Search on Bibsonomy CoRR The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
29Dhruv Gajaria, Tosiron Adegbija Evaluating the performance and energy of STT-RAM caches for real-world wearable workloads. Search on Bibsonomy Future Gener. Comput. Syst. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
29Yogesh Kumar, S. Sivakumar, John Jose ENDURA : Enhancing Durability of Multi Level Cell STT-RAM based Non Volatile Memory Last Level Caches. Search on Bibsonomy VLSI-SoC The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
29Dhruv Gajaria, Kevin Antony Gomez, Tosiron Adegbija A Study of STT-RAM-based In-Memory Computing Across the Memory Hierarchy. Search on Bibsonomy ICCD The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
29Arindam Sarkar, Newton Singh, Varun Venkitaraman, Virendra Singh DAM: Deadblock Aware Migration Techniques for STT-RAM-Based Hybrid Caches. Search on Bibsonomy IEEE Comput. Archit. Lett. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
29Xiaoxiao Liu 0001, Mengjie Mao, Xiuyuan Bi, Hai Helen Li, Yiran Chen 0001 Exploring Applications of STT-RAM in GPU Architectures. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
29Sara Choi, Hong Keun Ahn, Byungkyu Song, Seung-Hyuk Kang, Seong-Ook Jung Self-Referenced Single-Ended Resistance Monitoring Write Termination Scheme for STT-RAM Write Energy Reduction. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
29Jen-Wei Hsieh, Yi-Yu Liu, Hung-Tse Lee, Tai Chang TSE: Two-Step Elimination for MLC STT-RAM Last-Level Cache. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
29Fateme S. Hosseini, Chengmo Yang A Compile-Time Framework for Tolerating Read Disturbance in STT-RAM. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
29Yao-Hung Huang, Jen-Wei Hsieh Read/Write Disturbance-Aware Design for MLC STT-RAM-based Cache. Search on Bibsonomy RTCSA The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
29Sukarn Agarwal, Shounak Chakraborty 0001 ABACa: Access Based Allocation on Set Wise Multi-Retention in STT-RAM Last Level Cache. Search on Bibsonomy ASAP The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
29Mayank Baranwal, Udbhav Chugh, Shivang Dalal, Sukarn Agarwal, Hemangee K. Kapoor DAMUS: Dynamic Allocation based on Write Frequency in MUlti-Retention STT-RAM based Last Level Caches. Search on Bibsonomy ISQED The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
29Muhammad Avais Qureshi, Jungwoo Park, Soontae Kim SALE: Smartly Allocating Low-Cost Many-Bit ECC for Mitigating Read and Write Errors in STT-RAM Caches. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Elyas Khajekarimi, Kamal Jamshidi, Abbas Vafaei Integer linear programming model for allocation and migration of data blocks in the STT-RAM-based hybrid caches. Search on Bibsonomy IET Comput. Digit. Tech. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Masoomeh Jasemi, Shaahin Hessabi, Nader Bagherzadeh Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators. Search on Bibsonomy Comput. Electr. Eng. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Saeed Seyedfaraji, Amir M. Hajisadeghi, Javad Talafy, Hamid R. Zarandi DYSCO: DYnamic Stepper Current InjectOr to improve write performance in STT-RAM memories. Search on Bibsonomy Microprocess. Microsystems The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Kyle Kuan, Tosiron Adegbija Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Quan Deng, Youtao Zhang, Zhenyu Zhao, Shuzheng Zhang, Minxuan Zhang, Jun Yang 0002 FRF: Toward Warp-Scheduler Friendly STT-RAM/SRAM Fine-Grained Hybrid GPGPU Register File Design. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Masoomeh Jasemi, Shaahin Hessabi, Nader Bagherzadeh Reliable and Energy Efficient MLC STT-RAM Buffer for CNN Accelerators. Search on Bibsonomy CoRR The full citation details ... 2020 DBLP  BibTeX  RDF
29Shashank Suman, Hemangee K. Kapoor Reinforcement Learning Based Refresh Optimized Volatile STT-RAM Cache. Search on Bibsonomy ISVLSI The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Shuo-Han Chen, Yu-Pei Liang, Yuan-Hao Chang 0001, Yun-Fei Liu, Chun-Feng Wu, Hsin-Wen Wei, Wei-Kuan Shih Reinforcing the energy efficiency of cyber-physical systems via direct and split cache consolidation on MLC STT-RAM. Search on Bibsonomy SAC The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Ping Cheng, Jen-Wei Hsieh Early eviction and swapping for MLC STT-RAM-based LLC. Search on Bibsonomy SAC The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Shruti R. Kulkarni, Shihui Yin, Jae-sun Seo, Bipin Rajendran An On-Chip Learning Accelerator for Spiking Neural Networks using STT-RAM Crossbar Arrays. Search on Bibsonomy DATE The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Jingjing Fu, Yu Liu A Comprehensive Performance Evaluation to GPGPU Applications under STT- RAM based Hybrid Cache Architectures. Search on Bibsonomy SBESC The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Masayuki Sato 0001, Xue Hao, Kazuhiko Komatsu, Hiroaki Kobayashi Energy-efficient Design of an STT-RAM-based Hybrid Cache Architecture. Search on Bibsonomy COOL CHIPS The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Binbin Liu, Fan Yang 0001, Dian Zhou, Xuan Zeng 0001 An Efficient Memory Partitioning Approach for Multi-Pattern Data Access in STT-RAM. Search on Bibsonomy ISCAS The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Jinbo Chen, Keren Liu, Xiaochen Guo, Patrick Girard 0001, Yuanqing Cheng DOVA: A Dynamic Overwriting Voltage Adjustment for STT-RAM L1 Cache. Search on Bibsonomy ISQED The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
29Mimi Xie, Chen Pan, Youtao Zhang, Jingtong Hu, Yongpan Liu, Chun Jason Xue A Novel STT-RAM-Based Hybrid Cache for Intermittently Powered Processors in IoT Devices. Search on Bibsonomy IEEE Micro The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Muhammad Avais Qureshi, Hyeonggyu Kim, Soontae Kim A Restore-Free Mode for MLC STT-RAM Caches. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Fazal Hameed, Jerónimo Castrillón A Novel Hybrid DRAM/STT-RAM Last-Level-Cache Architecture for Performance, Energy, and Endurance Enhancement. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Fanfan Shen, Yanxiang He, Jun Zhang 0058, Chao Xu Periodic learning-based region selection for energy-efficient MLC STT-RAM cache. Search on Bibsonomy J. Supercomput. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Elyas Khajekarimi, Kamal Jamshidi, Abbas Vafaei Energy minimization in the STT-RAM-based high-capacity last-level caches. Search on Bibsonomy J. Supercomput. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Zahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, Seyed Ghassem Miremadi AWARE: Adaptive Way Allocation for Reconfigurable ECCs to Protect Write Errors in STT-RAM Caches. Search on Bibsonomy IEEE Trans. Emerg. Top. Comput. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Lei Yang 0018, Weichen Liu, Nan Guan, Nikil D. Dutt Optimal Application Mapping and Scheduling for Network-on-Chips with Computation in STT-RAM Based Router. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Kyle Kuan, Tosiron Adegbija HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Jungwoo Park, Myoungjun Lee, Soontae Kim, Minho Ju, Jeongkyu Hong MH Cache: A Mult Stephen Jarvisi-retention STT-RAM-based Low-power Last-level Cache for Mobile Hardware Rendering Systems. Search on Bibsonomy ACM Trans. Archit. Code Optim. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Zhiyao Gong, Keni Qiu, Weiwen Chen, Yuanhui Ni, Yuanchao Xu 0002, Jianlei Yang 0001 Redesigning pipeline when architecting STT-RAM as registers in rad-hard environment. Search on Bibsonomy Sustain. Comput. Informatics Syst. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Keni Qiu, Yujie Zhu, Yuanchao Xu 0002, Qirun Huo, Chun Jason Xue BRLoop: Constructing balanced retimed loop to architect STT-RAM-based hybrid cache for VLIW processors. Search on Bibsonomy Microelectron. J. The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Kyle Kuan, Tosiron Adegbija Energy-Efficient Runtime Adaptable L1 STT-RAM Cache Design. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
29Kyle Kuan, Tosiron Adegbija HALLS: An Energy-Efficient Highly Adaptable Last Level STT-RAM Cache for Multicore Systems. Search on Bibsonomy CoRR The full citation details ... 2019 DBLP  BibTeX  RDF
29Fateme S. Hosseini, Chengmo Yang Compiler-Directed and Architecture-Independent Mitigation of Read Disturbance Errors in STT-RAM. Search on Bibsonomy DATE The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Shruti R. Kulkarni, Deepak Vinayak Kadetotad, Shihui Yin, Jae-Sun Seo, Bipin Rajendran Neuromorphic Hardware Accelerator for SNN Inference based on STT-RAM Crossbar Arrays. Search on Bibsonomy ICECS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Dhruv Gajaria, Kyle Kuan, Tosiron Adegbija SCART: Predicting STT-RAM Cache Retention Times Using Machine Learning. Search on Bibsonomy IGSC The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Dhruv Gajaria, Tosiron Adegbija ARC: DVFS-aware asymmetric-retention STT-RAM caches for energy-efficient multicore processors. Search on Bibsonomy MEMSYS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Puneet Saraf, Madhu Mutyam Endurance enhancement of write-optimized STT-RAM caches. Search on Bibsonomy MEMSYS The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Yu-Pei Liang, Tseng-Yi Chen, Yuan-Hao Chang 0001, Shuo-Han Chen, Pei-Yu Chen, Wei-Kuan Shih Rethinking Last-level-cache Write-back Strategy for MLC STT-RAM Main Memory with Asymmetric Write Energy. Search on Bibsonomy ISLPED The full citation details ... 2019 DBLP  DOI  BibTeX  RDF
29Masayuki Sato 0001, Yoshiki Shoji, Zentaro Sakai, Ryusuke Egawa, Hiroaki Kobayashi An Adjacent-Line-Merging Writeback Scheme for STT-RAM-Based Last-Level Caches. Search on Bibsonomy IEEE Trans. Multi Scale Comput. Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Mohammad Taghi Teimoori, Alireza Ejlali An Instruction-Level Quality-Aware Method for Exploiting STT-RAM Read Approximation Techniques. Search on Bibsonomy IEEE Embed. Syst. Lett. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29He Zhang 0011, Wang Kang 0001, Youguang Zhang, Meng-Fan Chang, Weisheng Zhao A Full-Sensing-Margin Dual-Reference Sensing Scheme for Deeply-Scaled STT-RAM. Search on Bibsonomy IEEE Access The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Navid Khoshavi, Ronald F. DeMara Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization. Search on Bibsonomy IEEE Access The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Jaeyoung Park, Young Uk Yim Two-Phase Read Strategy for Low Energy Variation-Tolerant STT-RAM. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Fazal Hameed, Asif Ali Khan, Jerónimo Castrillón Performance and Energy-Efficient Design of STT-RAM Last-Level Cache. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Shouyi Yin, Tianyi Lu, Zhicong Xie, Leibo Liu, Shaojun Wei Bit-Level Disturbance-Aware Memory Partitioning for Parallel Data Access for MLC STT-RAM. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Lan Gao, Rui Wang 0014, Yunlong Xu, Hailong Yang, Zhongzhi Luan, Depei Qian, Han Zhang, Jihong Cai SRAM- and STT-RAM-based hybrid, shared last-level cache for on-chip CPU-GPU heterogeneous architectures. Search on Bibsonomy J. Supercomput. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Adnan Nasri, Mahmood Fathy, Ali Broumandnia An energy-efficient 3D-stacked STT-RAM cache architecture for cloud processors: the effect on emerging scale-out workloads. Search on Bibsonomy J. Supercomput. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Zihao Liu, Mengjie Mao, Tao Liu 0023, Xue Wang, Wujie Wen, Yiran Chen 0001, Hai Li 0001, Danghui Wang, Yukui Pei, Ning Ge 0001 TriZone: A Design of MLC STT-RAM Cache for Combined Performance, Energy, and Reliability Optimizations. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Bohua Li, Yukui Pei, Wujie Wen Efficient LDPC Code Design for Combating Asymmetric Errors in STT-RAM. Search on Bibsonomy ACM J. Emerg. Technol. Comput. Syst. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Yanna Zhu, Danghui Wang 基于多级磁自旋存储器的Cache调度策略的设计 (Design of Cache Scheduling Policies Based on MLC STT-RAM). Search on Bibsonomy 计算机科学 The full citation details ... 2018 DBLP  BibTeX  RDF
29Taehui Na, Byungkyu Song, Jung Pill Kim, Seung-Hyuk Kang, Seong-Ook Jung Data-Cell-Variation-Tolerant Dual-Mode Sensing Scheme for Deep Submicrometer STT-RAM. Search on Bibsonomy IEEE Trans. Circuits Syst. I Regul. Pap. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Behzad Zeinali, Dimitrios Karsinos, Farshad Moradi Progressive Scaled STT-RAM for Approximate Computing in Multimedia Applications. Search on Bibsonomy IEEE Trans. Circuits Syst. II Express Briefs The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Roberto Rodríguez-Rodríguez, Javier Díaz, Fernando Castro, Pablo Ibáñez, Daniel Chaver, Víctor Viñals, Juan Carlos Saez, Manuel Prieto-Matías, Luis Piñuel, Teresa Monreal Arnal, José María Llabería Reuse Detector: Improving the Management of STT-RAM SLLCs. Search on Bibsonomy Comput. J. The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Rabab Bouziane, Erven Rohou, Abdoulaye Gamatié Energy-Efficient Memory Mappings based on Partial WCET Analysis and Multi-Retention Time STT-RAM. Search on Bibsonomy RTNS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Zihao Liu, Tao Liu 0023, Jie Guo 0002, Nansong Wu, Wujie Wen An ECC-Free MLC STT-RAM Based Approximate Memory Design for Multimedia Applications. Search on Bibsonomy ISVLSI The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Kyle Kuan, Tosiron Adegbija LARS: Logically adaptable retention time STT-RAM cache for embedded systems. Search on Bibsonomy DATE The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Saaed S. Faraji, Javad Talafy, Amir M. Hajisadeghi, Hamid R. Zarandi DUSTER: DUal Source Write TERmination Method for STT-RAM Memories. Search on Bibsonomy DSD The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Enes Eken, Ismail Bayram, Hai Helen Li, Yiran Chen 0001 Modeling of biaxial magnetic tunneling junction for multi-level cell STT-RAM realization. Search on Bibsonomy ASP-DAC The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Bhukya Krishna Priya, Sampath Kumar, B. Shameedha Begum, N. Ramasubramaniam Enhancing the lifetime of STT-RAM with MRU replacement algorithm. Search on Bibsonomy RAIT The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Hengyu Zhao, Jishen Zhao Leveraging MLC STT-RAM for energy-efficient CNN training. Search on Bibsonomy MEMSYS The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
29Sparsh Mittal, Jeffrey S. Vetter, Lei Jiang 0001 Addressing Read-Disturbance Issue in STT-RAM by Data Compression and Selective Duplication. Search on Bibsonomy IEEE Comput. Archit. Lett. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
29Yuanhui Ni, Zhiyao Gong, Weiwen Chen, Chengmo Yang, Keni Qiu State-Transition-Aware Spilling Heuristic for MLC STT-RAM-Based Registers. Search on Bibsonomy VLSI Design The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
29Enes Eken, Ismail Bayram, Yaojun Zhang, Bonan Yan, Wenqing Wu, Hai (Helen) Li, Yiran Chen 0001 Giant Spin-Hall assisted STT-RAM and logic design. Search on Bibsonomy Integr. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
29Xiuyuan Bi, Mengjie Mao, Danghui Wang, Hai Helen Li Cross-Layer Optimization for Multilevel Cell STT-RAM Caches. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
29Hooman Farkhani, Mohammad Tohidi, Ali Peiravi, Jens Kargaard Madsen, Farshad Moradi STT-RAM Energy Reduction Using Self-Referenced Differential Write Termination Technique. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
29Hyeonggyu Kim, Soontae Kim, Jooheung Lee Write-Amount-Aware Management Policies for STT-RAM Caches. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
29Lili Song, Ying Wang 0001, Yinhe Han 0001, Huawei Li 0001, Yuanqing Cheng, Xiaowei Li 0001 STT-RAM Buffer Design for Precision-Tunable General-Purpose Neural Network Accelerator. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
29Xunchao Chen, Navid Khoshavi, Ronald F. DeMara, Jun Wang 0001, Dan Huang, Wujie Wen, Yiran Chen 0001 Energy-Aware Adaptive Restore Schemes for MLC STT-RAM Cache. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
29Zahra Azad, Hamed Farbeh, Amir Mahdi Hosseini Monazzah, Seyed Ghassem Miremadi An Efficient Protection Technique for Last Level STT-RAM Caches in Multi-Core Processors. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
29Yaojun Zhang, Bonan Yan, Xiaobin Wang, Yiran Chen 0001 Persistent and Nonpersistent Error Optimization for STT-RAM Cell Design. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
29Sparsh Mittal Mitigating Read-disturbance Errors in STT-RAM Caches by Using Data Compression. Search on Bibsonomy CoRR The full citation details ... 2017 DBLP  BibTeX  RDF
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