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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 654 occurrences of 435 keywords
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Results
Found 1011 publication records. Showing 1002 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
93 | Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu |
An FPGA-based re-configurable functional tester for memory chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 51-57, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
re-configurable tester, memory chips, re-configurable hardware platform, prototype tester, compiler, integrated circuit testing, reconfigurable architectures, integrated memory circuits |
73 | Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka |
Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 28-31, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
SRAM test, SRAM-based reconfigurable cell, memory tester, marching test |
71 | Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara |
Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(7), pp. 790-800, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
71 | Matthieu Tuna, Mounir Benabdenbi, Alain Greiner |
At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 25th IEEE VLSI Test Symposium (VTS 2007), 6-10 May 2007, Berkeley, California, USA, pp. 447-454, 2007, IEEE Computer Society, 0-7695-2812-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
67 | Intaik Park, Donghwi Lee, Erik Chmelar, Edward J. McCluskey |
Inconsistent Fail due to Limited Tester Timing Accuracy. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 47-52, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
inconsistent fail, tester timing accuracy, tester EPA, delay test, inconsistency |
62 | Dana Moshkovitz, Ran Raz |
Sub-constant error low degree test of almost-linear size. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 38th Annual ACM Symposium on Theory of Computing, Seattle, WA, USA, May 21-23, 2006, pp. 21-30, 2006, ACM, 1-59593-134-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
plane vs. point test, probabilistically checkable proofs, locally testable codes, low degree testing |
62 | Alexandre Petrenko, Nina Yevtushenko 0001, Jiale Huo |
Testing Transition Systems with Input and Output Testers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TestCom ![In: Testing of Communicating Systems, 15th IFIP International Conference, TestCom 2003, Sophia Antipolis, France, May 26-28, 2003, Proceedings, pp. 129-145, 2003, Springer, 3-540-40123-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
input/output transition system, test generation, fault model, conformance testing |
62 | Joan Feigenbaum, Sampath Kannan, Martin Strauss 0001, Mahesh Viswanathan 0001 |
Testing and Spot-Checking of Data Streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Algorithmica ![In: Algorithmica 34(1), pp. 67-80, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
62 | Abhijit Jas, Nur A. Touba |
Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 18(4-5), pp. 503-514, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
test data compression, system-on-chip testing, deterministic testing |
58 | Vinay Verma, Shantanu Dutt, Vishal Suthar |
Efficient on-line testing of FPGAs with provable diagnosabilities. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 498-503, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability |
55 | Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Nobuhiro Yanagida |
Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 8th Asian Test Symposium (ATS '99), 16-18 November 1999, Shanghai, China, pp. 341-346, 1999, IEEE Computer Society, 0-7695-0315-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
single/multiple fault simulators, EB tester, fault diagnosis, combinational circuit, multiple stuck-at fault |
53 | Paul Valiant |
Testing symmetric properties of distributions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
STOC ![In: Proceedings of the 40th Annual ACM Symposium on Theory of Computing, Victoria, British Columbia, Canada, May 17-20, 2008, pp. 383-392, 2008, ACM, 978-1-60558-047-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
vandermonde matrices, continuity, property testing, distribution testing, multivariate statistics |
53 | Irit Dinur, Omer Reingold |
Assignment Testers: Towards a Combinatorial Proof of the PCP-Theorem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 45th Symposium on Foundations of Computer Science (FOCS 2004), 17-19 October 2004, Rome, Italy, Proceedings, pp. 155-164, 2004, IEEE Computer Society, 0-7695-2228-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
53 | Robert W. Bassett, Barry J. Butkus, Stephen L. Dingle, Marc R. Faucher, Pamela S. Gillis, Jeannie H. Panner, John G. Petrovick, Donald L. Wheater |
Low-Cost Testing of High-Density Logic Components. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 7(2), pp. 15-28, 1990. The full citation details ...](Pics/full.jpeg) |
1990 |
DBLP DOI BibTeX RDF |
|
53 | Lyl M. Ciganda, Francesco Abate, Paolo Bernardi, M. Bruno, Matteo Sonza Reorda |
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 2009 IEEE Symposium on Design and Diagnostics of Electronic Circuits and Systems, DDECS 2009, April 15-17, 2009, Liberec, Czech Republic, pp. 258-263, 2009, IEEE Computer Society, 978-1-4244-3341-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
53 | David Money Harris, David Diaz |
TestosterICs: A Low-Cost Functional Chip Tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2003 International Conference on Microelectronics Systems Education, MSE 2003, Educating Tomorrow's Microsystems Designers, Anaheim, CA, USA, June 1-2, 2003, pp. 74-75, 2003, IEEE Computer Society, 0-7695-1973-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
53 | Juhana Helovuo, Antti Valmari |
Checking for CFFD-Preorder with Tester Processes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
TACAS ![In: Tools and Algorithms for Construction and Analysis of Systems, 6th International Conference, TACAS 2000, Held as Part of the European Joint Conferences on the Theory and Practice of Software, ETAPS 2000, Berlin, Germany, March 25 - April 2, 2000, Proceedings, pp. 283-298, 2000, Springer, 3-540-67282-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
53 | Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu |
Electron Beam Tester Aided Fault Diagnosis for Logic Circuits Based on Sensitized Paths. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 7th Asian Test Symposium (ATS '98), 2-4 December 1998, Singapore, pp. 237-, 1998, IEEE Computer Society, 0-8186-8277-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
49 | Irith Pomeranz, Sudhakar M. Reddy |
On Test Compaction Objectives for Combinational and Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 11th International Conference on VLSI Design (VLSI Design 1991), 4-7 January 1998, Chennai, India, pp. 279-284, 1998, IEEE Computer Society, 0-8186-8224-8. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
combinational circuits synchronous sequential circuits test compaction tester storage schemes tester memory requirements |
47 | Jae Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham |
A delay measurement method using a shrinking clock signal. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, Providence, Rhode Island, USA, May 16-18 2010, pp. 139-142, 2010, ACM, 978-1-4503-0012-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
edge placement accuracy, tester, measurement, delay |
47 | Matthew L. Fichtenbaum, Gordon D. Robinson |
Scan test architectures for digital board testers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 2(1), pp. 99-105, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
tester architecture, scan, boundary scan |
44 | Angela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar |
Testing High Speed VLSI Devices Using Slower Testers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 17th IEEE VLSI Test Symposium (VTS '99), 25-30 April 1999, San Diego, CA, USA, pp. 16-21, 1999, IEEE Computer Society, 0-7695-0146-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
44 | Xuefa Hu, Zhen Zhao 0004, Shu Wang, Fuli Wang, Dakuo He, Shui-kang Wu |
Multi-stage extreme learning machine for fault diagnosis on hydraulic tube tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Neural Comput. Appl. ![In: Neural Comput. Appl. 17(4), pp. 399-403, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
44 | Shu Wang, Xuefa Hu, Dakuo He, Fuli Wang |
A Fault Diagnosis Method to Hydraulic Tube Tester Production Process. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSKD (4) ![In: Fourth International Conference on Fuzzy Systems and Knowledge Discovery, FSKD 2007, 24-27 August 2007, Haikou, Hainan, China, Proceedings, Volume 4, pp. 370-373, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
44 | A. M. Majid, David C. Keezer, J. V. Karia |
A 5 Gbps Wafer-Level Tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 14th Asian Test Symposium (ATS 2005), 18-21 December 2005, Calcutta, India, pp. 58-63, 2005, IEEE Computer Society, 0-7695-2481-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
44 | Mark Litterick, Joachim Geishauser |
Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTV ![In: Fifth International Workshop on Microprocessor Test and Verification (MTV 2004), Common Challenges and Solutions, 08-10 September 2004, Austin, Texas, USA, pp. 64-78, 2004, IEEE Computer Society, 0-7695-2320-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
44 | Maurizio Gavardoni |
Data flow within an open architecture tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 185-190, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
44 | Kazuhiro Yamada, Yoshikazu Takahashi |
Vector Memory Expansion System For T33xx Logic Tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, pp. 392-, 2002, IEEE Computer Society, 0-7695-1825-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
T33XX LSSD vector pattern DFT |
44 | Junichi Hirase |
Test Time Reduction through Minimum Execution of Tester-Hardware Setting Instructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, pp. 173-178, 2001, IEEE Computer Society, 0-7695-1378-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
40 | Vishal Suthar, Shantanu Dutt |
High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 78-83, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability |
40 | Ravi Kumar 0001, D. Sivakumar 0001 |
Efficient Self-Testing/Self-Correction of Linear Recurrences. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 37th Annual Symposium on Foundations of Computer Science, FOCS '96, Burlington, Vermont, USA, 14-16 October, 1996, pp. 602-611, 1996, IEEE Computer Society, 0-8186-7594-2. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
efficient self-testing, efficient self-correction, self-tester design, self-corrector design, result-checkers, linear function testing, counting arguments, matrix twist, convolution identities, VLSI chip testing, randomness-efficient self-tester, rational domains, signal processing, finite fields, program testing, polynomials, reduction, functions, spectral analysis, matrix groups, linear recurrences, control engineering |
40 | Kotaro Katsuyama, Fumiaki Sato, Tetsuo Nakakawaji, Tadanori Mizuno |
Strategic Testing Environment with Formal Description Techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 40(4), pp. 514-525, 1991. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
formal environment for systematic testing, stepwise approach, test development, TENT, test sequence generation tool, APRICOT, ASN.1 pre-compiler, coder, test-debugger, test specification editor, upper tester, lower tester, simulator, design, formal specification, protocol, protocols, data structures, programming environments, formal semantics, communication systems, formal description techniques, FOREST, test execution |
38 | Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei |
A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(6), pp. 621-630, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
timing specifications testing, test environment, tester OTA and yield, high-speed interconnect testing, yield analysis |
38 | Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov |
Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 348-353, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Timing specifications testing, Test Environment, Tester OTA and yield, High-speed interconnect testing, Yield analysis |
38 | Hiroshi Takahashi, Nobuhiro Yanagida, Yuzo Takamatsu |
Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 4th Asian Test Symposium (ATS '95), November 23-24, 1995. Bangalore, India, pp. 58-64, 1995, IEEE Computer Society, 0-8186-7129-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
electron beam testing, multiple fault diagnosis, sensitized paths, EB testing, TP-1, TP-2, TP-3, TP-4, electron-beam tester, internal lines, VLSI, fault diagnosis, logic testing, combinational circuits, combinational circuits, fault location, fault location, stuck-at faults, diagnostic resolution |
38 | Hyun Sook Rhee, Jong Hwan Park, Willy Susilo, Dong Hoon Lee 0001 |
Improved searchable public key encryption with designated tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AsiaCCS ![In: Proceedings of the 2009 ACM Symposium on Information, Computer and Communications Security, ASIACCS 2009, Sydney, Australia, March 10-12, 2009, pp. 376-379, 2009, ACM, 978-1-60558-394-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
designated tester, public key encryption with keyword search, searchable encryption |
38 | Daniel G. Bobrow, J. Bruce Fraser |
A phonological rule tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 11(11), pp. 766-772, 1968. The full citation details ...](Pics/full.jpeg) |
1968 |
DBLP DOI BibTeX RDF |
format-directed list processing, on-line systems, phonology, rule tester, LISP, linguistics, transformational grammar |
37 | Kasper Johansen, Mitchell J. L. Morton, Yoann Malbéteau, Bruno Aragon, Samer Al-Mashharawi, Matteo G. Ziliani, Yoseline Angel, Gabriele Fiene, Sónia Negrão, Magdi A. A. Mousa, Mark A. Tester, Matthew F. McCabe |
Predicting Biomass and Yield in a Tomato Phenotyping Experiment Using UAV Imagery and Random Forest. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Frontiers Artif. Intell. ![In: Frontiers Artif. Intell. 3, pp. 28, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
37 | Maciej Lukawski, Jefferson W. Tester, Michal C. Moore, Pawel Król, C. Lindsay Anderson |
Demand Response for Reducing Coincident Peak Loads in Data Centers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HICSS ![In: 52nd Hawaii International Conference on System Sciences, HICSS 2019, Grand Wailea, Maui, Hawaii, USA, January 8-11, 2019, pp. 1-11, 2019, ScholarSpace. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP BibTeX RDF |
|
37 | Uzma Tahir, Anthony L. Hessel, Eric R. Lockwood, John T. Tester, Zhixiu Han, Daniel J. Rivera, Kaitlyn L. Covey, Thomas G. Huck, Nicole A. Rice, Kiisa C. Nishikawa |
Case Study: A Bio-Inspired Control Algorithm for a Robotic Foot-Ankle Prosthesis Provides Adaptive Control of Level Walking and Stair Ascent. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Frontiers Robotics AI ![In: Frontiers Robotics AI 5, pp. 36, 2018. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
37 | Ben Ward, John W. Bastian, Anton van den Hengel, Daniel Pooley, Rajendra Bari, Bettina Berger, Mark A. Tester |
A model-based approach to recovering the structure of a plant from images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/1503.03191, 2015. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP BibTeX RDF |
|
37 | Robert LeMoyne, Jeremy Petak, John T. Tester, Kiisa Nishikawa |
Simulation of a computational winding filament model with an exponential spring to represent titin. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EMBC ![In: 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, EMBC 2014, Chicago, IL, USA, August 26-30, 2014, pp. 836-839, 2014, IEEE. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
37 | Ben Ward, John W. Bastian, Anton van den Hengel, Daniel Pooley, Rajendra Bari, Bettina Berger, Mark A. Tester |
A Model-Based Approach to Recovering the Structure of a Plant from Images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ECCV Workshops (4) ![In: Computer Vision - ECCV 2014 Workshops - Zurich, Switzerland, September 6-7 and 12, 2014, Proceedings, Part IV, pp. 215-230, 2014, Springer, 978-3-319-16219-5. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
37 | Kristofer Tester, James W. Scrofani, Murali Tummala, David Garren, John C. McEachen |
A spatiotemporal clustering approach to maritime domain awareness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICSPCS ![In: 7th International Conference on Signal Processing and Communication Systems, ICSPCS 2013, Carrara - Gold Coast, Australia, December 16-18, 2013, pp. 1-9, 2013, IEEE, 978-1-4799-1319-0. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
37 | Darlene M. Tester |
Book Review: Online Privacy: Issues in the Digital Age. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Digit. Forensics Secur. Law ![In: J. Digit. Forensics Secur. Law 6(3), pp. 75-78, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
37 | Kaijian Shi, David Tester |
Well tapping methodologies in power-gating design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SoCC ![In: IEEE 24th International SoC Conference, SOCC 2011, Taipei, Taiwan, September 26-28, 2011, pp. 128-131, 2011, IEEE, 978-1-4577-1616-4. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
37 | Keith Tester |
Book Review: The Ethics of Cyberspace. ![Search on Bibsonomy](Pics/bibsonomy.png) |
New Media Soc. ![In: New Media Soc. 4(1), pp. 130-133, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
37 | Jason Tester, B. J. Fogg, Michael Maile |
CommuterNews: a prototype of persuasive in-car entertainment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHI Extended Abstracts ![In: CHI '00 Extended Abstracts on Human Factors in Computing Systems, CHI Extended Abstracts '00, The Hague, The Netherlands, April 1-6, 2000, pp. 24-25, 2000, ACM, 978-1-58113-248-9. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
37 | Phillip King, Jason Tester |
The Landscape of Persuasive Technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Commun. ACM ![In: Commun. ACM 42(5), pp. 31-38, 1999. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
37 | B. J. Fogg, Daniel Bedichevsky, Jason Tester |
Persuasive computing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM SIGCHI Bull. ![In: ACM SIGCHI Bull. 30(4), pp. 71-72, 1998. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
37 | B. Kobrinsky, I. Tester, N. Demikova, Yu. Sedov, B. Marjanchik, L. Taperova, Yu. Glukhovskaya, M. Podolnaja |
A Multifunctional System of the National Genetic Register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MedInfo ![In: MEDINFO '98 - 9th World Congress on Medical Informatics, Seoul, South Korea, August 14-21, 1998., pp. 121-125, 1998, IOS Press, 978-90-5199-407-0. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
36 | Eli Ben-Sasson, Michael Viderman |
Composition of Semi-LTCs by Two-Wise Tensor Products. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APPROX-RANDOM ![In: Approximation, Randomization, and Combinatorial Optimization. Algorithms and Techniques, 12th International Workshop, APPROX 2009, and 13th International Workshop, RANDOM 2009, Berkeley, CA, USA, August 21-23, 2009. Proceedings, pp. 378-391, 2009, Springer, 978-3-642-03684-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
36 | Eldar Fischer, Frédéric Magniez, Michel de Rougemont |
Approximate Satisfiability and Equivalence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LICS ![In: 21th IEEE Symposium on Logic in Computer Science (LICS 2006), 12-15 August 2006, Seattle, WA, USA, Proceedings, pp. 421-430, 2006, IEEE Computer Society, 0-7695-2631-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | Mircea Popa 0001, Voicu Groza, Alina Botas |
Lin Bus Testing Software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the Canadian Conference on Electrical and Computer Engineering, CCECE 2006, May 7-10, 2006, Ottawa Congress Centre, Ottawa, Canada, pp. 1287-1290, 2006, IEEE, 1-4244-0038-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
36 | C. V. Krishna, Nur A. Touba |
Hybrid BIST Using an Incrementally Guided LFSR. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 3-5 November 2003, Boston, MA, USA, Proceedings, pp. 217-224, 2003, IEEE Computer Society, 0-7695-2042-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger |
Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 21st IEEE VLSI Test Symposium (VTS 2003), 27 April - 1 May 2003, Napa Valley, CA, USA, pp. 345-350, 2003, IEEE Computer Society, 0-7695-1924-5. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
36 | Ken Auer, Ron Jeffries, Jeff Canna, Glen B. Alleman, Lisa Crispin, Janet Gregory 0002 |
Are Testers eXtinct? How Can Testers Contribute to XP Teams? ![Search on Bibsonomy](Pics/bibsonomy.png) |
XP/Agile Universe ![In: Extreme Programming and Agile Methods - XP/Agile Universe 2002, Second XP Universe and First Agile Universe Conference Chicago, IL, USA, August 4-7, 2002, Proceedings, pp. 287, 2002, Springer, 3-540-44024-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
36 | Abhijit Jas, Nur A. Touba |
Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: Proceedings of the IEEE International Conference On Computer Design, VLSI in Computers and Processors, ICCD '99, Austin, Texas, USA, October 10-13, 1999, pp. 418-, 1999, IEEE Computer Society, 0-7695-0406-X. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
Test Vector Compression, External Testing, Built-In Self-Test, Embedded Processor, System-on-a-Chip, Automatic Test Equipment, At-Speed Testing, Scan Chains, Deterministic Testing |
36 | Abhijit Jas, Nur A. Touba |
Test vector decompression via cyclical scan chains and its application to testing core-based designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings IEEE International Test Conference 1998, Washington, DC, USA, October 18-22, 1998, pp. 458-464, 1998, IEEE Computer Society, 0-7803-5093-6. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
35 | Wai Han Ho, Paul Andrew Watters, Dominic R. Verity |
Robustness of the New Owner-Tester Approach for Face Identification Experiments. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CVPR ![In: 2007 IEEE Computer Society Conference on Computer Vision and Pattern Recognition (CVPR 2007), 18-23 June 2007, Minneapolis, Minnesota, USA, 2007, IEEE Computer Society, 1-4244-1179-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
35 | Jüri Vain, Kullo Raiend, Andres Kull, Juhan P. Ernits |
Synthesis of test purpose directed reactive planning tester for nondeterministic systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASE ![In: 22nd IEEE/ACM International Conference on Automated Software Engineering (ASE 2007), November 5-9, 2007, Atlanta, Georgia, USA, pp. 363-372, 2007, ACM, 978-1-59593-882-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
nondeterministic extended finite state machine, reactive planning, model-based testing, online testing |
35 | Vinay Verma, Shantanu Dutt |
Roving testing using new built-in-self-tester designs for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 257, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | A. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson |
Tester Architecture For The Source Synchronous Bus. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 738-747, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
35 | Rashid Rashidzadeh, Majid Ahmadi, William C. Miller |
A tester-on-chip implementation in 0.18µ CMOS utilizing a MEMS interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (5) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 561-564, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
35 | Atsushi Tagami, Teruyuki Hasegawa, Toru Hasegawa, Koji Nakao |
OC-48c traffic tester for generating and analyzing long-range dependence traffic. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCC ![In: Proceedings of the Seventh IEEE Symposium on Computers and Communications (ISCC 2002), 1-4 July 2002, Taormina, Italy, pp. 975-982, 2002, IEEE Computer Society, 0-7695-1671-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Achintya Halder, Abhijit Chatterjee, Pramodchandran N. Variyam, John Ridley |
Measuring Stray Capacitance on Tester Hardware. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 351-356, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Érika F. Cota, Luigi Carro, Marcelo Lubaszewski |
A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1999 Design, Automation and Test in Europe (DATE '99), 9-12 March 1999, Munich, Germany, pp. 184-188, 1999, IEEE Computer Society / ACM, 0-7695-0078-1. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
35 | Daniel P. Van der Velde, Ad J. van de Goor |
Designing a Memory Module Tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MTDT ![In: 7th IEEE International Workshop on Memory Technology, Design, and Testing (MTDT '99), August 9-10, 1999, San Jose, CA, USA, pp. 91-, 1999, IEEE Computer Society, 0-7695-0259-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
35 | Hideto Kayashima, Hideharu Amano |
TCI Tester: Tester for Through Chip Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, Tokyo, Japan, January 18-21, 2021, pp. 103-104, 2021, ACM, 978-1-4503-7999-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
35 | Masayuki Sato, Hiroki Wakamatsu, Masayuki Arai, Kenichi Ichino, Kazuhiko Iwasaki, Takeshi Asakawa |
Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Inf. Process. Syst. ![In: J. Inf. Process. Syst. 4(4), pp. 121-132, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
35 | Bill Bottoms, Lee Song, Paul Patton, Wilhelm Radermacher |
A Successful DFT Tester: What Will It Look Like? Is DFT Tester a Logical Next Step in ATE Evolution? ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 129-132, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
35 | Koji Nakamae, Takashi Ishimura, Hiromu Fujioka |
EB tester fault localization algorithm for combinational circuits by utilizing fault simulation and test pattern sequence for EB tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Syst. Comput. Jpn. ![In: Syst. Comput. Jpn. 31(8), pp. 41-48, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
35 | Hironobu Niijima, Yasuo Tokunaga, Shouichi Koshizuka, Kazuo Yakuwa, Péter Fazekas, Mathias Sturm, Hans-Peter Feuerbaum |
Electron Beam Tester Integrated into a VLSI Tester. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1988, Washington, D.C., USA, September 1988, pp. 908-913, 1988, IEEE Computer Society, 0-8186-0870-6. The full citation details ...](Pics/full.jpeg) |
1988 |
DBLP DOI BibTeX RDF |
|
35 | Robert L. Hickling |
Tester Independent Problem Representation and Tester Dependent Program Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings International Test Conference 1983, Philadelphia, PA, USA, October 1983, pp. 476-482, 1983, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
1983 |
DBLP BibTeX RDF |
|
29 | Scott Davidson 0001, Nur A. Touba |
Guest Editors' Introduction: Progress in Test Compression. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Des. Test Comput. ![In: IEEE Des. Test Comput. 25(2), pp. 112-113, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
tester memory, don't-care bits, X values, test compression, test vectors, test data volume |
29 | Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi 0001, Rubin A. Parekhji |
A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 26th IEEE VLSI Test Symposium (VTS 2008), April 27 - May 1, 2008, San Diego, California, USA, pp. 53-58, 2008, IEEE Computer Society, 978-0-7695-3123-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Tester, ATPG, Estimation, ATE, Test Time, Test Data Volume |
29 | Hacène Fouchal, Eric Petitjean, Sébastien Salva |
Testing timed systems with timed purposes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
RTCSA ![In: 7th International Workshop on Real-Time Computing and Applications Symposium (RTCSA 2000), 12-14 December 2000, Cheju Island, South Korea, pp. 166-171, 2000, IEEE Computer Society, 0-7695-0930-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
timed systems testing, timed purposes, timed counterpart, timed input/output automaton, canonical tester, protocols, conformance testing, time constraints, labeled transition system, automata theory |
29 | Zahari M. Darus, Iftekhar Ahmed 0003, Liakot Ali |
A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 155-, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
test processor chip, multiple polynomial linear feedback shift register, ASIC chip, scan-path testing, external IC tester, simulation, fault coverage, shift registers, pattern generator, multiple seed |
29 | Elaine J. Weyuker |
More Experience with Data Flow Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Software Eng. ![In: IEEE Trans. Software Eng. 19(9), pp. 912-919, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
Rapps-Weyuker data flow testing criteria, tester variability, cost assessment, data adequacy, software testing, fault detection, program testing, software cost estimation, data flow testing, numerical programs |
27 | Nicolas Bruno, Rimma V. Nehme |
Finding min-repros in database software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DBTest ![In: Proceedings of the 2nd International Workshop on Testing Database Systems, DBTest 2009, Providence, Rhode Island, USA, June 29, 2009, 2009, ACM, 978-1-60558-706-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
27 | Lili Pan 0002, Beiji Zou, Hao Chen 0051, Haoyu Zhou |
Research on Translucent Mechanism-Based Infeasible Path. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICYCS ![In: Proceedings of the 9th International Conference for Young Computer Scientists, ICYCS 2008, Zhang Jia Jie, Hunan, China, November 18-21, 2008, pp. 1076-1081, 2008, IEEE Computer Society, 978-0-7695-3398-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
27 | Anuja Sehgal, Krishnendu Chakrabarty |
Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 56(1), pp. 120-133, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Full-chip testing, dual-speed TAM, TAM optimization, test scheduling, test access mechanism, SOC testing |
27 | Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský |
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DFT ![In: 21th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2006), 4-6 October 2006, Arlington, Virginia, USA, pp. 300-308, 2006, IEEE Computer Society, 0-7695-2706-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
27 | Qiang Xu 0001, Nicola Nicolici |
Wrapper design for multifrequency IP cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(6), pp. 678-685, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Noga Alon, Asaf Shapira |
A Characterization of the (natural) Graph Properties Testable with One-Sided Error. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FOCS ![In: 46th Annual IEEE Symposium on Foundations of Computer Science (FOCS 2005), 23-25 October 2005, Pittsburgh, PA, USA, Proceedings, pp. 429-438, 2005, IEEE Computer Society, 0-7695-2468-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Abbas Tarhini, Hacène Fouchal |
Conformance Testing of Real-Time Component Based Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSADS ![In: Advanced Distributed Systems: 5th International School and Symposium, ISSADS 2005, Guadalajara, Mexico, January 24-28, 2005, Revised Selected Papers, pp. 167-181, 2005, Springer, 3-540-28063-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Abbas Tarhini, Antoine Rollet, Hacène Fouchal |
A pragmatic approach for testing robustness on real-time component based systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICCSA ![In: 2005 ACS / IEEE International Conference on Computer Systems and Applications (AICCSA 2005), January 3-6, 2005, Cairo, Egypt, pp. 143, 2005, IEEE Computer Society, 0-7803-8735-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Lei Li 0036, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan |
Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 18th International Conference on VLSI Design (VLSI Design 2005), with the 4th International Conference on Embedded Systems Design, 3-7 January 2005, Kolkata, India, pp. 53-58, 2005, IEEE Computer Society, 0-7695-2264-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Eldar Fischer, Lance Fortnow |
Tolerant Versus Intolerant Testing for Boolean Properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCC ![In: 20th Annual IEEE Conference on Computational Complexity (CCC 2005), 11-15 June 2005, San Jose, CA, USA, pp. 135-140, 2005, IEEE Computer Society, 0-7695-2364-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
27 | Irith Pomeranz |
Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(10), pp. 1465-1478, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Anuja Sehgal, Krishnendu Chakrabarty |
Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 422-427, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Harry M. Sneed |
Program Comprehension for the Purpose of Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWPC ![In: 12th International Workshop on Program Comprehension (IWPC 2004), 24-26 June 2004, Bari, Italy, pp. 162-171, 2004, IEEE Computer Society, 0-7695-2149-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
test documentation tools, testing, software comprehension, testing requirements |
27 | Martin Zambaldi, Wolfgang Ecker |
How to Bridge the Gap Between Simulationand Test. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2004 International Test Conference (ITC 2004), October 26-28, 2004, Charlotte, NC, USA, pp. 1091-1099, 2004, IEEE Computer Society, 0-7803-8581-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
27 | Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba |
An efficient test vector compression scheme using selective Huffman coding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(6), pp. 797-806, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Wenjing Rao, Alex Orailoglu |
Virtual Compression through Test Vector Stitching for Scan Based Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2003 Design, Automation and Test in Europe Conference and Exposition (DATE 2003), 3-7 March 2003, Munich, Germany, pp. 10104-10109, 2003, IEEE Computer Society, 0-7695-1870-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Irith Pomeranz |
Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ITC ![In: Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September - 3 October 2003, Charlotte, NC, USA, pp. 441-450, 2003, IEEE Computer Society, 0-7803-8106-8. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
27 | Lisa Crispin |
Test Drive for Testers: What, When, and How Testers Do for XP Teams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
XP/Agile Universe ![In: Extreme Programming and Agile Methods - XP/Agile Universe 2002, Second XP Universe and First Agile Universe Conference Chicago, IL, USA, August 4-7, 2002, Proceedings, pp. 277-278, 2002, Springer, 3-540-44024-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Sazzadur Chowdhury, Majid Ahmadi, Graham A. Jullien, William C. Miller |
A MEMS socket system for high density SoC interconnection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2002 International Symposium on Circuits and Systems, ISCAS 2002, Scottsdale, Arizona, USA, May 26-29, 2002, pp. 657-660, 2002, IEEE, 0-7803-7448-7. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
27 | Iboun Taimiya Sylla, Mustapha Slamani, Bozena Kaminska |
A Unity Gain High Speed Buffer to Improve Signal Integrity in High Frequency Test Interface. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 17(1), pp. 53-61, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
ATE interface, impedance matching, design for testability, high speed test |
27 | Nai-Yin Sung, Tsung-Yi Wu |
A Method of Embedded Memory Access Time Measurement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 2nd International Symposium on Quality of Electronic Design (ISQED 2001), 26-28 March 2001, San Jose, CA, USA, pp. 462-465, 2001, IEEE Computer Society, 0-7695-1025-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
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