Search results for "Tester"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
93	Jing-Reng Huang, Chee-Kian Ong, Kwang-Ting Cheng, Cheng-Wen Wu	An FPGA-based re-configurable functional tester for memory chips.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	re-configurable tester, memory chips, re-configurable hardware platform, prototype tester, compiler, integrated circuit testing, reconfigurable architectures, integrated memory circuits
73	Yuki Yamagata, Kenichi Ichino, Masayuki Arai, Satoshi Fukumoto, Kazuhiko Iwasaki, Masayuki Satoh, Hiroyuki Itabashi, Takashi Murai, Nobuyuki Otsuka	Implementation of Memory Tester Consisting of SRAM-Based Reconfigurable Cells.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	SRAM test, SRAM-based reconfigurable cell, memory tester, marching test
71	Yoshiyuki Nakamura, Thomas Clouqueur, Kewal K. Saluja, Hideo Fujiwara	Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
71	Matthieu Tuna, Mounir Benabdenbi, Alain Greiner	At-Speed Testing of Core-Based System-on-Chip Using an Embedded Micro-Tester.	VTS	2007	DBLP DOI BibTeX RDF
67	Intaik Park, Donghwi Lee, Erik Chmelar, Edward J. McCluskey	Inconsistent Fail due to Limited Tester Timing Accuracy.	VTS	2008	DBLP DOI BibTeX RDF	inconsistent fail, tester timing accuracy, tester EPA, delay test, inconsistency
62	Dana Moshkovitz, Ran Raz	Sub-constant error low degree test of almost-linear size.	STOC	2006	DBLP DOI BibTeX RDF	plane vs. point test, probabilistically checkable proofs, locally testable codes, low degree testing
62	Alexandre Petrenko, Nina Yevtushenko 0001, Jiale Huo	Testing Transition Systems with Input and Output Testers.	TestCom	2003	DBLP DOI BibTeX RDF	input/output transition system, test generation, fault model, conformance testing
62	Joan Feigenbaum, Sampath Kannan, Martin Strauss 0001, Mahesh Viswanathan 0001	Testing and Spot-Checking of Data Streams.	Algorithmica	2002	DBLP DOI BibTeX RDF
62	Abhijit Jas, Nur A. Touba	Deterministic Test Vector Compression/Decompression for Systems-on-a-Chip Using an Embedded Processor.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	test data compression, system-on-chip testing, deterministic testing
58	Vinay Verma, Shantanu Dutt, Vishal Suthar	Efficient on-line testing of FPGAs with provable diagnosabilities.	DAC	2004	DBLP DOI BibTeX RDF	built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability
55	Hiroshi Takahashi, Kwame Osei Boateng, Yuzo Takamatsu, Nobuhiro Yanagida	Multiple Fault Diagnosis in Logic Circuits Using EB Tester and Multiple/Single Fault Simulators.	Asian Test Symposium	1999	DBLP DOI BibTeX RDF	single/multiple fault simulators, EB tester, fault diagnosis, combinational circuit, multiple stuck-at fault
53	Paul Valiant	Testing symmetric properties of distributions.	STOC	2008	DBLP DOI BibTeX RDF	vandermonde matrices, continuity, property testing, distribution testing, multivariate statistics
53	Irit Dinur, Omer Reingold	Assignment Testers: Towards a Combinatorial Proof of the PCP-Theorem.	FOCS	2004	DBLP DOI BibTeX RDF
53	Robert W. Bassett, Barry J. Butkus, Stephen L. Dingle, Marc R. Faucher, Pamela S. Gillis, Jeannie H. Panner, John G. Petrovick, Donald L. Wheater	Low-Cost Testing of High-Density Logic Components.	IEEE Des. Test Comput.	1990	DBLP DOI BibTeX RDF
53	Lyl M. Ciganda, Francesco Abate, Paolo Bernardi, M. Bruno, Matteo Sonza Reorda	An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs.	DDECS	2009	DBLP DOI BibTeX RDF
53	David Money Harris, David Diaz	TestosterICs: A Low-Cost Functional Chip Tester.	MSE	2003	DBLP DOI BibTeX RDF
53	Juhana Helovuo, Antti Valmari	Checking for CFFD-Preorder with Tester Processes.	TACAS	2000	DBLP DOI BibTeX RDF
53	Nobuhiro Yanagida, Hiroshi Takahashi, Yuzo Takamatsu	Electron Beam Tester Aided Fault Diagnosis for Logic Circuits Based on Sensitized Paths.	Asian Test Symposium	1998	DBLP DOI BibTeX RDF
49	Irith Pomeranz, Sudhakar M. Reddy	On Test Compaction Objectives for Combinational and Sequential Circuits.	VLSI Design	1998	DBLP DOI BibTeX RDF	combinational circuits synchronous sequential circuits test compaction tester storage schemes tester memory requirements
47	Jae Wook Lee, Ji Hwan (Paul) Chun, Jacob A. Abraham	A delay measurement method using a shrinking clock signal.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	edge placement accuracy, tester, measurement, delay
47	Matthew L. Fichtenbaum, Gordon D. Robinson	Scan test architectures for digital board testers.	J. Electron. Test.	1991	DBLP DOI BibTeX RDF	tester architecture, scan, boundary scan
44	Angela Krstic, Kwang-Ting (Tim) Cheng, Srimat T. Chakradhar	Testing High Speed VLSI Devices Using Slower Testers.	VTS	1999	DBLP DOI BibTeX RDF
44	Xuefa Hu, Zhen Zhao 0004, Shu Wang, Fuli Wang, Dakuo He, Shui-kang Wu	Multi-stage extreme learning machine for fault diagnosis on hydraulic tube tester.	Neural Comput. Appl.	2008	DBLP DOI BibTeX RDF
44	Shu Wang, Xuefa Hu, Dakuo He, Fuli Wang	A Fault Diagnosis Method to Hydraulic Tube Tester Production Process.	FSKD (4)	2007	DBLP DOI BibTeX RDF
44	A. M. Majid, David C. Keezer, J. V. Karia	A 5 Gbps Wafer-Level Tester.	Asian Test Symposium	2005	DBLP DOI BibTeX RDF
44	Mark Litterick, Joachim Geishauser	Robust Vera Coding Techniques for Gate-Level and Tester-Compliant SoC Verification Environments.	MTV	2004	DBLP DOI BibTeX RDF
44	Maurizio Gavardoni	Data flow within an open architecture tester.	ITC	2003	DBLP DOI BibTeX RDF
44	Kazuhiro Yamada, Yoshikazu Takahashi	Vector Memory Expansion System For T33xx Logic Tester.	Asian Test Symposium	2002	DBLP DOI BibTeX RDF	T33XX LSSD vector pattern DFT
44	Junichi Hirase	Test Time Reduction through Minimum Execution of Tester-Hardware Setting Instructions.	Asian Test Symposium	2001	DBLP DOI BibTeX RDF
40	Vishal Suthar, Shantanu Dutt	High-diagnosability online built-in self-test of FPGAs via iterative bootstrapping.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	built-in self-tester (BISTer), roving tester (ROTE), FPGAs, functional testing, on-line testing, diagnosability
40	Ravi Kumar 0001, D. Sivakumar 0001	Efficient Self-Testing/Self-Correction of Linear Recurrences.	FOCS	1996	DBLP DOI BibTeX RDF	efficient self-testing, efficient self-correction, self-tester design, self-corrector design, result-checkers, linear function testing, counting arguments, matrix twist, convolution identities, VLSI chip testing, randomness-efficient self-tester, rational domains, signal processing, finite fields, program testing, polynomials, reduction, functions, spectral analysis, matrix groups, linear recurrences, control engineering
40	Kotaro Katsuyama, Fumiaki Sato, Tetsuo Nakakawaji, Tadanori Mizuno	Strategic Testing Environment with Formal Description Techniques.	IEEE Trans. Computers	1991	DBLP DOI BibTeX RDF	formal environment for systematic testing, stepwise approach, test development, TENT, test sequence generation tool, APRICOT, ASN.1 pre-compiler, coder, test-debugger, test specification editor, upper tester, lower tester, simulator, design, formal specification, protocol, protocols, data structures, programming environments, formal semantics, communication systems, formal description techniques, FOREST, test execution
38	Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei	A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices.	J. Electron. Test.	2005	DBLP DOI BibTeX RDF	timing specifications testing, test environment, tester OTA and yield, high-speed interconnect testing, yield analysis
38	Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov	Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing.	Asian Test Symposium	2003	DBLP DOI BibTeX RDF	Timing specifications testing, Test Environment, Tester OTA and yield, High-speed interconnect testing, Yield analysis
38	Hiroshi Takahashi, Nobuhiro Yanagida, Yuzo Takamatsu	Enhancing multiple fault diagnosis in combinational circuits based on sensitized paths and EB testing.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	electron beam testing, multiple fault diagnosis, sensitized paths, EB testing, TP-1, TP-2, TP-3, TP-4, electron-beam tester, internal lines, VLSI, fault diagnosis, logic testing, combinational circuits, combinational circuits, fault location, fault location, stuck-at faults, diagnostic resolution
38	Hyun Sook Rhee, Jong Hwan Park, Willy Susilo, Dong Hoon Lee 0001	Improved searchable public key encryption with designated tester.	AsiaCCS	2009	DBLP DOI BibTeX RDF	designated tester, public key encryption with keyword search, searchable encryption
38	Daniel G. Bobrow, J. Bruce Fraser	A phonological rule tester.	Commun. ACM	1968	DBLP DOI BibTeX RDF	format-directed list processing, on-line systems, phonology, rule tester, LISP, linguistics, transformational grammar
37	Kasper Johansen, Mitchell J. L. Morton, Yoann Malbéteau, Bruno Aragon, Samer Al-Mashharawi, Matteo G. Ziliani, Yoseline Angel, Gabriele Fiene, Sónia Negrão, Magdi A. A. Mousa, Mark A. Tester, Matthew F. McCabe	Predicting Biomass and Yield in a Tomato Phenotyping Experiment Using UAV Imagery and Random Forest.	Frontiers Artif. Intell.	2020	DBLP DOI BibTeX RDF
37	Maciej Lukawski, Jefferson W. Tester, Michal C. Moore, Pawel Król, C. Lindsay Anderson	Demand Response for Reducing Coincident Peak Loads in Data Centers.	HICSS	2019	DBLP BibTeX RDF
37	Uzma Tahir, Anthony L. Hessel, Eric R. Lockwood, John T. Tester, Zhixiu Han, Daniel J. Rivera, Kaitlyn L. Covey, Thomas G. Huck, Nicole A. Rice, Kiisa C. Nishikawa	Case Study: A Bio-Inspired Control Algorithm for a Robotic Foot-Ankle Prosthesis Provides Adaptive Control of Level Walking and Stair Ascent.	Frontiers Robotics AI	2018	DBLP DOI BibTeX RDF
37	Ben Ward, John W. Bastian, Anton van den Hengel, Daniel Pooley, Rajendra Bari, Bettina Berger, Mark A. Tester	A model-based approach to recovering the structure of a plant from images.	CoRR	2015	DBLP BibTeX RDF
37	Robert LeMoyne, Jeremy Petak, John T. Tester, Kiisa Nishikawa	Simulation of a computational winding filament model with an exponential spring to represent titin.	EMBC	2014	DBLP DOI BibTeX RDF
37	Ben Ward, John W. Bastian, Anton van den Hengel, Daniel Pooley, Rajendra Bari, Bettina Berger, Mark A. Tester	A Model-Based Approach to Recovering the Structure of a Plant from Images.	ECCV Workshops (4)	2014	DBLP DOI BibTeX RDF
37	Kristofer Tester, James W. Scrofani, Murali Tummala, David Garren, John C. McEachen	A spatiotemporal clustering approach to maritime domain awareness.	ICSPCS	2013	DBLP DOI BibTeX RDF
37	Darlene M. Tester	Book Review: Online Privacy: Issues in the Digital Age.	J. Digit. Forensics Secur. Law	2011	DBLP DOI BibTeX RDF
37	Kaijian Shi, David Tester	Well tapping methodologies in power-gating design.	SoCC	2011	DBLP DOI BibTeX RDF
37	Keith Tester	Book Review: The Ethics of Cyberspace.	New Media Soc.	2002	DBLP DOI BibTeX RDF
37	Jason Tester, B. J. Fogg, Michael Maile	CommuterNews: a prototype of persuasive in-car entertainment.	CHI Extended Abstracts	2000	DBLP DOI BibTeX RDF
37	Phillip King, Jason Tester	The Landscape of Persuasive Technologies.	Commun. ACM	1999	DBLP DOI BibTeX RDF
37	B. J. Fogg, Daniel Bedichevsky, Jason Tester	Persuasive computing.	ACM SIGCHI Bull.	1998	DBLP DOI BibTeX RDF
37	B. Kobrinsky, I. Tester, N. Demikova, Yu. Sedov, B. Marjanchik, L. Taperova, Yu. Glukhovskaya, M. Podolnaja	A Multifunctional System of the National Genetic Register.	MedInfo	1998	DBLP DOI BibTeX RDF
36	Eli Ben-Sasson, Michael Viderman	Composition of Semi-LTCs by Two-Wise Tensor Products.	APPROX-RANDOM	2009	DBLP DOI BibTeX RDF
36	Eldar Fischer, Frédéric Magniez, Michel de Rougemont	Approximate Satisfiability and Equivalence.	LICS	2006	DBLP DOI BibTeX RDF
36	Mircea Popa 0001, Voicu Groza, Alina Botas	Lin Bus Testing Software.	CCECE	2006	DBLP DOI BibTeX RDF
36	C. V. Krishna, Nur A. Touba	Hybrid BIST Using an Incrementally Guided LFSR.	DFT	2003	DBLP DOI BibTeX RDF
36	Ananta K. Majhi, Guido Gronthoud, Camelia Hora, Maurice Lousberg, Pop Valer, Stefan Eichenberger	Improving Diagnostic Resolution of Delay Faults using Path Delay Fault Model.	VTS	2003	DBLP DOI BibTeX RDF
36	Ken Auer, Ron Jeffries, Jeff Canna, Glen B. Alleman, Lisa Crispin, Janet Gregory 0002	Are Testers eXtinct? How Can Testers Contribute to XP Teams?	XP/Agile Universe	2002	DBLP DOI BibTeX RDF
36	Abhijit Jas, Nur A. Touba	Using an Embedded Processor for Efficient Deterministic Testing of Systems-on-a-Chip.	ICCD	1999	DBLP DOI BibTeX RDF	Test Vector Compression, External Testing, Built-In Self-Test, Embedded Processor, System-on-a-Chip, Automatic Test Equipment, At-Speed Testing, Scan Chains, Deterministic Testing
36	Abhijit Jas, Nur A. Touba	Test vector decompression via cyclical scan chains and its application to testing core-based designs.	ITC	1998	DBLP DOI BibTeX RDF
35	Wai Han Ho, Paul Andrew Watters, Dominic R. Verity	Robustness of the New Owner-Tester Approach for Face Identification Experiments.	CVPR	2007	DBLP DOI BibTeX RDF
35	Jüri Vain, Kullo Raiend, Andres Kull, Juhan P. Ernits	Synthesis of test purpose directed reactive planning tester for nondeterministic systems.	ASE	2007	DBLP DOI BibTeX RDF	nondeterministic extended finite state machine, reactive planning, model-based testing, online testing
35	Vinay Verma, Shantanu Dutt	Roving testing using new built-in-self-tester designs for FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF
35	A. T. Sivaram, Masashi Shimanouchi, Howard Maassen, Robert Jackson	Tester Architecture For The Source Synchronous Bus.	ITC	2004	DBLP DOI BibTeX RDF
35	Rashid Rashidzadeh, Majid Ahmadi, William C. Miller	A tester-on-chip implementation in 0.18µ CMOS utilizing a MEMS interface.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
35	Atsushi Tagami, Teruyuki Hasegawa, Toru Hasegawa, Koji Nakao	OC-48c traffic tester for generating and analyzing long-range dependence traffic.	ISCC	2002	DBLP DOI BibTeX RDF
35	Achintya Halder, Abhijit Chatterjee, Pramodchandran N. Variyam, John Ridley	Measuring Stray Capacitance on Tester Hardware.	VTS	2002	DBLP DOI BibTeX RDF
35	Érika F. Cota, Luigi Carro, Marcelo Lubaszewski	A Method to Diagnose Faults in Linear Analog Circuits using an Adaptive Tester.	DATE	1999	DBLP DOI BibTeX RDF
35	Daniel P. Van der Velde, Ad J. van de Goor	Designing a Memory Module Tester.	MTDT	1999	DBLP DOI BibTeX RDF
35	Hideto Kayashima, Hideharu Amano	TCI Tester: Tester for Through Chip Interface.	ASP-DAC	2021	DBLP DOI BibTeX RDF
35	Masayuki Sato, Hiroki Wakamatsu, Masayuki Arai, Kenichi Ichino, Kazuhiko Iwasaki, Takeshi Asakawa	Tester Structure Expression Language and Its Application to the Environment for VLSI Tester Program Development.	J. Inf. Process. Syst.	2008	DBLP DOI BibTeX RDF
35	Bill Bottoms, Lee Song, Paul Patton, Wilhelm Radermacher	A Successful DFT Tester: What Will It Look Like? Is DFT Tester a Logical Next Step in ATE Evolution?	VTS	2002	DBLP DOI BibTeX RDF
35	Koji Nakamae, Takashi Ishimura, Hiromu Fujioka	EB tester fault localization algorithm for combinational circuits by utilizing fault simulation and test pattern sequence for EB tester.	Syst. Comput. Jpn.	2000	DBLP DOI BibTeX RDF
35	Hironobu Niijima, Yasuo Tokunaga, Shouichi Koshizuka, Kazuo Yakuwa, Péter Fazekas, Mathias Sturm, Hans-Peter Feuerbaum	Electron Beam Tester Integrated into a VLSI Tester.	ITC	1988	DBLP DOI BibTeX RDF
35	Robert L. Hickling	Tester Independent Problem Representation and Tester Dependent Program Generation.	ITC	1983	DBLP BibTeX RDF
29	Scott Davidson 0001, Nur A. Touba	Guest Editors' Introduction: Progress in Test Compression.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	tester memory, don't-care bits, X values, test compression, test vectors, test data volume
29	Rajesh Tiwari, Abhijeet Shrivastava, Mahit Warhadpande, Srivaths Ravi 0001, Rubin A. Parekhji	A Regression Based Technique for ATE-Aware Test Data Volume Estimation of System-on-Chips.	VTS	2008	DBLP DOI BibTeX RDF	Tester, ATPG, Estimation, ATE, Test Time, Test Data Volume
29	Hacène Fouchal, Eric Petitjean, Sébastien Salva	Testing timed systems with timed purposes.	RTCSA	2000	DBLP DOI BibTeX RDF	timed systems testing, timed purposes, timed counterpart, timed input/output automaton, canonical tester, protocols, conformance testing, time constraints, labeled transition system, automata theory
29	Zahari M. Darus, Iftekhar Ahmed 0003, Liakot Ali	A test processor chip implementing multiple seed, multiple polynomial linear feedback shift register.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	test processor chip, multiple polynomial linear feedback shift register, ASIC chip, scan-path testing, external IC tester, simulation, fault coverage, shift registers, pattern generator, multiple seed
29	Elaine J. Weyuker	More Experience with Data Flow Testing.	IEEE Trans. Software Eng.	1993	DBLP DOI BibTeX RDF	Rapps-Weyuker data flow testing criteria, tester variability, cost assessment, data adequacy, software testing, fault detection, program testing, software cost estimation, data flow testing, numerical programs
27	Nicolas Bruno, Rimma V. Nehme	Finding min-repros in database software.	DBTest	2009	DBLP DOI BibTeX RDF
27	Lili Pan 0002, Beiji Zou, Hao Chen 0051, Haoyu Zhou	Research on Translucent Mechanism-Based Infeasible Path.	ICYCS	2008	DBLP DOI BibTeX RDF
27	Anuja Sehgal, Krishnendu Chakrabarty	Optimization of Dual-Speed TAM Architectures for Efficient Modular Testing of SOCs.	IEEE Trans. Computers	2007	DBLP DOI BibTeX RDF	Full-chip testing, dual-speed TAM, TAM optimization, test scheduling, test access mechanism, SOC testing
27	Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský	Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead.	DFT	2006	DBLP DOI BibTeX RDF
27	Qiang Xu 0001, Nicola Nicolici	Wrapper design for multifrequency IP cores.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
27	Noga Alon, Asaf Shapira	A Characterization of the (natural) Graph Properties Testable with One-Sided Error.	FOCS	2005	DBLP DOI BibTeX RDF
27	Abbas Tarhini, Hacène Fouchal	Conformance Testing of Real-Time Component Based Systems.	ISSADS	2005	DBLP DOI BibTeX RDF
27	Abbas Tarhini, Antoine Rollet, Hacène Fouchal	A pragmatic approach for testing robustness on real-time component based systems.	AICCSA	2005	DBLP DOI BibTeX RDF
27	Lei Li 0036, Krishnendu Chakrabarty, Seiji Kajihara, Shivakumar Swaminathan	Efficient Space/Time Compression to Reduce Test Data Volume and Testing Time for IP Cores.	VLSI Design	2005	DBLP DOI BibTeX RDF
27	Eldar Fischer, Lance Fortnow	Tolerant Versus Intolerant Testing for Boolean Properties.	CCC	2005	DBLP DOI BibTeX RDF
27	Irith Pomeranz	Reducing test-data volume using P-testable scan chains in circuits with multiple scan chains.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
27	Anuja Sehgal, Krishnendu Chakrabarty	Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures.	DATE	2004	DBLP DOI BibTeX RDF
27	Harry M. Sneed	Program Comprehension for the Purpose of Testing.	IWPC	2004	DBLP DOI BibTeX RDF	test documentation tools, testing, software comprehension, testing requirements
27	Martin Zambaldi, Wolfgang Ecker	How to Bridge the Gap Between Simulationand Test.	ITC	2004	DBLP DOI BibTeX RDF
27	Abhijit Jas, Jayabrata Ghosh-Dastidar, Mom-Eng Ng, Nur A. Touba	An efficient test vector compression scheme using selective Huffman coding.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
27	Wenjing Rao, Alex Orailoglu	Virtual Compression through Test Vector Stitching for Scan Based Designs.	DATE	2003	DBLP DOI BibTeX RDF
27	Irith Pomeranz	Reducing Test Data Volume Using Random-Testable and Periodic-Testable Scan Chains in Circuits with Multiple Scan Chains.	ITC	2003	DBLP DOI BibTeX RDF
27	Lisa Crispin	Test Drive for Testers: What, When, and How Testers Do for XP Teams.	XP/Agile Universe	2002	DBLP DOI BibTeX RDF
27	Sazzadur Chowdhury, Majid Ahmadi, Graham A. Jullien, William C. Miller	A MEMS socket system for high density SoC interconnection.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
27	Iboun Taimiya Sylla, Mustapha Slamani, Bozena Kaminska	A Unity Gain High Speed Buffer to Improve Signal Integrity in High Frequency Test Interface.	J. Electron. Test.	2001	DBLP DOI BibTeX RDF	ATE interface, impedance matching, design for testability, high speed test
27	Nai-Yin Sung, Tsung-Yi Wu	A Method of Embedded Memory Access Time Measurement.	ISQED	2001	DBLP DOI BibTeX RDF