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Searching for phrase Verilog-HDL (changed automatically) with no syntactic query expansion in all metadata.

Publication years (Num. hits)
1993-2000 (16) 2001-2003 (20) 2004-2005 (17) 2006-2007 (31) 2008-2010 (18) 2014-2022 (16) 2023 (2)
Publication types (Num. hits)
article(19) book(2) inproceedings(97) phdthesis(2)
Venues (Conferences, Journals, ...)
J. VLSI Signal Process.(5) ICCD(3) ISCAS(3) AHS(2) ARC(2) ASP-DAC(2) CoRR(2) DAC(2) DSD(2) FPGA(2) HIS (1)(2) IC3I(2) IEEE Trans. Very Large Scale I...(2) ISCAS (2)(2) ISCAS (4)(2) MSE(2) More (+10 of total 94)
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The graphs summarize 85 occurrences of 67 keywords

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Found 120 publication records. Showing 120 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
78Lin Yuan, Pushkin R. Pari, Gang Qu 0001 Soft IP Protection: Watermarking HDL Codes. Search on Bibsonomy Information Hiding The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
77Peter A. Jamieson, Kenneth B. Kent Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only). Search on Bibsonomy FPGA The full citation details ... 2010 DBLP  DOI  BibTeX  RDF fpga, verilog hdl
75Arash Saifhashemi, Hossein Pedram Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction. Search on Bibsonomy DAC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF CHP, PLI, CSP, asynchronous circuits, channel, verilog
68Shengchao Qin, Jifeng He 0001, Zongyan Qiu, Naixiao Zhang Hardware/Software Partitioning in Verilog. Search on Bibsonomy ICFEM The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
66Ivan Blunno, Luciano Lavagno Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL. Search on Bibsonomy ASYNC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
59Choudhury A. Rahman, Wael M. Badawy A quarter pel full search block motion estimation architecture for H.264/AVC. Search on Bibsonomy ICME The full citation details ... 2005 DBLP  DOI  BibTeX  RDF CIF frame sequence, quarter pel full search, block motion estimation architecture, H.264-AVC encoder, Xilinx Virtex2 FPGA, field programmable gate array, hardware description language, Verilog HDL
49Raik Brinkmann, Rolf Drechsler RTL-Datapath Verification using Integer Linear Programming. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
49Richard Goering, Clifford E. Cummings, Steven E. Schulz, Simon Davidman, John Sanguinetti, Joachim Kunkel, Oz Levia The future of system design languages (panel session). Search on Bibsonomy DAC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
40Xiumin Wang, Yang Zhang, Qiang Ye, Shihua Yang A New Algorithm for Designing Square Root Calculators Based on FPGA with Pipeline Technology. Search on Bibsonomy HIS (1) The full citation details ... 2009 DBLP  DOI  BibTeX  RDF FPGA, algorithm, pipeline, square root, Verilog HDL
40Yang Zhang, Xiumin Wang, Yuduo Wang A New Design of HDB3 Encoder and Decoder Based on FPGA. Search on Bibsonomy HIS (1) The full citation details ... 2009 DBLP  DOI  BibTeX  RDF HDB3, FPGA, encoder, decoder, Verilog HDL
40Takao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto System-Level Design of IEEE1394 Bus Segment Bridge. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF HW/SW co-simulation, IEEE1394, PLI, bus bridge, C/C++, verilog-HDL
40Marcel Jacomet, Roger Wälti, Lukas Winzenried, Jaime Perez, Martin Gysel ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAs. Search on Bibsonomy Asian Test Symposium The full citation details ... 1997 DBLP  DOI  BibTeX  RDF test bench, test machine, CAT-tool, ProTest, FPGA, VHDL, rapid prototyping, Verilog-HDL
39Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti 0001, Vivekananda M. Vedula, K. S. Maneperambil Automatic Constraint Based Test Generation for Behavioral HDL Models. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
39Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits. Search on Bibsonomy IWDC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
39John A. Nestor Teaching Computer Organization with HDLs: An Incremental Approach. Search on Bibsonomy MSE The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
39Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems. Search on Bibsonomy ISPDC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
37Anik Mallik, Sanjoy Kundu, Md. Ashikur Rahman An FPGA-Based Semi-Automated Traffic Control System Using Verilog HDL. Search on Bibsonomy CoRR The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
37Lekshmi S. Ajay, Sreenidhi Prabha Rajeev Comparative Analysis of Data Compression using Canonical Huffman and Golomb Rice Encoding in Verilog HDL and Implementation in FPGA. Search on Bibsonomy ICCCNT The full citation details ... 2023 DBLP  DOI  BibTeX  RDF
37Pawel Szczepankowski, Wojciech Sleszynski, Tomasz Bajdecki A Direct Modulation for Matrix Converters Based on the One-Cycle Atomic Operation Developed in Verilog HDL. Search on Bibsonomy IEEE Trans. Ind. Electron. The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
37K. N. Raja Praveen, Gadug Sudhamsu Using AIG in Verilog HDL, Autonomous Testing in a Family of Wien Bridge Cross Transducers. Search on Bibsonomy IC3I The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
37K. N. Raja Praveen, Gadug Sudhamsu Using AIG in Verilog HDL, Autonomous Testing in a Family of Wien Bridge Cross Transducers. Search on Bibsonomy IC3I The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
37Hye-Hyun Lee, Yeon-Seob Song, Kang-Yoon Lee Modeling of nano-scale PLL using Verilog HDL. Search on Bibsonomy ICTC The full citation details ... 2022 DBLP  DOI  BibTeX  RDF
37Jin-Yang Lai, Chiung-An Chen, Shih-Lun Chen, Chun-Yu Su Implement 32-bit RISC-V Architecture Processor using Verilog HDL. Search on Bibsonomy ISPACS The full citation details ... 2021 DBLP  DOI  BibTeX  RDF
37Peter Flake, Phil Moorby, Steve Golson, Arturo Salz, Simon J. Davidmann Verilog HDL and its ancestors and descendants. Search on Bibsonomy Proc. ACM Program. Lang. The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
37Junya Miura, Hiromu Miyazaki, Kenji Kise A portable and Linux capable RISC-V computer system in Verilog HDL. Search on Bibsonomy CoRR The full citation details ... 2020 DBLP  BibTeX  RDF
37Guo-Ming Sung, Chun-Ting Lee, Chao-Rong Chen IoT-Based Home Care System with a FPGA Development Board by Using RS-485 Interface and Verilog HDL. Search on Bibsonomy SMC The full citation details ... 2020 DBLP  DOI  BibTeX  RDF
37Abdul Rafay Khatri, Ali Hayek, Josef Börcsök Validation of the Proposed Fault Injection, Test and Hardness Analysis for Combinational Data-Flow Verilog HDL Designs Under the RASP-FIT Tool. Search on Bibsonomy DASC/PiCom/DataCom/CyberSciTech The full citation details ... 2018 DBLP  DOI  BibTeX  RDF
37Mo Qiu, Simin Yu, Yuqiong Wen, Jinhu Lü, Jianbin He, Zhuosheng Lin Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control. Search on Bibsonomy Int. J. Bifurc. Chaos The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
37Bei Cao, Tianliang Xu, Pengfei Wu RSA Encryption Algorithm Design and Verification Based on Verilog HDL. Search on Bibsonomy MLICOM (1) The full citation details ... 2017 DBLP  DOI  BibTeX  RDF
37Ryohei Kobayashi, Tomohiro Misono, Kenji Kise A High-speed Verilog HDL Simulation Method using a Lightweight Translator. Search on Bibsonomy SIGARCH Comput. Archit. News The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
37Zbigniew Jaworski Verilog HDL model based thermometer-to-binary encoder with bubble error correction. Search on Bibsonomy MIXDES The full citation details ... 2016 DBLP  DOI  BibTeX  RDF
37Shinya Takamaeda-Yamazaki Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL. Search on Bibsonomy ARC The full citation details ... 2015 DBLP  DOI  BibTeX  RDF
37Tze Sin Tan, Bakhtiar Affendi Rosdi Verilog HDL Simulator Technology: A Survey. Search on Bibsonomy J. Electron. Test. The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
37Tariq B. Ahmad, Maciej J. Ciesielski Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning. Search on Bibsonomy ISVLSI The full citation details ... 2014 DBLP  DOI  BibTeX  RDF
37Rosario M. Reas, Anastacia B. Alvarez, Joy Alinda P. Reyes Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL. Search on Bibsonomy UKSim The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
37Peter Jamieson, Kenneth B. Kent, Farnaz Gharibian, Lesley Shannon Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research. Search on Bibsonomy FCCM The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
37Adam Duley, Chris Spandikow, Miryung Kim A program differencing algorithm for verilog HDL. Search on Bibsonomy ASE The full citation details ... 2010 DBLP  DOI  BibTeX  RDF
37Mohammad Shokrollah-Shirazi, Seyed Ghassem Miremadi FPGA-Based Fault Injection into Synthesizable Verilog HDL Models. Search on Bibsonomy SSIRI The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
37Robert B. Reese, Mitchell A. Thornton Introduction to Logic Synthesis using Verilog HDL Search on Bibsonomy 2006   DOI  RDF
37Mile K. Stojcev Digital Computer Arithmetic Datapath Design Using Verilog HDL, James E. Stine, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7710-6. Hardcover, pp 180, plus XI. Search on Bibsonomy Microelectron. Reliab. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
37Jordan Dimitriov Developing semantics of Verilog HDL in formal compositional design of mixed hardware/software systems. Search on Bibsonomy 2002   RDF
37Daniel C. Hyde Using verilog HDL to teach computer architecture concepts. Search on Bibsonomy WCAE@ISCA The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
37Gordon G. Pace Hardware design based on Verilog HDL. Search on Bibsonomy 1998   RDF
37Ulrich Golze VLSI-Entwurf eines RISC-Prozessors - eine Einführung in das Design großer Chips und die Hardware-Beschreibungssprache VERILOG HDL. Search on Bibsonomy 1995   RDF
37Michael J. C. Gordon The Semantic Challenge of Verilog HDL Search on Bibsonomy LICS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
37Felice Balarin, Gary York Verilog HDL Modeling Styles for Formal Verification. Search on Bibsonomy CHDL The full citation details ... 1993 DBLP  BibTeX  RDF
29Yan Lin Aung, Douglas L. Maskell, Timothy F. Oliver, Bertil Schmidt, William Bong C-Based Design Methodology for FPGA Implementation of ClustalW MSA. Search on Bibsonomy PRIB The full citation details ... 2007 DBLP  DOI  BibTeX  RDF ClustalW, FPGA, multiple sequence alignment, sequence analysis
29Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Navid Farazmand Assessment of Message Missing Failures in FlexRay-Based Networks. Search on Bibsonomy PRDC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Ryuichi Takahashi, Noriyoshi Yoshida Diagonal Examples for Design Space Exploration in an Educational Environment CITY-1. Search on Bibsonomy MSE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
29Ilker Hamzaoglu, Ozgur Tasdizen, Esra Sahin An efficient H.264 intra frame coder system design. Search on Bibsonomy VLSI-SoC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Esra Sahin, Ilker Hamzaoglu Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Esra Sahin, Ilker Hamzaoglu An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding. Search on Bibsonomy DSD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Serkan Oktem, Ilker Hamzaoglu An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation. Search on Bibsonomy DSD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick D. Wolf Design Methodology and CAD Tools for Prototyping Delta-Sigma Fractional-N Frequency Synthesizers. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
29Sinan Yalcin, Ilker Hamzaoglu A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Mustafa Parlak, Ilker Hamzaoglu An Efficient Hardware Architecture for H.264 Adaptive Deblocking Filter. Search on Bibsonomy AHS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
29Ivan Blunno, Luciano Lavagno Designing an Asynchronous Microcontroller Using Pipefitter. Search on Bibsonomy ICCD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
29Jordan Dimitrov Operational Semantics for Verilog. Search on Bibsonomy APSEC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
29Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò Gate-level power and current simulation of CMOS integrated circuits. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF
19Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner Fpga-based face detection system using Haar classifiers. Search on Bibsonomy FPGA The full citation details ... 2009 DBLP  DOI  BibTeX  RDF haar classifier, fpga, image processing, real-time, architecture, face detection, adaboost
19Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm. Search on Bibsonomy ARC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Block Cipher Algorithm, Field Programmable Gate Arrays (FPGA), Cryptography, SEED
19Chun-Lung Hsu, Yu-Sheng Huang A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FDBS, H.264/AVC, PSNR, bit-rate, deblocking filter
19Christian Haufe, Frank Rogin Ad-Hoc Translations to Close Verilog Semantics Gap. Search on Bibsonomy DDECS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
19Jaume Joven, Oriol Font-Bach, David Castells-Rufas, Ricardo Martínez, Lluís Terés, Jordi Carrabina xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures. Search on Bibsonomy PDP The full citation details ... 2008 DBLP  DOI  BibTeX  RDF NoC-based MPSoCs, Message Passing Interface, Distributed Programming, Design Tools and Techniques
19Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi Fault Effects in FlexRay-Based Networks with Hybrid Topology. Search on Bibsonomy ARES The full citation details ... 2008 DBLP  DOI  BibTeX  RDF FlexRay Protocol, Fault Injection, Error Propagation, Distributed Embedded Systems, Dependability Evaluation
19Ruchika Verma, Ali Akoglu A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation. Search on Bibsonomy IPDPS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
19Miaoqing Huang, Kris Gaj, Soonhak Kwon, Tarek A. El-Ghazawi An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm. Search on Bibsonomy Public Key Cryptography The full citation details ... 2008 DBLP  DOI  BibTeX  RDF MWR2MM Algorithm, Field Programmable Gate Arrays, Montgomery Multiplication
19Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, Yasuaki Ito A Tiny Processing System for Education and Small Embedded Systems on the FPGAs. Search on Bibsonomy EUC (2) The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
19Shahid Rizwan Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding. Search on Bibsonomy VLSI Design The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
19Xiang Xiao, Jaehwan John Lee A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip. Search on Bibsonomy IEEE Comput. Archit. Lett. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
19Maria Stepanova, Feng Lin 0002, Valerie C.-L. Lin A Hopfield Neural Classifier and Its FPGA Implementation for Identification of Symmetrically Structured DNA Motifs. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF DNA motifs, sequence structure identification, hopfield classifier, field-programmable gate arrays, recurrent neural network
19Muhammad T. Anan, Ghulam M. Chaudhry A Real-Time Hardware-Based Scheduler For Next-Generation Optical Burst Switches. Search on Bibsonomy ICC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
19Xiao Hu, Pengyong Ma, Shuming Chen Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor. Search on Bibsonomy ICESS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
19Jin-Oh Jeon, Su-Bong Ryu, Tae-Min Chang, Ho-Yong Choi, Min-Sup Kang Digital Codec Design for RFID Tag Based on Cryptographic Authentication Protocol. Search on Bibsonomy FGCN (2) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
19Ik-Jae Chun, Tae Moon Roh, Bo-Gwan Kim Binary-Truncated CDMA-Based On-Chip Network. Search on Bibsonomy ISCAS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
19Jun Wang 0010, Kyeong-Yuk Min, Jong-Wha Chong A Hybrid Image Coding in Overdriving for Motion Blur Reduction in LCD. Search on Bibsonomy ICEC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Overdriving, Block Truncation Coding, Adaptive Quantization Coding, Compression, LCD, Motion blur
19Mustafa Parlak, Ilker Hamzaoglu A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm. Search on Bibsonomy AHS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
19Jin-Oh Jeon, Su-Bong Ryu, Sang-Jo Park, Min-Sup Kang Strong Authentication Protocol for RFID Tag Using SHA-1 Hash Algorithm. Search on Bibsonomy ICCSA (1) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Strong authentication protocol, SHA-1 hash algorithm, Three-way challenge response, ISO/IEC 1800-3 standard, Digital Codec design, RFID Tag
19Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong An Efficient VLSI Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC. Search on Bibsonomy MMM (2) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF VBSME, VLSI, motion estimation, H.264/AVC, block matching algorithm
19Jaehwan John Lee, Vincent John Mooney A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Parallel Banker's Algorithm, deadlock avoidance in hardware, multiprocessor system-on-a-chip
19Alexander Kamkin The UniTESK Approach to Specification-Based Validation of Hardware Designs. Search on Bibsonomy ISoLA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
19Baofeng Li, Qiang Shao Deeply Parallel Architecture for Lifting-Based 2D DWT in JPEG2000. Search on Bibsonomy CIT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
19Choudhury A. Rahman, Wael M. Badawy An Area Efficient Real-time CAVLC IP-Block towards the H.264/AVC Encoder. Search on Bibsonomy SiPS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
19Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong, Satoshi Goto An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC. Search on Bibsonomy ISVC (2) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
19Zude Zhou, Songlin Cheng, Quan Liu Application of DDR Controller for High-speed Data Acquisition Board. Search on Bibsonomy ICICIC (2) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
19Pawel Garstecki, Adam Luczak, Marta Stepniewska A bit-serial implementation of mode decision algorithm for AVC encoders. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
19Kimo Kim, In-Cheol Park Combined image signal processing for CMOS image sensors. Search on Bibsonomy ISCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
19Junhao Zheng, Di Wu 0022, Lei Deng 0007, Don Xie, Wen Gao 0001 A Motion Vector Predictor Architecture for AVS and MPEG-2 HDTV Decoder. Search on Bibsonomy PCM The full citation details ... 2006 DBLP  DOI  BibTeX  RDF Motion vector prediction, MPEG, Motion compensation, VLSI architecture, AVS
19Wonwoo Jang, Hyunsik Kim, Sungmok Lee, Jooyoung Ha, Bongsoon Kang Implementation of the Gamma Line System Similar to Non-linear Gamma Curve with 2bit Error(LSB). Search on Bibsonomy APCCAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
19Insu Song, Guido Governatori Designing agent chips. Search on Bibsonomy AAMAS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF agent chips, agent architecture, agent programming languages
19Jung L. Lee, Myung Hoon Sunwoo Implementation of a Wireless Multimedia DSP Chip for Mobile Applications. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF multimedia, DSP, instruction
19Saranyan A. Vigraham, John C. Gallagher A space saving digital VLSI evolutionary engine for CTRNN-EH devices. Search on Bibsonomy Congress on Evolutionary Computation The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
19Jaehwan John Lee, Vincent John Mooney III A novel O(n) parallel banker's algorithm for System-on-a-Chip. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
19Mathias Halbach, Rolf Hoffmann Optimal Behavior of a Moving Creature in the Cellular Automata Model. Search on Bibsonomy PaCT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
19Gyu-Sung Yeon, Chi-Hun Jun, Tae-Jin Hwang, Seongsoo Lee, Jae-Kyung Wee Low-Power MPEG-4 Motion Estimator Design for Deep Sub-Micron Multimedia SoC. Search on Bibsonomy KES (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
19Hua Li, Jianzhou Li A High Performance Sub-Pipelined Architecture for AES. Search on Bibsonomy ICCD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF sub-pipelined architecture, FPGA, cryptography, AES
19Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch Design of superscalar processor with multi-bank register file. Search on Bibsonomy ISCAS (4) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
19Yasuhiro Takahashi, Michio Yokoyama New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination. Search on Bibsonomy ISCAS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
19Donghyun Kim, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip. Search on Bibsonomy ISCAS (3) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
19Ping Dong, Xiangdong Shi, Jiehui Yang Design of a New Kind of Encryption Kernel Based on RSA Algorithm. Search on Bibsonomy CIS (2) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
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