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Found 14725 publication records. Showing 14699 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
102Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, I. P. Hsu, J.-Y. Chen Design theory and implementation for low-power segmented bus systems. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF OLA tree, bus graph model, bus segmentation, bus segmentation cell, low-power design flow, low-power design, ASIC design
95Kyeong Keol Ryu, Vincent John Mooney Automated Bus Generation for Multiprocessor SoC Design. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
94Bo-Shiun Wu, Tsung-Yi Ho Bus-pin-aware bus-driven floorplanning. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2010 DBLP  DOI  BibTeX  RDF bus planning, floorplanning
92Hon Wai Chun A distributed constraint-based search architecture for bus timetabling and duty assignment. Search on Bibsonomy APSEC The full citation details ... 1997 DBLP  DOI  BibTeX  RDF distributed constraint-based search architecture, bus timetabling, duty assignment, bus company, bus assignment, driver assignment, bus driver resource allocation, labour constraints, scheduling, software prototype, service industries
92Michael S. Allen, W. Kurt Lewchuk, J. D. Coddington A high performance bus and cache controller for PowerPC multiprocessing systems. Search on Bibsonomy ICCD The full citation details ... 1995 DBLP  DOI  BibTeX  RDF high performance bus, cache controller, PowerPC 620 microprocessor, system bus interface, ECC protected, server-class systems, physical address bus, data bus, address transfer rates, address snoop response, direct cache-to-cache data transfers, 2 GByte/s, 133 MHz, 128 MB, performance evaluation, pipelining, multiprocessing systems, multiprocessing systems, pipeline processing, cache storage, microprocessor chips, coprocessors, cache coherency protocol, data transfer, PowerPC, system buses, co-processor
86Je-Hoon Lee, Young-Sin Cho, Seok-Man Kim, Kyoung-Rok Cho On-Chip Bus Modeling for Power and Performance Estimation. Search on Bibsonomy SAMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF bus modeling, bus latency, SoC, on-chip bus
84Alexandre Brandwajn A note on SCSI bus waits. Search on Bibsonomy SIGMETRICS Perform. Evaluation Rev. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
83Tadaaki Tanimoto, Seiji Yamaguchi, Akio Nakata, Teruo Higashino A real time budgeting method for module-level-pipelined bus based system using bus scenarios. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF bus based systems, cycle budgeting, real-time systems, pipelined processing, multimedia processing
81Yasumasa Hayashi, Takashi Matsubara 0002, Yoshiaki Koga Implementation and evaluation for dependable bus control using CPLD. Search on Bibsonomy PRDC The full citation details ... 2000 DBLP  DOI  BibTeX  RDF phase control, dependable bus control, bus systems, dependable bus operations, bus phase control, reliability, dependability, sequential circuits, system buses, CPLD, asynchronous sequential logic, asynchronous sequential circuit
80Kazunori Toshioka, Takao Kawamura, Kazunori Sugahara Web Application to Generate Route Bus Timetables. Search on Bibsonomy ICIW The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Bus Timetable, Bus route system, web application
79Ruibing Lu, Aiqun Cao, Cheng-Kok Koh Improving the scalability of SAMBA bus architecture. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
79Kyeong Keol Ryu, Vincent John Mooney III Automated bus generation for multiprocessor SoC design. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
78Ke Ning, David R. Kaeli Bus Power Estimation and Power-Efficient Bus Arbitration for System-on-a-Chip Embedded Systems. Search on Bibsonomy PACS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Embedded System, Power-Aware, External Memory, Media Processor, Bus Arbitration
78Ruibing Lu, Aiqun Cao, Cheng-Kok Koh SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
78Seiichi Saito A novel analysis method of bus signal transmission and a proposal for high-speed low-power bus circuit. Search on Bibsonomy ISCAS (1) The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
73Gang-Hoon Seo, Won-Yong Jung, Seongsoo Lee, Jae-Kyung Wee Pipelined Bidirectional Bus Architecture for Embedded Multimedia SoCs. Search on Bibsonomy EUC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
73Kyeong Keol Ryu, Eung S. Shin, Vincent John Mooney III A Comparison of Five Different Multiprocessor SoC Bus Architectures. Search on Bibsonomy DSD The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
69Avnish R. Brahmbhatt, Jingyi Zhang, Qing Wu 0002, Qinru Qiu Low-power bus encoding using an adaptive hybrid algorithm. Search on Bibsonomy DAC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF data probabilistic distribution, delayed bus, weighted code mapping, window based change detection, low power, adaptive algorithm, bus encoding
68Anders Landin, Fredrik Dahlgren Bus-Based COMA - Reducing Traffic in Shared-Bus Multiprocessors. Search on Bibsonomy HPCA The full citation details ... 1996 DBLP  DOI  BibTeX  RDF bus-based COMA, standard UMA architecture, program-driven simulation, SPLASH, cache only memory architecture, shared-memory multiprocessors, shared memory systems, memory architecture, cache storage, shared-bus multiprocessors
68J.-Y. Chen, Wen-Ben Jone, Jinn-Shyan Wang, Hsueh-I Lu, Tien-Fu Chen Segmented bus design for low-power systems. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
66Syed Masud Mahmud Performance Analysis of Multilevel Bus Networks for Hierarchical Multiprocessors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1994 DBLP  DOI  BibTeX  RDF multilevel bus networks, hierarchical multiprocessors, partial multiple bus system, bus architecture, hierarchical multiprocessor design, synchronous multilevel bus systems, asynchronous multilevel bus systems, hierarchical reference model, MVA algorithm, performance evaluation, fault tolerance, performance analysis, parallel architectures, connections, queueing theory, multiprocessing systems, analytical models, bandwidth, queueing networks, switches, simulation models, memory bandwidth, packet-switched networks, cost-effectiveness, system buses, local computations, memory modules
65Carlos Fernández, Rajkumar K. Raval, Chris J. Bleakley GALS SoC interconnect bus for wireless sensor network processor platforms. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2007 DBLP  DOI  BibTeX  RDF SoC bus, application specific bus, system on chip bus, WSN, wireless sensor network, low power, GALS
65Chiung-San Lee, Tai-Ming Parng A Subsystem-Oriented Performance Analysis Methodology for Shared-Bus Multiprocessors. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Bottleneck analysis, DMA transfer, separated address bus and data bus, shared-bus multiprocessor system, subsystem access time modeling, subsystem interferences, performance analysis
64Young-Sin Cho, Eun-Ju Choi, Kyoung-Rok Cho Modeling and analysis of the system bus latency on the SoC platform. Search on Bibsonomy SLIP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF multi-layer bus, system bus, SoC, latency, platform
63Ke Ning, David R. Kaeli Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems. Search on Bibsonomy Trans. High Perform. Embed. Archit. Compil. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF embedded systems, power-aware, external memory, media processor, bus arbitration
63Sascha Mühlbach, Sebastian Wallner Secure and Authenticated Communication in Chip-Level Microcomputer Bus Systems with Tree Parity Machines. Search on Bibsonomy ICSAMOS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
63Kyoung-Sun Jhang, Kang Yi, Soo Yun Hwang A Two-Level On-Chip Bus System Based on Multiplexers. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
60Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar, Laxmi N. Bhuyan Power efficient encoding techniques for off-chip data buses. Search on Bibsonomy CASES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF FV, FV-MSB-LSB, data bus, low power, bus encoding
60Roman L. Lysecky, Frank Vahid, Tony Givargis Experiments with the Peripheral Virtual Component Interface. Search on Bibsonomy ISSS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF VCI, bus wrappers, interfacing, system-on-a-chip, intellectual property, Cores, on-chip bus
59Michael R. T. Tan, Paul Rosenberg, Jong Souk Yeo, Moray McLaren, Sagi Mathai, Terry Morris, Joseph Straznicky, Norman P. Jouppi, Huei Pei Kuo, Shih-Yuan Wang, Scott Lerner, Pavel Kornilovich, Neal Meyer, Robert Bicknell, Charles Otis, Len Seals A High-Speed Optical Multi-Drop Bus for Computer Interconnections. Search on Bibsonomy Hot Interconnects The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Computer interconnections, Multi-drop Bus, Optical Interconnects, Optical Bus
58Ke Ning, David R. Kaeli Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems. Search on Bibsonomy HiPEAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF embedded systems, Power-aware, external memory, media processor, bus arbitration
58Shi-Jinn Horng, Horng-Ren Tsai, Yi Pan 0001, Jennifer Seitzer Optimal Algorithms for the Channel-Assignment Problem on a Reconfigurable Array of Processors with Wider Bus Networks. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF minimum coloring problem, reconfigurable array of processors with wider bus networks, parallel algorithm, interval graph, list ranking, integer sorting, Channel-assignment problem
56Ruibing Lu, Cheng-Kok Koh A high performance bus communication architecture through bus splitting. Search on Bibsonomy ASP-DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
56Ruibing Lu, Cheng-Kok Koh SAMBA-Bus: A High Performance Bus Architecture for System-on-Chips. Search on Bibsonomy ICCAD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
56Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi Partial bus-invert coding for power optimization of system level bus. Search on Bibsonomy ISLPED The full citation details ... 1998 DBLP  DOI  BibTeX  RDF
54Stephen K. Sunter A low cost 100 MHz analog test bus. Search on Bibsonomy VTS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF analog test bus, on-chip analog bus, digital three-state inverter, low-input capacitance, signal bandwidth, bus input, design for testability, DFT, integrated circuit design, mixed-signal circuits, capacitance, mixed analogue-digital integrated circuits, IC design, 100 MHz
53Jun-hee Yoo, Dongwook Lee, Sungjoo Yoo, Kiyoung Choi Communication Architecture Synthesis of Cascaded Bus Matrix. Search on Bibsonomy ASP-DAC The full citation details ... 2007 DBLP  DOI  BibTeX  RDF AMBA3 AXI, cascaded bus matrix, on-chip communication architecture, bus topology, encoding method, traffic group encoding, simulated annealing, design space exploration
53Wei-Chung Cheng, Jian-Lin Liang, Massoud Pedram Software-Only Bus Encoding Techniques for an Embedded System. Search on Bibsonomy ASP-DAC/VLSI Design The full citation details ... 2002 DBLP  DOI  BibTeX  RDF memory bus encoding, bus activity minimization, CompactFlash, low power, Flash memory, LCD
53Sharath Jayaprakash, Nihar R. Mahapatra Partitioned Hybrid Encoding to Minimize On-Chip Energy Dissipation ofWide Microprocessor Buses. Search on Bibsonomy VLSI Design The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
53Constantine Katsinis, Bahram Nabet A Scalable Interconnection Network Architecture for Petaflops Computing. Search on Bibsonomy J. Supercomput. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF petaflops computing, performance analysis, interconnection networks, computer architecture
53H. A. Xie, Kevin E. Forward, K. M. Adams, D. Leask An SBus Monitor Board. Search on Bibsonomy FPGA The full citation details ... 1995 DBLP  DOI  BibTeX  RDF
53Lee-Juan Fan, Chang-Biau Yang, Shyue-Horng Shiau Routing Algorithms on the Bus-Based Hypercube Network. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Multiple-bus network, fault tolerance, hypercube, routing algorithm, diameter
53Yan Zhang 0028, John C. Lach, Kevin Skadron, Mircea R. Stan Odd/even bus invert with two-phase transfer for buses with coupling. Search on Bibsonomy ISLPED The full citation details ... 2002 DBLP  DOI  BibTeX  RDF bus invert, buses with coupling, coding for low-power I/O
53Hung-Kuei Ku, John P. Hayes Connective Fault Tolerance in Multiple-Bus Systems. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1997 DBLP  DOI  BibTeX  RDF interconnection methods, fault tolerance, multiprocessors, graph models, Multiple-bus systems
52Yi-Ting Lin, Chien-Chou Wang, Ing-Jer Huang AMBA AHB bus potocol checker with efficient debugging mechanism. Search on Bibsonomy ISCAS The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
52Sujan Pandey, Manfred Glesner Simultaneous On-Chip Bus Synthesis and Voltage Scaling Under Random On-Chip Data Traffic. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
52Sanghun Lee, Chanho Lee A High Performance SoC On-chip-bus with Multiple Channels and Routing Processes. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykrishnan, Nagu R. Dhanwada Transaction Level Error Susceptibility Model for Bus Based SoC Architectures. Search on Bibsonomy ISQED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Chang Hee Pyoun, Chi-Ho Lin, Hi-Seok Kim, Jong-Wha Chong The Efficient Bus Arbitration Scheme in SoC Environment. Search on Bibsonomy IWSOC The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
52Cheng-Ta Hsieh, Massoud Pedram Architectural energy optimization by bus splitting. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
49Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar A tunable bus encoder for off-chip data buses. Search on Bibsonomy ISLPED The full citation details ... 2005 DBLP  DOI  BibTeX  RDF TUBE, data bus, data bus encoding, tunable bus encoder
48Dinesh C. Suresh, Banit Agrawal, Jun Yang 0002, Walid A. Najjar Energy-efficient encoding techniques for off-chip data buses. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Low-power data buses, bus switching, internal capacitances, encoding
48Wissam Hlayhel, Daniel Litaize, Laurent Fesquet, Jacques Henri Collet Optical versus Electronic Bus for Address-Transactions in Future SMP Architectures. Search on Bibsonomy IEEE PACT The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Bandwidth requirement, SMP architecture, optical bus, shared bus
48Saied Hosseini-Khayat, Andreas D. Bovopoulos A Simple and Efficient Bus Management Scheme that Supports Continuous Streams Search on Bibsonomy ACM Trans. Comput. Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF bus management, continuous stream, multimedia workstation, bus arbitration
47Hui Kong 0002, Tan Yan, Martin D. F. Wong Automatic bus planner for dense PCBs. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF PCB routing, bus planning, topological routing, layer assignment
47Lan Gao, Jun Yang 0002, Marek Chrobak, Youtao Zhang, San Nguyen, Hsien-Hsin S. Lee A low-cost memory remapping scheme for address bus protection. Search on Bibsonomy PACT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF address bus leakage protection, secure processor
47Sudeep Pasricha, Young-Hwan Park, Fadi J. Kurdahi, Nikil D. Dutt System-level power-performance trade-offs in bus matrix communication architecture synthesis. Search on Bibsonomy CODES+ISSS The full citation details ... 2006 DBLP  DOI  BibTeX  RDF bus matrix synthesis, system-on-chip, power estimation, communication architectures, power-performance trade-offs
47Chung-Hsiang Lin, Chia-Lin Yang, Ku-Jei King Hierarchical value cache encoding for off-chip data bus. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF data bus encoding, hierarchical value cache, energy
47Harmander Deogun, Robert M. Senger, Dennis Sylvester, Richard B. Brown, Kevin J. Nowka A dual-VDD boosted pulsed bus technique for low power and low leakage operation. Search on Bibsonomy ISLPED The full citation details ... 2006 DBLP  DOI  BibTeX  RDF pulsed bus, leakage, repeaters, Dual-VDD
47Ann T. Tai, Savio N. Chau, Leon Alkalai COTS-Based Fault Tolerance in Deep Space: Qualitative and Quantitative Analyses of a Bus Network Architecture. Search on Bibsonomy HASE The full citation details ... 1999 DBLP  DOI  BibTeX  RDF COTS-based fault tolerance, deep-space applications, bus network reliability, tree topology, IEEE 1394
47Huan-Yu Tu, Lois Wright Hawkes Network Simulations of a General Class of Partial-Connection Multiple-Bus Systems. Search on Bibsonomy MASCOTS The full citation details ... 1999 DBLP  DOI  BibTeX  RDF multiple-bus, fault-tolerant, routing, CSMA/CD
47Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane BMSYN: Bus Matrix Communication Architecture Synthesis for MPSoC. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Hua Xiang 0001, Liang Deng, Li-Da Huang, Martin D. F. Wong OPC-Friendly Bus Driven Floorplanning. Search on Bibsonomy ISQED The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
47Hui Guo, Ying Jiang Application Layer Definition and Analyses of Controller Area Network Bus for Wire Harness Assembly Machine. Search on Bibsonomy CIMCA/IAWTIC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
47Lin Xie, Peiliang Qiu, Qinru Qiu Partitioned bus coding for energy reduction. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Liang Deng, Martin D. F. Wong Energy optimization in memory address bus structure for application-specific systems. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
47Hua Xiang 0001, Xiaoping Tang, Martin D. F. Wong Bus-driven floorplanning. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
47Constantine Katsinis, Diana Hecht Fault-Tolerant DSM on the SOME-Bus Multiprocessor Architecture with Message Combining. Search on Bibsonomy IPDPS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
47Hua Xiang 0001, Xiaoping Tang, Martin D. F. Wong Bus-Driven Floorplanning. Search on Bibsonomy ICCAD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
47Christos D. Antonopoulos, Dimitrios S. Nikolopoulos, Theodore S. Papatheodorou Scheduling Algorithms with Bus Bandwidth Considerations for SMPs. Search on Bibsonomy ICPP The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
47Youngsoo Shin, Soo-Ik Chae, Kiyoung Choi Partial bus-invert coding for power optimization of application-specific systems. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
47Cheng-Ta Hsieh, Massoud Pedram Architectural Power Optimization by Bus Splitting. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
47Woo-Jong Hahn, Ando Ki, Kee-Wook Rim, Soo-Won Kim Electronics and Telecommunications Research Institute: A Multiprocessor Server with a New Highly Pipelined Bus. Search on Bibsonomy IPPS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
47T. Pattabhiraman, Nick Cercone Representing and Using Protosemantic Information in Generating Bus Route Descriptions. Search on Bibsonomy KBCS The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
46Brian J. d'Auriol The systems edge of the Parameterized Linear Array with a Reconfigurable Pipelined Bus System (LARPBS(p)) optical bus parallel computing model. Search on Bibsonomy J. Supercomput. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Parallel computing model, Optical bus
46Sujan Pandey, Nurten Utlu, Manfred Glesner Tabu Search Based On-Chip Communication Bus Synthesis for Shared Multi-Bus Based Architecture. Search on Bibsonomy VLSI-SoC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
44Krishnan Sundaresan, Nihar R. Mahapatra Interconnect Signaling and Layout Optimization to Manage Thermal Effects Due to Self Heating in On-Chip Signal Buses. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Bus Energy, Self Heating, Wire Permutation, Optimization, Interconnect, Layout, Temperature, On-Chip Bus
44Basem A. Nayfeh, Kunle Olukotun, Jaswinder Pal Singh The Impact of Shared-Cache Clustering in Small-Scale Shared-Memory Multiprocessors. Search on Bibsonomy HPCA The full citation details ... 1996 DBLP  DOI  BibTeX  RDF shared-cache clustering, small-scale shared-memory multiprocessors, shared global bus, low-latency interconnections, performance evaluation, shared memory systems, cache storage, memory system, multichip module, L2 cache, processor performance, high-bandwidth, bus contention
43Hong Jiang, Kenneth C. Smith PPMB: A Partial-Multiple-Bus Multiprocessor Architecture with Improved Cost-Effectiveness. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 1992 DBLP  DOI  BibTeX  RDF PPMB, partial-multiple-bus multiprocessor architecture, processor-oriented partial-multiple-bus, memory-oriented partial-multiple-bus, system bandwidth, simulation, performance evaluation, design, performance analysis, interconnection networks, computer architecture, multiprocessor interconnection networks, cost-effectiveness, arbitration
43Tan Yan, Martin D. F. Wong Theories and algorithms on single-detour routing for untangling twisted bus. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF printed circuit board (PCB), single-detour routing, twisted bus, dynamic programming, Bus routing
43Hettihe P. Dharmasena, Ramachandran Vaidyanathan Lower Bounds on the Loading of Multiple Bus Networks for Binary Tree Algorithms. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Multiple bus networks, binary tree algorithms, bus loading, interconnection networks, lower bounds
43Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane Fast exploration of bus-based on-chip communication architectures. Search on Bibsonomy CODES+ISSS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF bus cycle accurate modeling, fast communication architecture exploration, shared bus architectures, transaction level modeling, AMBA
43Roman L. Lysecky, Frank Vahid Prefetching for improved bus wrapper performance in cores. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF Bus wrapper, PVCI, VSIA, interfacing, system-on-a-chip, intellectual property, cores, design reuse, on-chip bus
43Roman L. Lysecky, Frank Vahid, Tony Givargis Techniques for Reducing Read Latency of Core Bus Wrappers. Search on Bibsonomy DATE The full citation details ... 2000 DBLP  DOI  BibTeX  RDF bus wrapper, interfacing, system-on-a-chip, intellectual property, Cores, design reuse, on-chip bus
43Reiner W. Hartenstein, Jürgen Becker 0001, Michael Herz, Rainer Kress 0002, Ulrich Nageldinger A Synthesis System For Bus-Based Wavefront Array Architectures. Search on Bibsonomy ASAP The full citation details ... 1996 DBLP  DOI  BibTeX  RDF synthesis system, bus-based wavefront array architectures, datapath synthesis system, reconfigurable datapath architecture, internal data bus, automatic mapping, datapath units, high speed datapaths, parallel architectures, rapid prototyping, reconfigurable architectures, software prototyping, fine grained parallelism, data manipulations
43Thin-Fong Tsuei, Mary K. Vernon A Multiprocessor Bus Design Model Validated by System Measurement. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1992 DBLP  DOI  BibTeX  RDF commercial multiprocessor bus, bus design, asynchronous memorywrite operations, in-order delivery, processor read requests, memoryresponses, outstanding processor requests, two-level hierarchical model, mean value analysis techniques, measured system performance, parallel program workloads, memory access characteristics, analytic queueing models, model tractability, detailed simulation, system design tradeoffs, parallel programming, formal verification, Markov chain, Markov processes, queueing theory, multiprocessing systems, queueing networks, system buses, priority scheduling, performanceevaluation, system measurement
43Carlos G. Bilich, Zaijun Hu Experiences with the Certification of a Generic Functional Safety Management Structure According to IEC 61508. Search on Bibsonomy SAFECOMP The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Functional Safety, reusable components, IEC 61508
43Bas Breijer, Filipa Duarte, Stephan Wong An OCM based shared Memory controller for Virtex 4. Search on Bibsonomy FPL The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Srinivasa R. Sridhara, Naresh R. Shanbhag Coding for system-on-chip networks: a unified framework. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Sujan Pandey, Heiko Zimmer, Manfred Glesner, Max Mühlhäuser High level hardware/software communication estimation in shared memory architecture. Search on Bibsonomy ISCAS (1) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
42Ricardo Bedin França, Leandro Buss Becker, Jean-Paul Bodeveix, Jean-Marie Farines, Mamoun Filali Towards Safe Design of Synchronous Bus Protocols in Event-B. Search on Bibsonomy SBMF The full citation details ... 2009 DBLP  DOI  BibTeX  RDF synchronous systems, Event-B, parameterized systems, bus protocols
42Renshen Wang, Nan-Chi Chou, Bill Salefski, Chung-Kuan Cheng Low power gated bus synthesis using shortest-path Steiner graph for system-on-chip communications. Search on Bibsonomy DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Steiner graph, gated bus, power efficiency
42Kriangsak Vanitchakornpong, Nakorn Indra-Payoong, Agachai Sumalee, Pairoj Raothanachonkun Constrained Local Search Method for Bus Fleet Scheduling Problem with Multi-depot with Line Change. Search on Bibsonomy EvoWorkshops The full citation details ... 2008 DBLP  DOI  BibTeX  RDF Bus scheduling, Multi-depot and line change, Constrained local search
42Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas Process Variation Aware Bus-Coding Scheme for Delay Minimization in VLSI Interconnects. Search on Bibsonomy ISQED The full citation details ... 2008 DBLP  DOI  BibTeX  RDF bus coding, delay, process variation
42Jill H. Y. Law, Evangeline F. Y. Young Multi-bend bus driven floorplanning. Search on Bibsonomy ISPD The full citation details ... 2005 DBLP  DOI  BibTeX  RDF bus planning, floorplanning, VLSI CAD
42Massimo Conti, Marco Caldari, Giovanni B. Vece, Simone Orcioni, Claudio Turchetti Performance analysis of different arbitration algorithms of the AMBA AHB bus. Search on Bibsonomy DAC The full citation details ... 2004 DBLP  DOI  BibTeX  RDF AMBA AHB BUS, arbitration algorithm, performance, systemC
42Ching-Chih Han, Chao-Ju Hou, Kar Shun Tsoi, Sean Ho Dynamic Establishment and Termination of Real-Time Message Streams in Dual-Bus Networks. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2000 DBLP  DOI  BibTeX  RDF Dual-bus networks, $(C,D){hbox{-}}{rm smooth}$ message model, message stream setup and tear-down, temporal QoS guarantee, distance constraint
42Ramachandran Vaidyanathan, Sudharani Nadella Fault-Tolerant Multiple Bus Networks for Fan-In Algorithms. Search on Bibsonomy IPPS The full citation details ... 1996 DBLP  DOI  BibTeX  RDF Multiple bus networks, Fan-in algorithms, Fault-tolerance, Parallel processing, Interconnection networks
42K. C. Lee A Virtual Bus Architecture for Dynamic Parallel Processing. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1993 DBLP  DOI  BibTeX  RDF virtual bus architecture, dynamic parallel processing, parallel/distributed machine, end-to-end communication bandwidth, communicationpatterns, data collection operations, nonuniformtraffic, open system parallel interface, open system communication backbone, scheduling, interconnection network, delays, multiprocessor interconnection networks, open systems, dynamic load balancing, network interfaces, queuing delay
42Guenter Klas Protocol Optimization for a Packet-Switched Bus in Case of Burst Traffic by Means of GSPN. Search on Bibsonomy Application and Theory of Petri Nets The full citation details ... 1993 DBLP  DOI  BibTeX  RDF Bus Pipeline, Performance Modeling, Multiprocessor Systems, GSPN
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