Search results for "cmos"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
76	Keivan Navi, Daniel Etiemble	From Multi-Valued Current Mode CMOS Circuits to Efficient Voltage Mode CMOS Arithmetic Operators.	ISMVL	1995	DBLP DOI BibTeX RDF	multivalued current mode CMOS circuits, voltage mode CMOS arithmetic operators, 3-valued current mode CMOS 2-input BSC adder, CMOS binary 4-2 counter, 1-digit Avizienis-like adder, adders, CMOS integrated circuits, integrated logic circuits, multivalued logic circuits, ternary logic, redundant number representation
55	Sergey Gavrilov, Alexey Glebov, Satyamurthy Pullela, S. C. Moore, Abhijit Dharchoudhury, Rajendran Panda, Gopalakrishnan Vijayan, David T. Blaauw	Library-less synthesis for static CMOS combinational logic circuits.	ICCAD	1997	DBLP DOI BibTeX RDF	library-less synthesis, resynthesized circuits, size-wise CMOS circuit optimization, static CMOS combinational logic circuits, structural CMOS circuit optimization, transistor level technique, CMOS logic circuits, design space, optimal design, circuit performance
55	Andreas G. Andreou, Kwabena A. Boahen	A 590, 000 transistor 48, 000 pixel, contrast sensitive, edge enhancing, CMOS imager-silicon retina.	ARVLSI	1995	DBLP DOI BibTeX RDF	silicon retina, analog VLSI focal plane processor, phototransduction, local gain control, single chip system, vertebrate distal retina, ultra low power dissipation, n-well double metal double poly digital oriented CMOS technology, current-mode subthreshold CMOS, 48000 pixel, computer vision, VLSI, edge detection, CMOS integrated circuits, image sensors, contrast, edge enhancement, CMOS imager, focal planes, area efficiency, 1.2 micron
49	Sreejit Chakravarty	On the complexity of computing tests for CMOS gates.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
46	Saed G. Younis, Thomas F. Knight Jr.	Non-dissipative rail drivers for adiabatic circuits.	ARVLSI	1995	DBLP DOI BibTeX RDF	driver circuits, distributed parameter networks, lumped parameter networks, passive networks, nondissipative rail drivers, adiabatic circuits, CMOS charge recovery logic, energy dissipation per operation, SCRL circuits, rail waveform generation, rail driver circuit, multiple harmonics, harmonic rail driver, passive reactive components, trimmed transmission line segments, CMOS logic circuits, CMOS circuits, harmonics
45	Kazuma Ohashi, Yusaku Ito, Yoshiaki Yoshihara, Kenichi Okada, Kazuya Masu	A Wideband CMOS LC-VCO Using Variable Inductor.	ASP-DAC	2007	DBLP DOI BibTeX RDF	wideband CMOS LC-VCO, variable inductor, tunable CMOS voltage controlled oscillator, switched capacitors, 1.28 to 2.75 GHz, CMOS process, 0.18 micron
45	João Navarro Jr., Reinaldo Silveira, Fábio L. Romao, Wilhelmus A. M. Van Noije	A 1.4 Gbit/s CMOS driver for 50 Ω ECL systems.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	CMOS driver, ECL systems, speed performance, effective length, circuit operation, current source switching, output load, SDH/SONET system, CMOS-ECL convertor output buffer, 0.8 mum, 0.7 mum, 1.4 Gbit/s, 50 ohm, CMOS logic circuits, output buffer
45	Stephan P. Athan, David L. Landis, Sami A. Al-Arian	A novel built-in current sensor for IDDQ testing of deep submicron CMOS ICs.	VTS	1996	DBLP DOI BibTeX RDF	deep submicron CMOS ICs, fault diagnosability, ULSI CMOS, fault diagnosis, integrated circuit testing, fault detectability, CMOS integrated circuits, leakage currents, built-in current sensor, I/sub DDQ/ testing, electric current measurement, ULSI, electric sensing devices
45	William C. Athas, Nestoras Tzartzanis	Energy recovery for low-power CMOS.	ARVLSI	1995	DBLP DOI BibTeX RDF	bootstrap circuits, low-power CMOS, energy-recovery techniques, voltage swing, transition time, MOS device parameters, adder designs, VLSI, mathematical model, bootstrapping, adders, CMOS logic circuits, CMOS logic circuits, power dissipation, integrated circuit modelling, SOI
42	B. Chester Hwang	Trends of Key Advanced Device Technologies.	ARVLSI	1997	DBLP DOI BibTeX RDF	SIA roadmap, Sematech, TFSOI, graded-channel CMOS, complementary IC technology, 0.25 micron, CMOS integrated circuits, CMOS technology, Moore's law, GaAs, Si
42	Adrian M. Ionescu, Michel J. Declercq, Santanu Mahapatra, Kaustav Banerjee, Jacques Gautier	Few electron devices: towards hybrid CMOS-SET integrated circuits.	DAC	2002	DBLP DOI BibTeX RDF	Iinverter, hybrid CMOS-SET Circuits, single-Electron transistors, ultimate CMOS, low power, quantizer, nanoelectronics
42	Hoi-Jun Yoo, Chris Van Hoof	Introduction to Bio-Medical CMOS IC.	Bio-Medical CMOS ICs	2011	DBLP DOI BibTeX RDF
41	Tak H. Ning	GLSVLSI 2008 invited/keynote talk.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	soi, cmos scaling
41	Ayman I. Kayssi	Macromodeling C- and RC-loaded CMOS inverters for timing analysis.	Great Lakes Symposium on VLSI	1996	DBLP DOI BibTeX RDF	RC-loaded CMOS inverters, C-loaded CMOS inverters, series-resistor shunt-capacitor circuit, capacitive load case, input wave shape, transistor drive, timing, logic CAD, timing analysis, circuit analysis computing, CMOS logic circuits, circuit simulation, table lookup, macromodels, logic gates, lookup table, integrated circuit modelling
41	Terry Lee, Ibrahim N. Hajj, Elizabeth M. Rudnick, Janak H. Patel	Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits.	VTS	1996	DBLP DOI BibTeX RDF	GA-based test generators, CMOS VLSI circuits, I/sub DDQ/ current testing, CMOS digital circuits, two-line bridging fault set, compact test set generation, genetic algorithms, VLSI, logic testing, integrated circuit testing, ATPG, automatic test pattern generator, automatic testing, fault location, bridging faults, CMOS digital integrated circuits, adaptive genetic algorithm
41	A. K. Jain, Mostafa I. H. Abd-El-Barr, R. J. Bolton	Current-Mode CMOS Multiple-Valued Logic Function Realization Using a Direct Cover Algorithm.	ISMVL	1995	DBLP DOI BibTeX RDF	current-mode CMOS multiple-valued logic function realization, heuristic based programs, sum of product form expression, HAMLET, Gold heuristic, current mode CMOS, multiple valued logic function realization, direct cover algorithm, logic design, random sample, multivalued logic, CMOS logic circuits, heuristic programming, MVL function
40	Reza M. Rad, Mohammad Tehranipoor	Evaluating area and performance of hybrid FPGAs with nanoscale clusters and CMOS routing.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	performance, FPGA, reliability, CMOS, Nanotechnology
39	K. Wayne Current	Memory Circuits for Multiple-Valued Logic Voltage Signals.	ISMVL	1995	DBLP DOI BibTeX RDF	memory circuits, multiple valued logic voltage signals, voltage-mode CMOS multiple valued logic memory circuits, polysilicon-gate CMOS technology, SETUP clock mode, HOLD clock mode, multivalued logic circuits, integrated memory circuits, CMOS memory circuits
39	Eric Y. Chou, Bing J. Sheu, Tony H. Wu, Robert C. Chang	VLSI design of densely-connected array processors.	ICCD	1995	DBLP DOI BibTeX RDF	densely-connected array processors, paralleled array processors, real-time signal processing, problem mapping, high potential computational bandwidth, local interconnection, synaptic operators, CNN processing engine, hardware design problems, CNN accelerator design, digital-programmable synapses, flexible digital interface, current-mode CMOS circuits, 2.0 /spl mu/m CMOS technology, edge detection operation, image processing, image processing, parallel processing, VLSI, edge detection, signal processing, VLSI design, heterogeneous computing, CMOS integrated circuits, cellular neural networks, cellular neural nets
39	Sanjay Rekhi, J. Donald Trotter	HAL: heuristic algorithms for layout synthesis.	ARVLSI	1995	DBLP DOI BibTeX RDF	layout synthesis, graph theory based algorithms, leaf cells, common poly gates, 1-1/2-d layout style, common circuit nodes, transistor sets, symbolic layouts, static dual type, static CMOS circuitry, pullup network, pulldown network, dynamic logic styles, graph theory, network topology, logic CAD, heuristic algorithms, circuit layout CAD, CMOS logic circuits, CMOS circuits, GENIE, run time efficient, layout area
38	Alex G. Dickinson, Bryan D. Ackland, El-Sayed Eid, David A. Inglis, Eric R. Fossum	Standard CMOS active pixel image sensors for multimedia applications.	ARVLSI	1995	DBLP DOI BibTeX RDF	CMOS active pixel image sensors, single chip video cameras, color filter array, document capture, 1024 pixel, multimedia, multimedia systems, CMOS integrated circuits, image sensors, transistors, video cameras, gain
37	Marcelino B. Santos, M. Simões, Isabel C. Teixeira, João Paulo Teixeira 0001	Test preparation for high coverage of physical defects in CMOS digital ICs.	VTS	1995	DBLP DOI BibTeX RDF	high defect coverage, CMOS digital ICs, pseudo realistic faults generation, test quality assessment, tabloid, iceTgen, I/sub DDQ/ test generation, test preparation, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, CMOS digital integrated circuits, physical defects
37	Bill Huston	Practical CMOS microprocessor systems.	AFIPS National Computer Conference	1982	DBLP DOI BibTeX RDF
36	L. Richard Carley, Akshay Aggarwal, Ram K. Krishnamurthy	Decreasing low-voltage manufacturing-induced delay variations with adaptive mixed-voltage-swing circuits.	ISLPED	1998	DBLP DOI BibTeX RDF	low power CMOS logic, low voltage logic circuits, manufacturing variations, mixed-swing CMOS logic
36	Duncan M. Hank Walker	K Longest Paths.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
36	Sudhakar M. Reddy, Peter Maxwell	Fundamentals of Small-Delay Defect Testing.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
36	Mahmut Yilmaz	Output Deviations-Based SDD Testing.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
36	Sandeep Kumar Goel, Krishnendu Chakrabarty	Circuit Topology-Based Test Pattern Generation for Small-Delay Defects.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
36	Sandeep Kumar Goel, Narendra Devta-Prasanna	Hybrid/Top-off Test Pattern Generation Schemes for Small-Delay Defects.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
36	Narendra Devta-Prasanna, Sandeep Kumar Goel	Small-Delay Defect Coverage Metrics.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
36	Ke Peng, Mahmut Yilmaz, Mohammad Tehranipoor	Circuit Path Grading Considering Layout, Process Variations, and Cross Talk.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
36	Nisar Ahmed, Mohammad Tehranipoor	Faster-than-at-Speed Test for Screening Small-Delay Defects.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
36	Mark Kassab, Benoit Nadeau-Dostie, Xijiang Lin	Timing-Aware ATPG.	Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits	2014	DBLP BibTeX RDF
36	Erno Klaassen	Cardiac Rhythm Management IC's.	Bio-Medical CMOS ICs	2011	DBLP DOI BibTeX RDF
36	Refet Firat Yazicioglu	Readout Circuits.	Bio-Medical CMOS ICs	2011	DBLP DOI BibTeX RDF
36	Jan Craninckx, Geert Van der Plas	Low-Power ADCs for Bio-Medical Applications.	Bio-Medical CMOS ICs	2011	DBLP DOI BibTeX RDF
36	Robert Puers, Jef Thoné	Short Distance Wireless Communications.	Bio-Medical CMOS ICs	2011	DBLP DOI BibTeX RDF
36	Yong Jeong	Introduction to Bioelectricity.	Bio-Medical CMOS ICs	2011	DBLP DOI BibTeX RDF
36	Sunyoung Kim, Hoi-Jun Yoo	Digital Hearing Aid and Cochlear Implant.	Bio-Medical CMOS ICs	2011	DBLP DOI BibTeX RDF
36	Jun Ohta	Artificial Retina IC.	Bio-Medical CMOS ICs	2011	DBLP DOI BibTeX RDF
36	Hyejung Kim, Hoi-Jun Yoo	Low Power Bio-Medical DSP.	Bio-Medical CMOS ICs	2011	DBLP DOI BibTeX RDF
36	David A. Dinsmoor, Robert W. Hocken Jr, Wesley A. Santa, Jalpa S. Shah, Larry Tyler, Timothy J. Denison	Neurostimulation Design from an Energy and Information Transfer Perspective.	Bio-Medical CMOS ICs	2011	DBLP DOI BibTeX RDF
36	Jerald Yoo, Hoi-Jun Yoo	Wearable Healthcare System.	Bio-Medical CMOS ICs	2011	DBLP DOI BibTeX RDF
36	Eric McAdams	Biomedical Electrodes For Biopotential Monitoring and Electrostimulation.	Bio-Medical CMOS ICs	2011	DBLP DOI BibTeX RDF
36	Julien Penders, Chris Van Hoof, Bert Gyselinckx	Bio-Medical Application of WBAN: Trends and Examples.	Bio-Medical CMOS ICs	2011	DBLP DOI BibTeX RDF
36	Seong-Jun Song, Hoi-Jun Yoo	Body Channel Communication for Energy-Efficient BAN.	Bio-Medical CMOS ICs	2011	DBLP DOI BibTeX RDF
36	Harika Manem, Garrett S. Rose	The effects of logic partitioning in a majority logic based CMOS-NANO FPGA.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	cmos-nano, fpga
36	Siva G. Narendra	Challenges and design choices in nanoscale CMOS.	ACM J. Emerg. Technol. Comput. Syst.	2005	DBLP DOI BibTeX RDF	nanoscale, process variation, CMOS, leakage power
36	Nestoras Tzartzanis, William C. Athas	Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing.	ARVLSI	1999	DBLP DOI BibTeX RDF	low-power digital CMOS, adiabatic switching, clock-powered logic, energy recovery
36	Maryam Ashouei, Adit D. Singh, Abhijit Chatterjee	Reconfiguring CMOS as Pseudo N/PMOS for Defect Tolerance in Nano-Scale CMOS.	VLSI Design	2008	DBLP DOI BibTeX RDF
35	Peter M. Kogge, Toshio Sunaga, Hisatada Miyataka, Koji Kitamura, Eric Retter	Combined DRAM and logic chip for massively parallel systems.	ARVLSI	1995	DBLP DOI BibTeX RDF	EXECUBE, custom circuits, high density memory, PIM chip, Processor-In-Memory computer architecture, logic chip, 0.8 micron, 2.7 W, 25 MHz, 5 V, 50 MIPS, embedded systems, parallel architectures, CMOS logic circuits, microprocessor chips, CMOS technology, CPU, macros, massively parallel processing, DRAM chips, DRAM chip, CMOS memory circuits
35	YuHua Cheng	A glance of technology efforts for design-for-manufacturing in nano-scale CMOS processes.	Sci. China Ser. F Inf. Sci.	2008	DBLP DOI BibTeX RDF	nano-CMOS IC design, IC design methodology, CMOS design technology platform, design-for-manufacturing (DFM), design-for-yield
35	Tadayoshi Enomoto, Suguru Nagayama, Nobuaki Kobayashi	Low-Power High-Speed 180-nm CMOS Clock Drivers.	ASP-DAC	2007	DBLP DOI BibTeX RDF	0.640 ns, CMOS clock drivers, register array, delay flip-flops, 251 muW, CMOS technology, power dissipation, delay time, 0.18 micron
35	Mostafa I. H. Abd-El-Barr, Yanging Xu, Carl McCrosky	Transistor Stuck-Open Fault Detection in Multilevel CMOS Circuits.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF	Transistor stuck-open fault, multi-level CMOS circuits testing, robust CMOS testing, test pattern generation, two-pattern test
35	Alvernon Walker, Algernon P. Henry, Parag K. Lala	An approach for detecting bridging faults in CMOS domino logic circuits using dynamic power supply current monitoring.	DFT	1997	DBLP DOI BibTeX RDF	bridging faults detection, CMOS domino logic circuits, dynamic power supply current monitoring, CMOS logic circuits, transient current
35	Jonathan T.-Y. Chang, Edward J. McCluskey	SHOrt voltage elevation (SHOVE) test for weak CMOS ICs.	VTS	1997	DBLP DOI BibTeX RDF	short voltage elevation test, SHOVE test, voltage stress, reliability screening, oxide thinning, via defect, complementary logic gate, domino logic gate, functional test, CMOS integrated circuits, IDDQ test, transistor, CMOS IC
35	Soon-Jyh Chang, Chung-Len Lee 0001, Jwu E. Chen	Functional test pattern generation for CMOS operational amplifier.	VTS	1997	DBLP DOI BibTeX RDF	functional test pattern generation, CMOS operational amplifier, programmable gain/loss mixed signal circuit, op amp testing, IC testing, CMOS analogue integrated circuits
35	Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan	New MVL-PLA Structures Based on Current-Mode CMOS Technology.	ISMVL	1996	DBLP DOI BibTeX RDF	MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic
35	A. B. Bhattacharyya, Ram Singh Rana, S. K. Guha, Rajendar Bahl, R. Anand, M. J. Zarabi, P. A. Govindacharyulu, U. Gupta, V. Mohan, Jatin Roy, Amul Atri	A micropower analog hearing aid on low voltage CMOS digital process.	VLSI Design	1996	DBLP DOI BibTeX RDF	differential amplifiers, automatic gain control, micropower analog hearing aid, low voltage CMOS digital process, adaptive biasing, MOS translinear loop circuit, degenerating linearising resistor, input differential stage, AGC block, conversion efficiency, 3 micron, 1.0 V, power consumption, CMOS analogue integrated circuits, hearing aids
35	Ram K. Krishnamurthy, Ramalingam Sridhar	A CMOS wave-pipelined image processor for real-time morphology .	ICCD	1995	DBLP DOI BibTeX RDF	CMOS wave-pipelined image processor, real-time morphology, high-speed morphological image processor, wave-pipelined transmission gate logic, two-stage morphological skeleton transform filter, regular pipelined architectures, real-time systems, computational complexity, image processing, latency, pipeline processing, CMOS integrated circuits, hardware complexity
33	Khawla Alzoubi, Daniel G. Saab, Massood Tabib-Azar	Complementary nano-electromechanical switches for ultra-low power embedded processors.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	nems, cmos, switch, device, ultra-low power
33	Larkhoon Leem, James A. Weaver, Metha Jeeradit, James S. Harris Jr.	Nano-magnetic non-volatile CMOS circuits for nano-scale FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	spin-torque devices, fpga, spintronics
32	Weisheng Zhao, Guillaume Agnus, Vincent Derycke, Arianna Filoramo, Christian Gamrat, Jean-Philippe Bourgoin	Functional Model of Carbon Nanotube Programmable Resistors for Hybrid Nano/CMOS Circuit Design.	NanoNet	2009	DBLP DOI BibTeX RDF	Hybrid Nano/CMOS circuits, OG-CNTFET, Verilog-A, Carbon Nanotube, Functional Modelling
32	Kiyoo Itoh 0001	Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era.	ISLPED	2009	DBLP DOI BibTeX RDF	0.5-v nanoscale cmos lsis, conventional mosfet, minimum vdd, speed variation, vt variation, leakage, sram, dram, finfet
32	Ann Witvrouw	CMOS-MEMS integration: why, how and what?	ICCAD	2006	DBLP DOI BibTeX RDF	CMOS-MEMS integration, poly-SiGe, technology
32	Haigang Yang, Hongguang Sun, Jinghong Han, Jinbao Wei, Zengjin Lin, Shanhong Xia, Hua Zhong	A pH-ISFET Based Micro Sensor System on Chip Using Standard CMOS Technology.	IWSOC	2005	DBLP DOI BibTeX RDF	Micro Sensor System, ISFET, CMOS, SOC
32	Yongjian Brandon Guo, K. Wayne Current	Voltage Comparator Circuits for Multiple-Valued CMOS Logic.	ISMVL	2002	DBLP DOI BibTeX RDF	voltage comparator, MVL, low-power, CMOS
32	Siva G. Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan	Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS.	ISLPED	2002	DBLP DOI BibTeX RDF	sub-threshold leakage, CMOS, within-die variation
32	Ali Bastani, Charles A. Zukowski	A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology.	ISQED	2006	DBLP DOI BibTeX RDF
31	Ching-Hwa Cheng, Wen-Ben Jone, Jinn-Shyan Wang, Shih-Chieh Chang	Charge sharing fault analysis and testing for CMOS domino logic circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	charge sharing fault analysis, CMOS domino logic circuits, domino logic design, sensitivity measurement, domino gate, fault diagnosis, logic testing, delays, delay, automatic testing, CMOS logic circuits, logic gates, test vectors
31	Arabi Keshk, Yukiya Miura, Kozo Kinoshita	Simulation of resistive bridging fault to minimize the presence of intermediate voltage and oscillation in CMOS circuits.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	circuit oscillations, transistor level networks, feedback oscillation, Byzantine General's problems, logic threshold, logic testing, logic testing, integrated circuit testing, fault coverage, fault location, bridging fault, CMOS circuits, CMOS digital integrated circuits, test vector
31	Yinan N. Shen, Xiao-Tao Chen, Susumu Horiguchi, Fabrizio Lombardi	On the multiple fault diagnosis of multistage interconnection networks: the lower bound and the CMOS fault model.	ICPP	1997	DBLP DOI BibTeX RDF	CMOS fault model, multiple fault diagnosis, interconnection networks, fault diagnosis, lower bound, multistage interconnection networks, multistage interconnection networks, CMOS technology, stuck-open faults
31	Kuen-Jong Lee, Jing-Jou Tang	Two Modeling Techniques For CMOS Circuits To Enhance Test Generation And Fault Simulation For Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	efficient modeling techniques, enhanced test generation performance, fault modeling technique, inter-gate faults, threshold determination method, SPICE like accuracy, digital logic gates, logic testing, fault simulation, CMOS logic circuits, bridging faults, IDDQ testing, CMOS circuits
31	Kuen-Jong Lee, Jing-Jou Tang, Tsung-Chu Huang, Cheng-Liang Tsai	Combination Of Automatic Test Pattern Generation And Built-In Intermediate Voltage Sensing For Detecting CMOS Bridging Faults.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	CMOS bridging faults detection, ATPG system, built-in intermediate voltage sensing, BIFEST system, PODEM-like process, PPSFP-based process, logic monitoring, gate threshold ranges, Byzantine General's Command Problem, feedback bridging faults, parallel pattern single fault propagation, fault modelling, fault simulation, fault coverage, greedy algorithm, CMOS logic circuits
31	Haluk Konuk, F. Joel Ferguson	An unexpected factor in testing for CMOS opens: the die surface.	VTS	1996	DBLP DOI BibTeX RDF	surface phenomena, electric charge, CMOS opens, die surface, RC interconnect, HSPICE simulations, trapped charge, floating gates, VLSI, integrated circuit testing, CMOS integrated circuits, integrated circuit modelling, circuit model
31	Mohamed Soufi, Steve Rochon, Yvon Savaria, Bozena Kaminska	Design and performance of CMOS TSPC cells for high speed pseudo random testing.	VTS	1996	DBLP DOI BibTeX RDF	CMOS TSPC cells, high speed pseudo random testing, built-in self-test scheme, HSpice simulations, functionally equivalent logic block, true single phase clocking, logic testing, built-in self test, integrated circuit testing, logic CAD, layout, circuit analysis computing, clocks, circuit layout CAD, CMOS logic circuits, SPICE, cellular arrays, integrated circuit layout, test methodology, untestable faults, netlists
31	Masaru Sanada	A CAD-based approach to failure diagnosis of CMOS LSI's using abnormal Iddq.	VTS	1996	DBLP DOI BibTeX RDF	CAD-based failure diagnosis technology, CMOS LSI, abnormal Iddq phenomenon, physical damage detection, faulty blocks, failure point localization, Iddq test patterns, fault diagnosis, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, circuit CAD, large scale integration
31	G. Enrique Fernandez, R. Sridhar	Dual rail static CMOS architecture for wave pipelining.	VLSI Design	1996	DBLP DOI BibTeX RDF	dual rail static CMOS architecture, gate capacitance, storage elements, DRSCMOS, multi-functional basic building blocks, combinational logic block, delays, timing, throughput, combinational circuits, power consumption, pipeline processing, CMOS logic circuits, digital systems, capacitance, wave pipelining, delay variations
31	Pradip Mandal, V. Visvanathan	Design of high performance two stage CMOS cascode op-amps with stable biasing.	VLSI Design	1996	DBLP DOI BibTeX RDF	two stage CMOS cascode op-amps, stable biasing, mirror biasing, output voltage, bias variations, low frequency common mode rejection ratios, power supply rejection ratios, systematic offset, circuit analysis computing, performance metrics, integrated circuit design, circuit simulations, operational amplifiers, CMOS analogue integrated circuits, slew rate, circuit stability
31	Hassan Ihs, Christian Dufaza	Tolerance DC bands of CMOS operational amplifier.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	tolerance DC bands, CMOS operational amplifier, DC node voltages, data tolerance bands, foundry process fluctuations, DC branch current, OA, supply voltage, catastrophic defects, transistor connections, optimization, fault diagnosis, integrated circuit testing, fault detection, fault model, fault simulation, circuit optimisation, operational amplifiers, integrated circuit modelling, transistor size, CMOS analogue integrated circuits, design parameters
31	Junya Kudoh, Toshiro Takahashi, Yukio Umada, Masaharu Kimura, Shigeru Yamamoto, Youichi Ito	A CMOS gate array with dynamic-termination GTL I/O circuits.	ICCD	1995	DBLP DOI BibTeX RDF	CMOS gate array, dynamic-termination GTL I/O circuits, triple-metal-layer process technology, push-pull output driver, dynamic termination receiver, 250 Mb/s data, stub line, terminated bus line, IDDQ testability, differential receiver, delay time overheads, 0.5 micron, 250 Mbit/s, logic testing, delays, CMOS logic circuits, logic arrays
31	Gary C. Moyer, Mark Clements, Wentai Liu, Toby Schaffer, Ralph K. Cavin III	A technique for high-speed, fine-resolution pattern generation and its CMOS implementation.	ARVLSI	1995	DBLP DOI BibTeX RDF	high-speed fine-resolution pattern generation, data signals, edge placement, matched delays, MOSIS CMOS technology, 100 ps, 833 Mbit/s, architecture, delays, test pattern generators, network interfaces, CMOS digital integrated circuits, 1.2 micron
31	John D. Bunda, Donald S. Fussell, William C. Athas	Energy-efficient instruction set architecture for CMOS microprocessors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	energy-efficient instruction set architecture, CMOS microprocessors, portable battery-based applications, performance-driven designs, processor architecture tradeoffs, program encoding size, instruction set richness, energy cost, speculative instruction fetching, execution resources, instruction-level parallel machines, multiple-path instruction fetching, high execution bandwidth, power management, microprocessor chips, instruction sets, power dissipation, CMOS digital integrated circuits, reduced instruction set computing, cooling, design constraint, instruction delivery, code density
31	Enrico Macii, Massimo Poncino	Estimating worst-case power consumption of CMOS circuits modeled as symbolic neural networks.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	worst-case power consumption, symbolic neural networks, gate level description, symbolic domain, algebraic decision diagrams, graph specification, delays, combinational circuits, combinational circuits, logic CAD, circuit analysis computing, CMOS logic circuits, CMOS circuits, integrated circuit modelling, energy dissipation
31	L. F. Fuller, C. Kraaijenvanger	Design and manufacture of a 2K transistor p-well CMOS gate array in a student run factory at RIT.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	educational aids, p-well CMOS gate array, student run factory, microelectronic engineering program, wafer fabrication, logic design, integrated circuit design, integrated circuit design, CMOS logic circuits, logic arrays, teaching tool, integrated circuit manufacture, integrated circuit manufacturing, electronic engineering education
31	Jaume A. Segura 0001, Miquel Roca 0001, Diego Mateo, Antonio Rubio 0001	An approach to dynamic power consumption current testing of CMOS ICs.	VTS	1995	DBLP DOI BibTeX RDF	dynamic power consumption current testing, logic behavior, parametric defect, quiescent power supply current testing, consumption current testing time, on-chip sensor, static power consumption, fault diagnosis, logic testing, integrated circuit testing, automatic testing, adders, CMOS logic circuits, I/sub DDQ/ testing, CMOS ICs, full adders, open defects, electric current measurement, bridging defects, transient current
31	Josep Rius 0001, Joan Figueras	Detecting IDDQ defective CMOS circuits by depowering.	VTS	1995	DBLP DOI BibTeX RDF	I/sub DDQ/ defective CMOS circuits, depowering, fault detection capabilities, quiescent state, logic valves, discharge current, power supply line disconnection, logic testing, integrated circuit testing, fault location, CMOS logic circuits, capacitance
31	Varna Puvvada, S. Potla, S. Tamizh Selvam, P. R. Suresh	A simulation study on the effectiveness of n-guardring/p-guardring on latchup in 0.8 μm CMOS technology.	VLSI Design	1995	DBLP DOI BibTeX RDF	integrated circuit technology, n-guardring, p-guardring, latchup prevention, remote transient, I/O buffer n-channel transistor, 2D device simulator, TMA-MEDICI, substrate resistance, 0.8 micron, VLSI, circuit analysis computing, CMOS integrated circuits, CMOS technology, transients, steady state simulation
31	George A. Hadgis, P. R. Mukund	A novel CMOS monolithic analog multiplier with wide input dynamic range.	VLSI Design	1995	DBLP DOI BibTeX RDF	analogue multipliers, circuit feedback, CMOS monolithic analog multiplier, input dynamic range, voltage-controlled variable linear resistor, feedback network, PSpice simulation results, circuit analysis computing, linearity, SPICE, operational amplifiers, operational amplifier, CMOS analogue integrated circuits
31	Manjit Borah, Mary Jane Irwin, Robert Michael Owens	Minimizing power consumption of static CMOS circuits by transistor sizing and input reordering.	VLSI Design	1995	DBLP DOI BibTeX RDF	power consumption minimisation, static CMOS circuits, input reordering, high fan-out gates, power constrained module generator, PowerSizer, logic CAD, circuit layout CAD, CMOS logic circuits, logic circuits, minimisation, arithmetic circuits, circuit optimisation, integrated circuit layout, transistor sizing
30	Ming Liu 0022, Haigang Yang, Sansiri Tanachutiwat, Wei Wang 0003	Carbon Nanotube Nanorelays with Pass-Transistor for FPGA Routing Devices.	NanoNet	2009	DBLP DOI BibTeX RDF	carbon nanorelay, nanoelectromechanical switch, CMOS-nano hybrid, FPGA, carbon nanotube
29	Nishant Chandra, Apoorva Kumar Yati, A. B. Bhattacharyya	Extended-Sakurai-Newton MOSFET Model for Ultra-Deep-Submicrometer CMOS Digital Design.	VLSI Design	2009	DBLP DOI BibTeX RDF
29	Hamed F. Dadgour, Kaustav Banerjee	Design and Analysis of Hybrid NEMS-CMOS Circuits for Ultra Low-Power Applications.	DAC	2007	DBLP DOI BibTeX RDF
29	Sumeer Goel, Ashok Kumar 0001, Magdy A. Bayoumi	Design of Robust, Energy-Efficient Full Adders for Deep-Submicrometer Design Using Hybrid-CMOS Logic Style.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
29	S. M. Rezaul Hasan	A Novel 16-bit CMOS Digitally Controlled Oscillator.	APCCAS	2006	DBLP DOI BibTeX RDF
29	Congguang Yang, Maciej J. Ciesielski	Synthesis for Mixed CMOS/PTl Logic.	DATE	2000	DBLP DOI BibTeX RDF
29	Yu-Chuan Shih, Chung-Yu Wu	The design of high-performance 128×128 CMOS image sensors using new current-readout techniques.	ISCAS (5)	1999	DBLP DOI BibTeX RDF
29	Rochit Rajsuman, Anura P. Jayasumana, Yashwant K. Malaiya	CMOS Stuck-open Fault Detection Using Single Test Patterns.	DAC	1989	DBLP DOI BibTeX RDF
28	Yu-Hao Hsu, Min-Sheng Kao, Hou-Cheng Tzeng, Ching-Te Chiu, Jen-Ming Wu, Shuo-Hung Hsu	A 20 Gbps Scalable Load Balanced Birkhoff-von Neumann Symmetric TDM Switch IC with SERDES Interfaces.	ASP-DAC	2007	DBLP DOI BibTeX RDF	Birkhoff-von Neumann symmetric TDM switch IC, SERDES interfaces, load-balanced TDM switch IC, digital TDM switch, 8B10B CODEC, analog SERDES I/O interfaces, dual-mode SERDES, half-rate architectures, all static CMOS gates, wide-band CML buffer, PMOS active load scheme, 20 Gbit/s, high speed networking, CMOS technology, low power consumption, 0.18 micron
28	Peter Wohl, John A. Waicukauski, Matthew Graf	Testing "untestable" faults in three-state circuits.	VTS	1996	DBLP DOI BibTeX RDF	three-state circuits, complex CMOS designs, nonconventional circuits, test generation techniques, circuit particularities, fault diagnosis, logic testing, integrated circuit testing, automatic testing, CMOS logic circuits, test coverage, multivalued logic circuits, computer testing, CPU time, test vector generation, untestable faults, automatic learning