Search results for "edram"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
160	Chris Wilkerson, Alaa R. Alameldeen, Zeshan Chishti, Wei Wu 0024, Dinesh Somasekhar, Shih-Lien Lu	Reducing cache power with low-cost, multi-bit error-correcting codes.	ISCA	2010	DBLP DOI BibTeX RDF	ecc, edram, idle power, idle states, multi-bit ecc, refresh power, vccmin, dram
131	Valentina Salapura, José R. Brunheroto, Fernando F. Redígolo, Alan Gara	Exploiting eDRAM bandwidth with data prefetching: simulation and measurements.	ICCD	2007	DBLP DOI BibTeX RDF
67	Laurent Lopez, Jean-Michel Portal, Didier Née	A New Embedded Measurement Structure for eDRAM Capacitor.	DATE	2005	DBLP DOI BibTeX RDF
67	Yong-Ha Park, Jeonghoon Kook, Hoi-Jun Yoo	Embedded DRAM (eDRAM) Power-Energy Estimation for System-on-a-Chip (SoC) Applications.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF	power estimation, embedded DRAM
64	Wei Zhang 0032, Ki Chul Chun, Chris H. Kim	Variation aware performance analysis of gain cell embedded DRAMs.	ISLPED	2010	DBLP DOI BibTeX RDF	bitline delay, gain cell, process variation, monte carlo simulation, embedded DRAM
48	Yuhao Shu, Hongtu Zhang, Hao Sun, Qi Deng, Yajun Ha	CSDB-eDRAM: A 16Kb Energy-Efficient 4T CSDB Gain Cell eDRAM with over 16.6s Retention Time and 49.23uW/Kb at 4.2K for Cryogenic Computing.	ISCAS	2023	DBLP DOI BibTeX RDF
43	Rouwaida Kanj, Rajiv V. Joshi, Jente B. Kuang, J. Kim, Mesut Meterelliyoz, William R. Reohr, Sani R. Nassif, Kevin J. Nowka	Statistical yield analysis of silicon-on-insulator embedded DRAM.	ISQED	2009	DBLP DOI BibTeX RDF
43	Mango Chia-Tso Chao, Hao-Yu Yang, Rei-Fu Huang, Shih-Chin Lin, Ching-Yu Chin	Fault models for embedded-DRAM macros.	DAC	2009	DBLP DOI BibTeX RDF	memory testing, embedded DRAM
43	Brian R. Kessler, Jeffrey H. Dreibelbis, Tim McMahon, Joshua S. McCloy, Rex Kho	BIST-Based Bitfail Mapping of an Embedded DRAM.	MTDT	2001	DBLP DOI BibTeX RDF
31	Ronald N. Kalla, Balaram Sinharoy, William J. Starke, Michael S. Floyd	Power7: IBM's Next-Generation Server Processor.	IEEE Micro	2010	DBLP DOI BibTeX RDF	Power7, eDRAM, DDR3, SMT operation, PowerPC architecture, processor, IBM, RAS
31	Linda Dailey Paulson	News Briefs.	Computer	2007	DBLP DOI BibTeX RDF	nanodevices, memory-chip technology, eDRAM, mobile computing, optical networks, handheld devices
24	Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha, Juhyoung Lee, Sangyeob Kim, Donghyeon Han, Hoi-Jun Yoo	DynaPlasia: An eDRAM In-Memory Computing-Based Reconfigurable Spatial Accelerator With Triple-Mode Cell.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
24	Jiahao Song, Xiyuan Tang, Haoyang Luo, Haoyi Zhang, Xin Qiao, Zixuan Sun, Xiangxing Yang, Zihan Wu, Yuan Wang 0001, Runsheng Wang, Ru Huang	A 4-bit Calibration-Free Computing-In-Memory Macro With 3T1C Current-Programed Dynamic-Cascode Multi-Level-Cell eDRAM.	IEEE J. Solid State Circuits	2024	DBLP DOI BibTeX RDF
24	Jialong Liu, Wenjun Tang, Hongtian Li, Deyun Chen, Weihang Long, Yongpan Liu, Chen Jiang, Huazhong Yang, Xueqing Li	TFT-Based Near-Sensor In-Memory Computing: Circuits and Architecture Perspectives of Large-Area eDRAM and ROM CiM Chips.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
24	In Jun Jung, Do Han Kim, Minyoung Jo, Dong Han Ko, Young Kyu Lee, Seong-Ook Jung	A Charge-Domain 4T2C eDRAM Compute-in-Memory Macro With Enhanced Variation Tolerance and Low-Overhead Data Conversion Schemes.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
24	Yifan He, Shupei Fan, Xuan Li, Luchang Lei, Wenbin Jia, Chen Tang, Yaolei Li, Zongle Huang, Zhike Du, Jinshan Yue, Xueqing Li, Huazhong Yang, Hongyang Jia, Yongpan Liu	34.7 A 28nm 2.4Mb/mm2 6.9 - 16.3TOPS/mm2 eDRAM-LUT-Based Digital-Computing-in-Memory Macro with In-Memory Encoding and Refreshing.	ISSCC	2024	DBLP DOI BibTeX RDF
24	Jiahao Song, Zihan Wu, Xiyuan Tang, Bocheng Xu, Haoyang Luo, Youming Yang 0002, Yuan Wang 0001, Runsheng Wang, Ru Huang	30.5 A Variation-Tolerant In-eDRAM Continuous-Time Ising Machine Featuring 15-Level Coefficients and Leaked Negative-Feedback Annealing.	ISSCC	2024	DBLP DOI BibTeX RDF
24	Wenjun Tang, Jialong Liu, Chen Sun 0010, Zijie Zheng, Yongpan Liu, Huazhong Yang, Chen Jiang, Kai Ni 0004, Xiao Gong, Xueqing Li	Low-Power and Scalable BEOL-Compatible IGZO TFT eDRAM-Based Charge-Domain Computing.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
24	Duy-Thanh Nguyen, Abhiroop Bhattacharjee, Abhishek Moitra, Priyadarshini Panda	MCAIMem: a Mixed SRAM and eDRAM Cell for Area and Energy-efficient on-chip AI Memory.	CoRR	2023	DBLP DOI BibTeX RDF
24	Subin Kim, Ingu Jeong, Jun-Eun Park	An N-Type Pseudo-Static eDRAM Macro with Reduced Access Time for High-Speed Processing-in-Memory in Intelligent Sensor Hub Applications.	Sensors	2023	DBLP DOI BibTeX RDF
24	Mengtian Yang, Yipeng Wang 0017, Jaydeep P. Kulkarni	A 118 GOPS/mm23D eDRAM TensorCore Architecture for Large-scale Matrix Multiplication.	HiPC	2023	DBLP DOI BibTeX RDF
24	Sangjin Kim, Soyeon Um, Wooyoung Jo, Jingu Lee, Sangwoo Ha, Zhiyong Li, Hoi-Jun Yoo	Scaling-CIM: An eDRAM-based In-Memory-Computing Accelerator with Dynamic-Scaling ADC for SQNR-Boosting and Layer-wise Adaptive Bit-Truncation.	VLSI Technology and Circuits	2023	DBLP DOI BibTeX RDF
24	Jiahao Song, Xiyuan Tang, Haoyang Luo, Haoyi Zhang, Xin Qiao, Zixuan Sun, Xiangxing Yang, Yuan Wang 0001, Runsheng Wang, Ru Huang	A Calibration-Free 15-level/Cell eDRAM Computing-in-Memory Macro with 3T1C Current-Programmed Dynamic-Cascoded MLC achieving 233-to-304-TOPS/W 4b MAC.	CICC	2023	DBLP DOI BibTeX RDF
24	Sangjin Kim, Zhiyong Li, Soyeon Um, Wooyoung Jo, Sangwoo Ha, Juhyoung Lee, Sangyeob Kim, Donghyeon Han, Hoi-Jun Yoo	DynaPlasia: An eDRAM In-Memory-Computing-Based Reconfigurable Spatial Accelerator with Triple-Mode Cell for Dynamic Resource Switching.	ISSCC	2023	DBLP DOI BibTeX RDF
24	Seryeong Kim, Soyeon Kim, Soyeon Um, Sangjin Kim, Zhiyong Li, Sangyeob Kim, Wooyoung Jo, Hoi-Jun Yoo	A Reconfigurable 1T1C eDRAM-based Spiking Neural Network Computing-In-Memory Processor for High System-Level Efficiency.	ISCAS	2023	DBLP DOI BibTeX RDF
24	Mayank Kabra, Prashanth H. C., Kedar Deshpande, Madhav Rao	eDRAM-OESP: A novel performance efficient in-embedded-DRAM-compute design for on-edge signal processing application.	ISQED	2023	DBLP DOI BibTeX RDF
24	Inhwan Lee, Eunhwan Kim, Nameun Kang, Hyunmyung Oh, Jae-Joon Kim	In-Memory Neural Network Accelerator based on eDRAM Cell with Enhanced Retention Time.	DAC	2023	DBLP DOI BibTeX RDF
24	Sangwoo Ha, Sangjin Kim, Donghyeon Han, Soyeon Um, Hoi-Jun Yoo	A 36.2 dB High SNR and PVT/Leakage-Robust eDRAM Computing-In-Memory Macro With Segmented BL and Reference Cell Array.	IEEE Trans. Circuits Syst. II Express Briefs	2022	DBLP DOI BibTeX RDF
24	Bahareh Seyedzadeh Sany, Behzad Ebrahimi	A 1-GHz GC-eDRAM in 7-nm FinFET with static retention time at 700 mV for ultra-low power on-chip memory applications.	Int. J. Circuit Theory Appl.	2022	DBLP DOI BibTeX RDF
24	Sangwoo Jung, Jaehyun Lee, Huiseong Noh, Jong-Hyeok Yoon, Jaeha Kung	DualPIM: A Dual-Precision and Low-Power CNN Inference Engine Using SRAM- and eDRAM-based Processing-in-Memory Arrays.	AICAS	2022	DBLP DOI BibTeX RDF
24	Shanshan Xie, Can Ni, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni	Gain-Cell CIM: Leakage and Bitline Swing Aware 2T1C Gain-Cell eDRAM Compute in Memory Design with Bitline Precharge DACs and Compact Schmitt Trigger ADCs.	VLSI Technology and Circuits	2022	DBLP DOI BibTeX RDF
24	Junyi Zhou, Roger Kahn, Shlomo Weiss	A novel low power hybrid cache using GC-EDRAM cells.	Integr.	2021	DBLP DOI BibTeX RDF
24	Shanshan Liu 0001, Pedro Reviriego, Jing Guo 0004, Jie Han 0001, Fabrizio Lombardi	Exploiting Asymmetry in eDRAM Errors for Redundancy-Free Error-Tolerant Design.	IEEE Trans. Emerg. Top. Comput.	2021	DBLP DOI BibTeX RDF
24	Chengshuo Yu, Taegeun Yoo, Hyunjoon Kim, Tony Tae-Hyoung Kim, Kevin Chai Tshun Chuan, Bongjin Kim	A Logic-Compatible eDRAM Compute-In-Memory With Embedded ADCs for Processing Neural Networks.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
24	Shi Rong Soo, Afiq Hamzah, Nurul Ezaila Alias, Izam Kamisian, Michael Loong Peng Tan, Suhaila Isaak, Zaharah Johari	Design of Low Power Gain-Cell eDRAM for 4Kb Memory Array in 130nm CMOS.	ICEEI	2021	DBLP DOI BibTeX RDF
24	Rakshith Saligram, Suman Datta, Arijit Raychowdhury	CryoMem: A 4K-300K 1.3GHz eDRAM Macro with Hybrid 2T-Gain-Cell in a 28nm Logic Process for Cryogenic Applications.	CICC	2021	DBLP DOI BibTeX RDF
24	Shanshan Xie, Can Ni, Aseem Sayal, Pulkit Jain, Fatih Hamzaoglu, Jaydeep P. Kulkarni	16.2 eDRAM-CIM: Compute-In-Memory Design with Reconfigurable Embedded-Dynamic-Memory Array Realizing Adaptive Data Converters and Charge-Domain Computing.	ISSCC	2021	DBLP DOI BibTeX RDF
24	Siddhartha Raman Sundara Raman, Shanshan Xie, Jaydeep P. Kulkarni	Compute-in-eDRAM with Backend Integrated Indium Gallium Zinc Oxide Transistors.	ISCAS	2021	DBLP DOI BibTeX RDF
24	Tzachi Noy, Adam Teman	Design of a Refresh-Controller for GC-eDRAM Based FIFOs.	IEEE Trans. Circuits Syst.	2020	DBLP DOI BibTeX RDF
24	Ramin Rajaei, Yen-Kai Lin, Sayeef S. Salahuddin, Michael T. Niemier, Xiaobo Sharon Hu	GC-eDRAM design using hybrid FinFET/NC-FinFET.	ISLPED	2020	DBLP DOI BibTeX RDF
24	Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman	GC-eDRAM with Body-Bias Compensated Readout and Error Detection in 28nm FD-SOI.	ISCAS	2020	DBLP DOI BibTeX RDF
24	Roman Golman, Robert Giterman, Odem Harel, Adam Teman	Improved Read Access in GC-eDRAM Memory by Dual-Negative Word-Line Technique.	ISCAS	2020	DBLP DOI BibTeX RDF
24	Robert Giterman, Andrea Bonetti, Andreas Burg, Adam Teman	GC-eDRAM With Body-Bias Compensated Readout and Error Detection in 28-nm FD-SOI.	IEEE Trans. Circuits Syst. II Express Briefs	2019	DBLP DOI BibTeX RDF
24	Jonathan Narinx, Robert Giterman, Andrea Bonetti, Nicolas Frigerio, Cosimo Aprile, Andreas Burg, Yusuf Leblebici	A 24 kb Single-Well Mixed 3T Gain-Cell eDRAM with Body-Bias in 28 nm FD-SOI for Refresh-Free DSP Applications.	A-SSCC	2019	DBLP DOI BibTeX RDF
24	Mehul Tikekar, Vivienne Sze, Anantha P. Chandrakasan	A Fully Integrated Energy-Efficient H.265/HEVC Decoder With eDRAM for Wearable Devices.	IEEE J. Solid State Circuits	2018	DBLP DOI BibTeX RDF
24	Navid Khoshavi, Ronald F. DeMara	Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Optimization.	IEEE Access	2018	DBLP DOI BibTeX RDF
24	Binyamin Frankel, Roi Herman, Shmuel Wimer	Queuing-Based eDRAM Refreshing for Ultra-Low Power Processors.	IEEE Trans. Computers	2018	DBLP DOI BibTeX RDF
24	Sivasundar Manisankar, Yeonbae Chung	P-channel logic 2 T eDRAM macro with high retention bit architecture.	Int. J. Circuit Theory Appl.	2018	DBLP DOI BibTeX RDF
24	Amir Shalom, Robert Giterman, Adam Teman	High Density GC-eDRAM Design in 16nm FinFET.	ICECS	2018	DBLP DOI BibTeX RDF
24	Masayuki Sato 0001, Zehua Li, Ryusuke Egawa, Hiroaki Kobayashi	An energy-aware set-level refreshing mechanism for eDRAM last-level caches.	COOL CHIPS	2018	DBLP DOI BibTeX RDF
24	Or Maltabashi, Hanan Marinberg, Robert Giterman, Adam Teman	A 5-Transistor Ternary Gain-Cell eDRAM with Parallel Sensing.	ISCAS	2018	DBLP DOI BibTeX RDF
24	Joonho Kong, Young-Ho Gong, Sung Woo Chung	Towards refresh-optimized EDRAM-based caches with a selective fine-grain round-robin refresh scheme.	Microprocess. Microsystems	2017	DBLP DOI BibTeX RDF
24	Joonho Kong, Young-Ho Gong	An efficient trade-off between yield and energy for eDRAM caches under process variations.	Microprocess. Microsystems	2017	DBLP DOI BibTeX RDF
24	Robert Giterman, Adam Teman, Pascal Meinerzhagen	Hybrid GC-eDRAM/SRAM Bitcell for Robust Low-Power Operation.	IEEE Trans. Circuits Syst. II Express Briefs	2017	DBLP DOI BibTeX RDF
24	Keng-Hao Yang, Hsiang-Jen Tsai, Chia-Yin Li, Paul Jendra, Meng-Fan Chang, Tien-Fu Chen	eTag: Tag-Comparison in Memory to Achieve Direct Data Access based on eDRAM to Improve Energy Efficiency of DRAM Cache.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
24	Esteve Amat, Antonio Calomarde, Ramon Canal, Antonio Rubio 0001	Suitability of FinFET introduction into eDRAM cells for operate at sub-threshold level.	PATMOS	2017	DBLP DOI BibTeX RDF
24	Naifeng Jing, Li Jiang 0002, Tao Zhang 0046, Chao Li 0009, Fengfeng Fan, Xiaoyao Liang	Energy-Efficient eDRAM-Based On-Chip Storage Architecture for GPGPUs.	IEEE Trans. Computers	2016	DBLP DOI BibTeX RDF
24	Young-Ho Gong, Jae Min Kim, Sung Kyu Lim, Sung Woo Chung	Exploration of temperature-aware refresh schemes for 3D stacked eDRAM caches.	Microprocess. Microsystems	2016	DBLP DOI BibTeX RDF
24	Navid Khoshavi, Xunchao Chen, Jun Wang 0001, Ronald F. DeMara	Read-Tuned STT-RAM and eDRAM Cache Hierarchies for Throughput and Energy Enhancement.	CoRR	2016	DBLP BibTeX RDF
24	Donghwan Jeong, Young H. Oh, Jae W. Lee, Yongjun Park 0001	An eDRAM-Based Approximate Register File for GPUs.	IEEE Des. Test	2016	DBLP DOI BibTeX RDF
24	Amit Kazimirsky, Shmuel Wimer	Opportunistic Refreshing Algorithm for eDRAM Memories.	IEEE Trans. Circuits Syst. I Regul. Pap.	2016	DBLP DOI BibTeX RDF
24	Navid Khoshavi, Xunchao Chen, Jun Wang 0001, Ronald F. DeMara	Bit-Upset Vulnerability Factor for eDRAM Last Level Cache immunity analysis.	ISQED	2016	DBLP DOI BibTeX RDF
24	Woong Choi, Gyuseong Kang, Jongsun Park 0001	A Refresh-Less eDRAM Macro With Embedded Voltage Reference and Selective Read for an Area and Power Efficient Viterbi Decoder.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
24	Alejandro Valero, Salvador Petit, Julio Sahuquillo, David R. Kaeli, José Duato	A reuse-based refresh policy for energy-aware eDRAM caches.	Microprocess. Microsystems	2015	DBLP DOI BibTeX RDF
24	Matt Poremba, Sparsh Mittal, Dong Li 0001, Jeffrey S. Vetter, Yuan Xie 0001	DESTINY: a tool for modeling emerging 3D NVM and eDRAM caches.	DATE	2015	DBLP BibTeX RDF
24	Cheng Li 0011, Paul Ampadu	A compact low-power eDRAM-based NoC buffer.	ISLPED	2015	DBLP DOI BibTeX RDF
24	Mu-Shan Lin, Chien-Chun Tsai, Chih-Hsien Chang, Wen-Hung Huang, Ying-Yu Hsu, Shu-Chun Yang, Chin-Ming Fu, Mao-Hsuan Chou, Tien-Chien Huang, Ching-Fang Chen, Tze-Chiang Huang, Saman Adham, Min-Jer Wang, William Wu Shen, Ashok Mehta	A 1 Tbit/s Bandwidth 1024 b PLL/DLL-Less eDRAM PHY Using 0.3 V 0.105 mW/Gbps Low-Swing IO for CoWoS Application.	IEEE J. Solid State Circuits	2014	DBLP DOI BibTeX RDF
24	Aditya Agrawal, Amin Ansari, Josep Torrellas	Mosaic: Exploiting the spatial locality of process variation to reduce refresh energy in on-chip eDRAM modules.	HPCA	2014	DBLP DOI BibTeX RDF
24	Kyungsang Cho, Yongjun Lee, Young H. Oh, Gyoo-Cheol Hwang, Jae W. Lee	eDRAM-based tiered-reliability memory with applications to low-power frame buffers.	ISLPED	2014	DBLP DOI BibTeX RDF
24	Hisashi Iwamoto, Yuji Yano, Yasuto Kuroda, Koji Yamamoto 0002, Kazunari Inoue, Ikuo Oka	A 250 Msps, 0.5 W eDRAM-Based Search Engine Dedicated Low Power FIB Application.	IEICE Trans. Electron.	2013	DBLP DOI BibTeX RDF
24	Mu-Tien Chang, Paul Rosenfeld, Shih-Lien Lu, Bruce L. Jacob	Technology comparison for large last-level caches (L3Cs): Low-leakage SRAM, low write-energy STT-RAM, and refresh-optimized eDRAM.	HPCA	2013	DBLP DOI BibTeX RDF
24	Alejandro Valero, Julio Sahuquillo, Salvador Petit, José Duato	Exploiting reuse information to reduce refresh energy in on-chip eDRAM caches.	ICS	2013	DBLP DOI BibTeX RDF
24	Young-Ho Gong, Hyung Beom Jang, Sung Woo Chung	Performance and cache access time of SRAM-eDRAM hybrid caches considering wire delay.	ISQED	2013	DBLP DOI BibTeX RDF
24	Naifeng Jing, Yao Shen, Yao Lu, Shrikanth Ganapathy, Zhigang Mao, Minyi Guo, Ramon Canal, Xiaoyao Liang	An energy-efficient and scalable eDRAM-based register file architecture for GPGPU.	ISCA	2013	DBLP DOI BibTeX RDF
24	Alejandro Valero, Salvador Petit, Julio Sahuquillo, Pedro López 0001, José Duato	Design, Performance, and Energy Consumption of eDRAM/SRAM Macrocells for L1 Data Caches.	IEEE Trans. Computers	2012	DBLP DOI BibTeX RDF
24	Mohammad Alizadeh, Adel Javanmard, Shang-Tse Chuang, Sundar Iyer, Yi Lu 0001	Versatile refresh: low complexity refresh scheduling for high-throughput multi-banked eDRAM.	SIGMETRICS	2012	DBLP DOI BibTeX RDF
24	Yasuto Kuroda, Yuji Yano, Hisashi Iwamoto, Koji Yamamoto 0002, Kazunari Inoue, Masahiro Suzuki	A 200Msps, 0.6W eDRAM-based search engine applying full-route capacity dedicated FIB application.	CICC	2012	DBLP DOI BibTeX RDF
24	Matt Wordeman, Joel Silberman, Gary W. Maier, Michael Scheuermann	A 3D system prototype of an eDRAM cache stacked over processor-like logic using through-silicon vias.	ISSCC	2012	DBLP DOI BibTeX RDF
24	Javier Lira, Carlos Molina, David M. Brooks, Antonio González 0001	Implementing a hybrid SRAM / eDRAM NUCA architecture.	HiPC	2011	DBLP DOI BibTeX RDF
24	Bing Yan, Yufeng Xie, Rui Yuan, Yinyin Lin	A BIST scheme for high-speed Gain Cell eDRAM.	ASICON	2011	DBLP DOI BibTeX RDF
24	Mesut Meterelliyoz, Jaydeep P. Kulkarni, Kaushik Roy 0001	Analysis of SRAM and eDRAM Cache Memories Under Spatial Temperature Variations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2010	DBLP DOI BibTeX RDF
24	Remi Pulicani, Olivier Goducheau, Hubert Degoirat, Hassen Aziza, Annie Pérez, Emmanuel Bergeret	Simulation of intrinsic bipolar transistor mechanisms for future capacitor-less eDRAM on bulk substrate.	ICECS	2010	DBLP DOI BibTeX RDF
24	Stanley Schuster, Richard E. Matick	Fast Low Power eDRAM Hierarchical Differential Sense Amplifier.	IEEE J. Solid State Circuits	2009	DBLP DOI BibTeX RDF
24	Alejandro Valero, Julio Sahuquillo, Salvador Petit, Vicente Lorente, Ramon Canal, Pedro López 0001, José Duato	An hybrid eDRAM/SRAM macrocell to implement first-level data caches.	MICRO	2009	DBLP DOI BibTeX RDF	retention time, static and dynamic memory cells, leakage current
24	Jente B. Kuang, Abraham Mathews, John Barth 0001, Fadi H. Gebara, Tuyet Nguyen, Jeremy D. Schaub, Kevin J. Nowka, Gary D. Carpenter, Don Plass, Erik Nelson, Ivan Vo, William R. Reohr, Toshiaki Kirihata	An on-chip dual supply charge pump system for 45nm PD SOI eDRAM.	ESSCIRC	2008	DBLP DOI BibTeX RDF
24	Hillary Hunter	Tutorial 5: Caches in the Many-Core Era: What Purpose Might eDRAM Serve?	ISQED	2008	DBLP DOI BibTeX RDF
24	Laurent Lopez, Jean-Michel Portal, Didier Née	A New Embedded Measurement Structure for eDRAM Capacitor	CoRR	2007	DBLP BibTeX RDF
24	Richard E. Matick, Stanley Schuster	Logic-based eDRAM: Origins and rationale for use.	IBM J. Res. Dev.	2005	DBLP BibTeX RDF
24	Martin Ohmacht, Dirk Hoenicke, Ruud A. Haring, Alan Gara	The eDRAM based L3-Cache of the BlueGene/L Supercomputer Processor Node.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
24	Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo	A practical method to use eDRAM in the shared bus packet switch.	GLOBECOM	2002	DBLP DOI BibTeX RDF
24	David Bondurant	Low Latency EDRAM Main Memory Subsystem for 66MHz Bus Operation.	COMPCON	1994	DBLP DOI BibTeX RDF
24	Kent Stalnaker	Practical Test Methods for Verification of the EDRAM.	ITC	1994	DBLP DOI BibTeX RDF
21	Ki Chul Chun, Pulkit Jain, Chris H. Kim	A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM.	ISLPED	2009	DBLP DOI BibTeX RDF	3T DRAM, gain cell, retention time, cache, static power, embedded DRAM
21	Xiaoxia Wu, Jian Li 0059, Lixin Zhang 0002, Evan Speight, Ramakrishnan Rajamony, Yuan Xie 0001	Hybrid cache architecture with disparate memory technologies.	ISCA	2009	DBLP DOI BibTeX RDF	hybrid cache architecture, three-dimensional ic
21	Jaime H. Moreno	Chip-level integration: the new frontier for microprocessor architecture.	SPAA	2006	DBLP DOI BibTeX RDF	chip-level integration, microprocessor architecture
21	Zaid Al-Ars, Ad J. van de Goor	Static and Dynamic Behavior of Memory Cell Array Spot Defects in Embedded DRAMs.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	dynamic faulty behavior, functional fault models, defect simulation, spot defects, Embedded DRAM, fault primitives
21	Zaid Al-Ars, Ad J. van de Goor	Impact of memory cell array bridges on the faulty behavior in embedded DRAMs.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	memory cell array bridges, memory fault models, dynamic faulty behavior, dynamic RAM, fault simulation, memory tests, circuit simulation, random-access storage, integrated memory circuits, functional faults, embedded DRAMs, faulty behavior, fault primitives