Search results for "global-interconnect"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
59	Jian Li 0061, Rajesh K. Gupta 0001	An Algorithm To Determine Mutually Exclusive Operations In Behavioral Descriptions.	DATE	1998	DBLP DOI BibTeX RDF
57	Basab Datta, Wayne P. Burleson	Analysis and mitigation of NBTI-impact on PVT variability in repeated global interconnect performance.	ACM Great Lakes Symposium on VLSI	2010	DBLP DOI BibTeX RDF	tunable buffer, variability, NBTI, global-interconnect
53	Andrew B. Kahng, Sudhakar Muddu, Egino Sarto, Rahul Sharma	Interconnect Tuning Strategies for High-Performance Ics.	DATE	1998	DBLP DOI BibTeX RDF
50	Jason Cong, Lei He 0001, Cheng-Kok Koh, David Zhigang Pan	Global interconnect sizing and spacing with consideration of coupling capacitance.	ICCAD	1997	DBLP DOI BibTeX RDF	GISS solutions, asymmetric wire sizing, delay reduction, fringing capacitances, global interconnect sizing and spacing, global wire sizing, interconnect delay minimization, multiple nets, optimal wire sizing, spacing solution, symmetric effective fringing properties, VLSI, coupling capacitance
49	Navneeth Kankani, Vineet Agarwal, Janet Meiling Wang	A probabilistic analysis of pipelined global interconnect under process variations.	ASP-DAC	2006	DBLP DOI BibTeX RDF
49	Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen	Wave-pipelined on-chip global interconnect.	ASP-DAC	2005	DBLP DOI BibTeX RDF
42	DiaaEldin Khalil, Yehea I. Ismail	A global interconnect link design for many-core microprocessors.	IFMT	2008	DBLP DOI BibTeX RDF	interconnect, link, bus, repeater insertion
42	Lizheng Zhang, Yuhen Hu, Charlie Chung-Ping Chen	Statistical timing analysis in sequential circuit for on-chip global interconnect pipelining.	DAC	2004	DBLP DOI BibTeX RDF	interconnect pipelining, statistical timing analysis
39	Emrah Acar, Sani R. Nassif, Ying Liu, Lawrence T. Pileggi	Time-Domain Simulation of Variational Interconnect Models.	ISQED	2002	DBLP DOI BibTeX RDF	simulation, Interconnect, variational models, reduced order modeling
34	Xiaoling Sun, A. Alimohammad, Pieter M. Trouborst	Modeling of FPGA Local/Global Interconnect Resources and Derivation of Minimal Test Configurations.	DFT	2002	DBLP DOI BibTeX RDF	global/local interconnect testing, modeling, graph coloring, greedy algorithms, FPGA testing
34	Min Ni, Seda Ogrenci Memik	Self-heating-aware optimal wire sizing under Elmore delay model.	DATE	2007	DBLP DOI BibTeX RDF
34	Yehia Massoud, Arthur Nieuwoudt	Modeling and design challenges and solutions for carbon nanotube-based interconnect in future high performance integrated circuits.	ACM J. Emerg. Technol. Comput. Syst.	2006	DBLP DOI BibTeX RDF	nanotube bundle, interconnect, inductance, Carbon nanotube, resistance
33	Abinash Roy, Masud H. Chowdhury	Impacts of Inductance on the Figures of Merit to Optimize Global Interconnect.	APCCAS	2006	DBLP DOI BibTeX RDF
31	Terrence S. T. Mak, N. Pete Sedcole, Peter Y. K. Cheung, Wayne Luk	High-throughput interconnect wave-pipelining for global communication in FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF
31	Dennis Sylvester, Kurt Keutzer	A global wiring paradigm for deep submicron design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
30	Basel Halak, Santosh Shedabale, Hiran Ramakrishnan, Alexandre Yakovlev, Gordon Russell 0002	The impact of variability on the reliability of long on-chip interconnect in the presence of crosstalk.	SLIP	2008	DBLP DOI BibTeX RDF	cross-talk, interconnect, variability, Bit Error Rate(BER)
30	Jason Cong, Lei He 0001	Theory and algorithm of local-refinement-based optimization with application to device and interconnect sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
29	M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni	A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization.	PATMOS	2003	DBLP DOI BibTeX RDF
28	Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001	Statistical crosstalk aggressor alignment aware interconnect delay calculation.	SLIP	2006	DBLP DOI BibTeX RDF
28	Ankireddy Nalamalpu, Sriram Srinivasan, Wayne P. Burleson	Boosters for driving long onchip interconnects - design issues, interconnect synthesis, and comparison with repeaters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
28	Abinash Roy, Masud H. Chowdhury	Global Interconnect Optimization in the Presence of On-chip Inductance.	ISCAS	2007	DBLP DOI BibTeX RDF
27	Ahmed Youssef, Tor Myklebust, Mohab Anis, Mohamed I. Elmasry	A Low-Power Multi-Pin Maze Routing Methodology.	ISQED	2007	DBLP DOI BibTeX RDF
27	Amir H. Ajami, Kaustav Banerjee, Massoud Pedram	Modeling and analysis of nonuniform substrate temperature effects on global ULSI interconnects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
27	Kaustav Banerjee, Amit Mehrotra	Inductance Aware Interconnect Scaling.	ISQED	2002	DBLP DOI BibTeX RDF
25	Vinita V. Deodhar, Jeffrey A. Davis	Optimization of throughput performance for low-power VLSI interconnects.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
24	Min Tang, Jun-Fa Mao	Optimization of Global Interconnects in High Performance VLSI Circuits.	VLSI Design	2006	DBLP DOI BibTeX RDF
24	Yici Cai, Yibo Wang, Xianlong Hong	A global interconnect optimization algorithm under accurate delay model using solution space smoothing.	ISCAS (1)	2005	DBLP DOI BibTeX RDF
22	Ajay Joshi, Jeffrey A. Davis	A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI).	SLIP	2004	DBLP DOI BibTeX RDF	interconnect area, wire sharing, time-division multiplexing
19	Jingye Xu, Pervez Khaled, Masud H. Chowdhury	Fast bus waveform estimation at the presence of coupling noise.	ACM Great Lakes Symposium on VLSI	2008	DBLP DOI BibTeX RDF	coupling noise, global interconnect
19	Jonggab Kil, Jie Gu 0003, Chris H. Kim	A high-speed variation-tolerant interconnect technique for sub threshold circuits using capacitive boosting.	ISLPED	2006	DBLP DOI BibTeX RDF	capacitive boosting, sub-threshold circuit, clock skew, global interconnect, variation tolerance
19	Jason Cong, Yiping Fan, Zhiru Zhang	Architecture-level synthesis for automatic interconnect pipelining.	DAC	2004	DBLP DOI BibTeX RDF	interconnect pipelining, multi-cycle communication, scheduling, high-level synthesis, register binding
18	Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001	Statistical Timing Analysis in the Presence of Signal-Integrity Effects.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
18	Youngsoo Shin, Hyung-Ock Kim	Analysis of power consumption in VLSI global interconnects.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
18	Lilian Bossuet, Wayne P. Burleson, Guy Gogniat, Vikas Anand, Andrew Laffely, Jean Luc Philippe	Targeting Tiled Architectures in Design Exploration.	IPDPS	2003	DBLP DOI BibTeX RDF
18	Pranav Anbalagan, Jeffrey A. Davis	Maximum multiplicity distributions (MMD).	SLIP	2003	DBLP DOI BibTeX RDF	system-level prediction, wire-length distributions, simulated annealing
18	Jason Cong, Lei He 0001	An efficient technique for device and interconnect optimization in deep submicron designs.	ISPD	1998	DBLP DOI BibTeX RDF
16	Siad Daboul, Stephan Held, Bento Natura, Daniel Rotter	Global Interconnect Optimization.	ACM Trans. Design Autom. Electr. Syst.	2023	DBLP DOI BibTeX RDF
16	Mark A. Anders 0001, Himanshu Kaul, Seongjong Kim, Gregory K. Chen, Raghavan Kumar, Huseyin Ekin Sumbul, Phil C. Knag, Monodeep Kar, Steven K. Hsu, Amit Agarwal 0001, Vikram B. Suresh, Sanu K. Mathew, Ram K. Krishnamurthy, Vivek De	25.9 Reconfigurable Transient Current-Mode Global Interconnect Circuits in 10nm CMOS for High-Performance Processors with Wide Voltage-Frequency Operating Range.	ISSCC	2020	DBLP DOI BibTeX RDF
16	Siad Daboul, Stephan Held, Bento Natura, Daniel Rotter	Global Interconnect Optimization.	ICCAD	2019	DBLP DOI BibTeX RDF
16	Adarsha Balaji, Yuefeng Wu, Anup Das 0001, Francky Catthoor, Siebren Schaafsma	Exploration of Segmented Bus As Scalable Global Interconnect for Neuromorphic Computing.	ACM Great Lakes Symposium on VLSI	2019	DBLP DOI BibTeX RDF
16	Zubair Al Azim, Akhilesh Jaiswal 0001, Indranil Chakraborty, Kaushik Roy 0001	Capacitively Driven Global Interconnect with Magnetoelectric Switching Based Receiver for Higher Energy Efficiency.	CoRR	2018	DBLP BibTeX RDF
16	Igor Gadelha Pereira, Leonardo Alves Dias, Cleonilson Protásio de Souza	A Shift-Register Based BIST Architecture for FPGA Global Interconnect Testing and Diagnosis.	J. Electron. Test.	2015	DBLP DOI BibTeX RDF
16	Jianfei Jiang 0001, Weifeng He, Jizeng Wei, Qin Wang 0009, Zhigang Mao	Design optimization for capacitive-resistively driven on-chip global interconnect.	IEICE Electron. Express	2015	DBLP DOI BibTeX RDF
16	Oluseyi A. Ayorinde, Benton H. Calhoun	Circuit optimizations to minimize energy in the global interconnect of a low-power-FPGA (abstract only).	FPGA	2013	DBLP DOI BibTeX RDF
16	Shuo Li 0002, Ahmed Hemani	Global Interconnect and Control Synthesis in System Level Architectural Synthesis Framework.	DSD	2013	DBLP DOI BibTeX RDF
16	Jianfei Jiang 0001, Wei-Guang Sheng, Zhi-Gang Mao, Wei-Feng He	A pre-emphasis circuit design for high speed on-chip global interconnect.	ISCAS	2012	DBLP DOI BibTeX RDF
16	Jianfei Jiang 0001, Xu Wang, Wei-Guang Sheng, Wei-Feng He, Zhi-Gang Mao	A clock-less transceiver for global interconnect.	VLSI-SoC	2011	DBLP DOI BibTeX RDF
16	Zaixiao Zheng, Zhigang Mao, Jianfei Jiang 0001	An efficient 90nm technology-node GHz transceiver of on-chip global interconnect.	ASICON	2011	DBLP DOI BibTeX RDF
16	Taemin Kim, Xun Liu	A global interconnect reduction technique during high level synthesis.	ASP-DAC	2010	DBLP DOI BibTeX RDF
16	Suwen Yang, Robert J. Drost, Mark R. Greenstreet, Shahriar Mirabbasi, Frank O'Mahony	Varactor-based signal restoration for near-speed-of-light surfing global interconnect.	CICC	2010	DBLP DOI BibTeX RDF
16	Mohammad Moghaddam Tabrizi, Nasser Masoumi	Low-power and high-performance techniques in global interconnect signaling.	Microelectron. J.	2009	DBLP DOI BibTeX RDF
16	Yulei Zhang 0002, Ling Zhang, Alina Deutsch, George A. Katopis, Daniel M. Dreps, James F. Buckwalter, Ernest S. Kuh, Chung-Kuan Cheng	Design methodology of high performance on-chip global interconnect using terminated transmission-line.	ISQED	2009	DBLP DOI BibTeX RDF
16	Cheng-Kok Koh, Evangeline F. Y. Young, Yao-Wen Chang	Global Interconnect Planning.	Handbook of Algorithms for Physical Design Automation	2008	DBLP DOI BibTeX RDF
16	Prashant Singh, Jae-sun Seo, David T. Blaauw, Dennis Sylvester	Self-Timed Regenerators for High-Speed and Low-Power On-Chip Global Interconnect.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
16	Wei-Sheng Huang, Yu-Ru Hong, Juinn-Dar Huang, Ya-Shih Huang	A multicycle communication architecture and synthesis flow for Global interconnect Resource Sharing.	ASP-DAC	2008	DBLP DOI BibTeX RDF
16	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Optimization technique for flip-flop inserted global interconnect.	ISCAS	2008	DBLP DOI BibTeX RDF
16	Jingye Xu, Abinash Roy, Masud H. Chowdhury	Power Consumption and BER of Flip-Flop Inserted Global Interconnect.	VLSI Design	2007	DBLP DOI BibTeX RDF
16	Jennifer L. Wong, Seapahn Megerian, Miodrag Potkonjak	Minimizing Global Interconnect in DSP Systems using Bypassing.	ICASSP (2)	2007	DBLP DOI BibTeX RDF
16	Yoichi Yuyama, Akira Tsuchiya, Kazutoshi Kobayashi, Hidetoshi Onodera	Alternate Self-Shielding for High-Speed and Reliable On-Chip Global Interconnect.	IEICE Trans. Electron.	2006	DBLP DOI BibTeX RDF
16	Lele Jiang, Junfa Mao	Global Interconnect Analysis and Optimization for Nanometer Scale VLSI.	APCCAS	2006	DBLP DOI BibTeX RDF
16	Jinsook Kim, Weiping Ni, Edwin C. Kan	A novel global interconnect method using nonlinear transmission lines.	CICC	2005	DBLP DOI BibTeX RDF
16	Vinita V. Deodhar, Jeffrey A. Davis	Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
16	James W. Joyner, Payman Zarkesh-Ha, James D. Meindl	Global interconnect design in a three-dimensional system-on-a-chip.	IEEE Trans. Very Large Scale Integr. Syst.	2004	DBLP DOI BibTeX RDF
16	Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni	Effects of temperature in deep-submicron global interconnect optimization in future technology nodes.	Microelectron. J.	2004	DBLP DOI BibTeX RDF
16	Yuantao Peng, Xun Liu	Global interconnect optimization with simultaneous macrocell placement and repeater insertion.	SoCC	2004	DBLP DOI BibTeX RDF
16	Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni	Effects of Temperature in Deep-Submicron Global Interconnect Optimization.	PATMOS	2003	DBLP DOI BibTeX RDF
16	Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex	Global interconnect trade-off for technology over memory modules to application level: case study.	SLIP	2003	DBLP DOI BibTeX RDF	Pareto-optimal energy/delay interconnect exploration, interconnect wire processing, intra/inter-memory interconnect
16	Yu Cao 0001, Chenming Hu, Xuejue Huang, Andrew B. Kahng, Sudhakar Muddu, Dirk Stroobandt, Dennis Sylvester	Effects of Global Interconnect Optimizations on Performance Estimation of Deep Submicron Design.	ICCAD	2000	DBLP DOI BibTeX RDF
16	Andrew A. Duncan, David C. Hendry	DSP datapath synthesis eliminating global interconnect.	EURO-DAC	1993	DBLP DOI BibTeX RDF
15	Mark J. Cianchetti, Joseph C. Kerekes, David H. Albonesi	Phastlane: a rapid transit optical routing network.	ISCA	2009	DBLP DOI BibTeX RDF	interconnection networks, multicore, optical interconnects, nanophotonics
15	Stephan Bourduas, Zeljko Zilic	A Hybrid Ring/Mesh Interconnect for Network-on-Chip Using Hierarchical Rings for Global Routing.	NOCS	2007	DBLP DOI BibTeX RDF
15	Ahmed Youssef, Mohab Anis, Mohamed I. Elmasry	POMR: a power-aware interconnect optimization methodology.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
15	John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Diana Franklin, Venkatesh Akella, Frederic T. Chong	Synchroscalar: A Multiple Clock Domain, Power-Aware, Tile-Based Embedded Processor.	ISCA	2004	DBLP DOI BibTeX RDF
15	John Y. Oliver, Ravishankar Rao, Paul Sultana, Jedidiah R. Crandall, Erik Czernikowski, Leslie W. Jones IV, Dean Copsey, Diana Keen, Venkatesh Akella, Frederic T. Chong	Synchroscalar: Initial Lessons in Power-Aware Design of a Tile-Based Embedded Architecture.	PACS	2003	DBLP DOI BibTeX RDF
15	Vinita V. Deodhar, Jeffrey A. Davis	Voltage scaling and repeater insertion for high-throughput low-power interconnects.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
15	Paul Wielage, Kees Goossens	Networks on Silicon: Blessing or Nightmare?	DSD	2002	DBLP DOI BibTeX RDF
13	M.-C. Frank Chang, Eran Socher, Sai-Wang Tam, Jason Cong, Glenn Reinman	RF interconnects for communications on-chip.	ISPD	2008	DBLP DOI BibTeX RDF	RF-interconnect, network-on-chip, chip multiprocessors
13	Chittarsu Raghunandan, K. S. Sainarayanan, M. B. Srinivas	Bus-encoding technique to reduce delay, power and simultaneous switching noise (SSN) in RLC interconnects.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	bit transitions, bus-encoding scheme, high impedance state, simultaneous switching noise (SSN), spatial and temporal redundancy, low power, delay, encoder, decoder, crosstalk noise, inductive coupling
13	Yu Ching Chang, King Ho Tam, Lei He 0001	Power-optimal repeater insertion considering Vdd and Vth as design freedoms.	ISLPED	2005	DBLP DOI BibTeX RDF	low power, buffer insertion
13	Ray Robert Rydberg III, Jabulani Nyathi, José G. Delgado-Frias	A distributed FIFO scheme for on chip communication.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
13	Charles J. Alpert, Anirudh Devgan, Stephen T. Quay	Buffer insertion for noise and delay optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1999	DBLP DOI BibTeX RDF
13	Leon Stok	Interconnect optimisation during data path allocation.	EURO-DAC	1990	DBLP DOI BibTeX RDF
11	Jason Cong, Sung Kyu Lim	Retiming-based timing analysis with an application to mincut-based global placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
11	Kenneth L. Shepard, Vinod Narayanan, Peter C. Elmendorf, Gutuan Zheng	Global harmony: coupled noise analysis for full-chip RC interconnect networks.	ICCAD	1997	DBLP DOI BibTeX RDF	interconnect, noise, static timing analysis
9	Ashutosh Chakraborty, David Z. Pan	On stress aware active area sizing, gate sizing, and repeater insertion.	ISPD	2009	DBLP DOI BibTeX RDF	performance, buffer, sizing, stress, repeater
9	Christianto C. Liu, Jeng-Huei Chen, Rajit Manohar, Sandip Tiwari	Mapping system-on-chip designs from 2-D to 3-D ICs.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
9	Hua Tang, Hui Zhang 0057, Alex Doboli	Layout-Aware Analog System Synthesis Based on Symbolic Layout Description and Combined Block Parameter Exploration, Placement and Global Routing.	ISVLSI	2003	DBLP DOI BibTeX RDF
9	Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky	Provably good global buffering by generalized multiterminalmulticommodity flow approximation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2002	DBLP DOI BibTeX RDF
9	Feodor F. Dragan, Andrew B. Kahng, Ion I. Mandoiu, Sudhakar Muddu, Alexander Zelikovsky	Provably good global buffering by multi-terminal multicommodity flow approximation.	ASP-DAC	2001	DBLP DOI BibTeX RDF
9	Pierre G. Paulin, John P. Knight	Force-directed scheduling for the behavioral synthesis of ASICs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
7	Yu-Ju Hong, Ya-Shih Huang, Juinn-Dar Huang	Simultaneous data transfer routing and scheduling for interconnect minimization in multicycle communication architecture.	ASP-DAC	2009	DBLP DOI BibTeX RDF
7	Ja Chun Ku, Yehea I. Ismail	Thermal-Aware Methodology for Repeater Insertion in Low-Power VLSI Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
7	Masaru Takesue	The SKB: A Semi-Completely-Connected Bus for On-Chip Systems.	NPC	2007	DBLP DOI BibTeX RDF
7	Ja Chun Ku, Yehea I. Ismail	Thermal-aware methodology for repeater insertion in low-power VLSI circuits.	ISLPED	2007	DBLP DOI BibTeX RDF	low-power design, repeater insertion, temperature-aware design
7	Jeonghwan Choi, Chen-Yong Cher, Hubertus Franke, Hendrik F. Hamann, Alan J. Weger, Pradip Bose	Thermal-aware task scheduling at the system software level.	ISLPED	2007	DBLP DOI BibTeX RDF	low-power design, repeater insertion, temperature-aware design
7	Milenko Drinic, Darko Kirovski, Seapahn Megerian, Miodrag Potkonjak	Latency-Guided On-Chip Bus-Network Design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
7	Marc Duranton	The Challenges for High Performance Embedded Systems.	DSD	2006	DBLP DOI BibTeX RDF
7	Zhanyuan Jiang, Shiyan Hu, Jiang Hu, Zhuo Li 0001, Weiping Shi	A new RLC buffer insertion algorithm.	ICCAD	2006	DBLP DOI BibTeX RDF
7	Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001	Statistical gate delay calculation with crosstalk alignment consideration.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF
7	Yu Cao 0001, Xuejue Huang, Dennis Sylvester, Tsu-Jae King 0001, Chenming Hu	Impact of on-chip interconnect frequency-dependent R(f)L(f) on digital and RF design.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF