Search results for "logic-in-memory"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
30	Takahiro Hanyu, Hiromitsu Kimura, Michitaka Kameyama	DRAM-Cell-Based Multiple-Valued Logic-in-Memory VLSI with Charge Addition and Charge Storage.	ISMVL	2000	DBLP DOI BibTeX RDF	logic-in-memory, communication bottleneck, threshold operation, functional pass gate, DRAM, multiple-valued logic
30	Thomas L. Sterling	An Introduction to the Gilgamesh PIM Architecture.	Euro-Par	2001	DBLP DOI BibTeX RDF
24	Masanori Hariyama, Michitaka Kameyama, Yasuhiro Kobayashi	Optimal Periodical Memory Allocation for Logic-in-Memory Image Processors.	ISVLSI	2006	DBLP DOI BibTeX RDF
24	Mohamed I. Elmasry, Philip M. Thompson	Two-Level Emitter-Function Logic Structures for Logic-in-Memory Computers.	IEEE Trans. Computers	1975	DBLP DOI BibTeX RDF	emitter-function logic (EFL), high-speed realization, logic-in memory (LIM) computers, multiemitter two-level structures (METTL), large-scale integration (LSI), Current-mode logic
23	Shunichi Kaeriyama, Takahiro Hanyu, Michitaka Kameyama	Arithmetic-Oriented Multiple-Valued Logic-in-Memory VLSI Based on Current-Mode Logic.	ISMVL	2000	DBLP DOI BibTeX RDF
13	Evelyn T. Breyer, Halid Mulaosmanovic, Jens Trommer, Thomas Melde, Stefan Dünkel, Martin Trentzsch, Sven Beyer, Thomas Mikolajick, Stefan Slesazeck	Ultra-dense co-integration of FeFETs and CMOS logic enabling very-fine grained Logic-in-Memory.	ESSDERC	2019	DBLP DOI BibTeX RDF
13	Fabrizio Riente, Grazvydas Ziemys, Giovanna Turvani, Doris Schmitt-Landsiedel, Stephan Breitkreutz-v. Gamm, Mariagrazia Graziano	Towards Logic-In-Memory circuits using 3D-integrated Nanomagnetic logic.	ICRC	2016	DBLP DOI BibTeX RDF
13	Mario Cofano, Giulia Santoro, Marco Vacca, D. Pala, Giovanni Causapruno, Fabrizio Cairo, Fabrizio Riente, Giovanna Turvani, Massimo Ruo Roch, Mariagrazia Graziano, Maurizio Zamboni	Logic-in-Memory: A Nano Magnet Logic Implementation.	ISVLSI	2015	DBLP DOI BibTeX RDF
13	Hiwa Mahmoudi, Thomas Windbacher, Viktor Sverdlov, Siegfried Selberherr	MRAM-based logic array for large-scale non-volatile logic-in-memory applications.	NANOARCH	2013	DBLP DOI BibTeX RDF
13	Masanori Natsui, Takahiro Hanyu, Noboru Sakimura, Tadahiko Sugibayashi	MTJ/MOS-hybrid logic-circuit design flow for nonvolatile logic-in-memory LSI.	ISCAS	2013	DBLP DOI BibTeX RDF
13	Takahiro Hanyu, Shunichi Kaeriyama, Michitaka Kameyama	Logic-in-Memory VLSI circuit for Fully Parallel Nearest Pattern Matching Based on Floating-Gate-MOS Pass-Transistor Logic.	J. Multiple Valued Log. Soft Comput.	2005	DBLP BibTeX RDF
13	Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama, Yoshikazu Fujimori, Takashi Nakamura, Hidemi Takasu	Complementary ferroelectric-capacitor logic for low-power logic-in-memory VLSI.	IEEE J. Solid State Circuits	2004	DBLP DOI BibTeX RDF
13	Takahiro Hanyu, Kaname Teranishi, Michitaka Kameyama	Multiple-Valued Floating-Gate-MOS Pass Logic and its Application to Logic-in-Memory VLSI.	ISMVL	1998	DBLP DOI BibTeX RDF
13	Fabrizio Ottati, Giovanna Turvani, Marco Vacca, Guido Masera	Custom Memory Design for Logic-in-Memory: Drawbacks and Improvements over Conventional Memories.	CoRR	2023	DBLP DOI BibTeX RDF
13	Lichuan Luo, He Zhang 0011, Jinyu Bai, Youguang Zhang, Wang Kang 0001, Weisheng Zhao	SpinLiM: Spin Orbit Torque Memory for Ternary Neural Networks Based on the Logic-in-Memory Architecture.	DATE	2021	DBLP DOI BibTeX RDF
13	Supreet Jeloka, Naveen Bharathwaj Akesh, Dennis Sylvester, David T. Blaauw	A 28 nm Configurable Memory (TCAM/BCAM/SRAM) Using Push-Rule 6T Bit Cell Enabling Logic-in-Memory.	IEEE J. Solid State Circuits	2016	DBLP DOI BibTeX RDF
13	Naifeng Jing, Taozhong Li, Zhongyuan Zhao 0004, Wei Jin 0004, Yanan Sun 0003, Weifeng He, Zhigang Mao	Enabling in-situ logic-in-memory capability using resistive-RAM crossbar memory.	FPT	2016	DBLP DOI BibTeX RDF
13	Hooman Jarollahi, Naoya Onizawa, Vincent Gripon, Noboru Sakimura, Tadahiko Sugibayashi, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu, Warren J. Gross	A Nonvolatile Associative Memory-Based Context-Driven Search Engine Using 90 nm CMOS/MTJ-Hybrid Logic-in-Memory Architecture.	IEEE J. Emerg. Sel. Topics Circuits Syst.	2014	DBLP DOI BibTeX RDF
13	Viktor Sverdlov, Hiwa Mahmoudi, Alexander Makarov, Siegfried Selberherr	Magnetic tunnel junctions for future memory and logic-in-memory applications.	MIXDES	2014	DBLP DOI BibTeX RDF
13	Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama	Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition.	ISMVL	2002	DBLP DOI BibTeX RDF	Ferroelectric capacitor, multiple-valued current-mode logic circuit, arithmetic operation, full adder
11	Esmail Amini, Mehrdad Najibi, Hossein Pedram	Globally Asynchronous Locally Synchronous Wrapper Circuit based on Clock Gating.	ISVLSI	2006	DBLP DOI BibTeX RDF
10	Mamoru Tanaka, Shinji Ozawa, Shinsaku Mori	Rewritable Progammable Logic Array of Current Mode Logic.	IEEE Trans. Computers	1981	DBLP DOI BibTeX RDF	Array logic, functional memory, logic-in-memory, associative memory, PLA, LSI, CML
9	Bhogi Satya Swaroop, Ayush Saxena, Shubham Sahay	Satisfiability Attack-Resilient Camouflaged Multiple Multivariable Logic-in-Memory Exploiting 3D NAND Flash Array.	IEEE Trans. Circuits Syst. I Regul. Pap.	2024	DBLP DOI BibTeX RDF
9	YaJuan Hui, Qingzhen Li, Cheng Liu 0008, Deming Zhang, Xiangshui Miao	Logic-in-Memory Based on Majority Gates With Voltage-Gated SOT-MRAM Crossbar Arrays.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
9	Pietro Inglese, Elena Ioana Vatajelu, Giorgio Di Natale	Side Channel and Fault Analyses on Memristor-Based Logic In-Memory.	IEEE Des. Test	2024	DBLP DOI BibTeX RDF
9	Sueyeon Kim, Insoo Choi, Sangki Cho, Myounggon Kang, Seungjae Baik, Changho Ra, Jongwook Jeon	Analysis of Logic-in-Memory Full Adder Circuit With Floating Gate Field Effect Transistor (FGFET).	IEEE Access	2023	DBLP DOI BibTeX RDF
9	Bi Wu, Haonan Zhu, Ke Chen 0018, Chenggang Yan 0002, Weiqiang Liu 0001	MLiM: High-Performance Magnetic Logic in-Memory Scheme With Unipolar Switching SOT-MRAM.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
9	Yanan Sun 0003, Zhi Li, Weiyi Liu, Weifeng He, Qin Wang 0009, Zhigang Mao	BC-MVLiM: A Binary-Compatible Multi-Valued Logic-in-Memory Based on Memristive Crossbars.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
9	Wenjun Tang, Mingyen Lee, Juejian Wu, Yixin Xu, Yao Yu, Yongpan Liu, Kai Ni 0004, Yu Wang 0002, Huazhong Yang, Vijaykrishnan Narayanan, Xueqing Li	FeFET-Based Logic-in-Memory Supporting SA-Free Write-Back and Fully Dynamic Access With Reduced Bitline Charging Activity and Recycled Bitline Charge.	IEEE Trans. Circuits Syst. I Regul. Pap.	2023	DBLP DOI BibTeX RDF
9	Jagadish Rajpoot, Shivam Verma	Area-Efficient Auto-Write-Terminate Circuit for NV Latch and Logic-In-Memory Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
9	Longfei Li, Qijing Wang, Mengjiao Pei, Hengyuan Wang, Jianhang Guo, Ziqian Hao, Yating Li, Qinyong Dai, Kuakua Lu, Yun Li	Integration of Neuromorphic and Reconfigurable Logic-in-Memory Operations in an Electrolyte-Manipulated Ferroelectric Organic Neuristor.	Adv. Intell. Syst.	2023	DBLP DOI BibTeX RDF
9	Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Leticia Bolzani Poehls, Rainer Leupers	Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware.	CoRR	2023	DBLP DOI BibTeX RDF
9	Jia-Hui Su, Chen-Hua Lu, Jenq-Kuen Lee, Andrea Coluccio, Fabrizio Riente, Marco Vacca, Marco Ottavi, Kuan-Hsun Chen	Simulation Environment with Customized RISC-V Instructions for Logic-in-Memory Architectures.	CoRR	2023	DBLP DOI BibTeX RDF
9	Simranjeet Singh, Chandan Kumar Jha 0001, Ankit Bende, Vikas Rana, Sachin B. Patkar, Rolf Drechsler, Farhad Merchant	MemSPICE: Automated Simulation and Energy Estimation Framework for MAGIC-Based Logic-in-Memory.	CoRR	2023	DBLP DOI BibTeX RDF
9	Yi Xiao, Yixin Xu, Shan Deng, Zijian Zhao, Sumitha George, Kai Ni 0004, Vijaykrishnan Narayanan	A Compact Ferroelectric 2T-(n+1)C Cell to Implement AND-OR Logic in Memory.	ISVLSI	2023	DBLP DOI BibTeX RDF
9	Cédric Marchand 0002, Alban Nicolas, Paul-Antoine Matrangolo, David Navarro, Alberto Bosio, Ian O'Connor	FeFET based Logic-in-Memory design methodologies, tools and open challenges.	VLSI-SoC	2023	DBLP DOI BibTeX RDF
9	Libo Shen, Boyu Long, Rui Liu, Xiaoyu Zhang 0009, Yinhe Han 0001, Xiaoming Chen 0003	LIM-GEN: A Data-Guided Framework for Automated Generation of Heterogeneous Logic-in-Memory Architecture.	ICCAD	2023	DBLP DOI BibTeX RDF
9	Tianchi Liu 0005, Yizhuo Zhou, Yakun Zhou, Zheng Chai, Jienan Chen	Hardware Efficient Reconfigurable Logic-in-Memory Circuit Based Neural Network Computing.	ISCAS	2023	DBLP DOI BibTeX RDF
9	Yihe Liu, Junjie Wang 0008, Shuang Liu, Mingyuan Sun, Kai Tang, Guohui Ren, Xindi Zhao, Mingliang Sun, Yang Liu 0062	A Programmable Logic-in-Memory Architecture Based on 22nm Fully DepletedSilicon on Insulator Technology.	CECCT	2023	DBLP DOI BibTeX RDF
9	Felix Staudigl, Thorben Fetz, Rebecca Pelke, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers	Fault Injection in Native Logic-in-Memory Computation on Neuromorphic Hardware.	DAC	2023	DBLP DOI BibTeX RDF
9	Jian Chen, Wenfeng Zhao, Yuqi Wang, Yuhao Shu, Weixiong Jiang, Yajun Ha	A Reliable 8T SRAM for High-Speed Searching and Logic-in-Memory Operations.	IEEE Trans. Very Large Scale Integr. Syst.	2022	DBLP DOI BibTeX RDF
9	Raffaele De Rose, Tommaso Zanotti, Francesco Maria Puglisi, Felice Crupi, Paolo Pavan, Marco Lanuzza	Smart Material Implication Using Spin-Transfer Torque Magnetic Tunnel Junctions for Logic-in-Memory Computing.	CoRR	2022	DBLP DOI BibTeX RDF
9	Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers	X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation.	CoRR	2022	DBLP DOI BibTeX RDF
9	Felix Staudigl, Karl J. X. Sturm, Maximilian Bartel, Thorben Fetz, Dominik Sisejkovic, Jan Moritz Joseph, Letícia Maria Bolzani Pöhls, Rainer Leupers	X-Fault: Impact of Faults on Binary Neural Networks in Memristor-Crossbar Arrays with Logic-in-Memory Computation.	AICAS	2022	DBLP DOI BibTeX RDF
9	Kai Liu, Bi Wu, Haonan Zhu, Weiqiang Liu 0001	High-performance STT-MRAM Logic-in-Memory Scheme Utilizing Data Read Features.	NANOARCH	2022	DBLP DOI BibTeX RDF
9	Ashkan Samiee, Payal Borulkar, Ronald F. DeMara, Peiyi Zhao, Yu Bai 0004	Low-Energy Acceleration of Binarized Convolutional Neural Networks Using a Spin Hall Effect Based Logic-in-Memory Architecture.	IEEE Trans. Emerg. Top. Comput.	2021	DBLP DOI BibTeX RDF
9	Javad Talafy, Farzaneh Zokaee, Hamid R. Zarandi, Nader Bagherzadeh	A High Performance, Multi-Bit Output Logic-in-Memory Adder.	IEEE Trans. Emerg. Top. Comput.	2021	DBLP DOI BibTeX RDF
9	Ali Zarei, Farshad Safaei	LIMITA: Logic-in-Memory Primitives for Imprecise Tolerant Applications.	IEEE Trans. Circuits Syst. I Regul. Pap.	2021	DBLP DOI BibTeX RDF
9	Minhui Zou, Junlong Zhou, Jin Sun 0001, Chengliang Wang, Shahar Kvatinsky	Improving Efficiency and Lifetime of Logic-in-Memory by Combining IMPLY and MAGIC Families.	J. Syst. Archit.	2021	DBLP DOI BibTeX RDF
9	Tianhong Shen, Yanan Sun 0003, Weifeng He, Zhi Li, Weiyi Liu, Zhezhi He, Li Jiang 0002	A Ternary Memristive Logic-in-Memory Design for Fast Data Scan.	ICTA	2021	DBLP DOI BibTeX RDF
9	Shuhang Zhang, Hai Li 0001, Ulf Schlichtmann	Peripheral Circuitry Assisted Mapping Framework for Resistive Logic-In-Memory Computing.	ICCAD	2021	DBLP DOI BibTeX RDF
9	Weiyi Liu, Yanan Sun 0003, Weifeng He, Qin Wang 0009	Design of Ternary Logic-in-Memory Based on Memristive Dual-Crossbars.	ISCAS	2021	DBLP DOI BibTeX RDF
9	Wei Chang, Yu-Guang Chen, Po-Yeh Huang, Jin-Fu Li 0001	An Aging-Aware CMOS SRAM Structure Design for Boolean Logic In-Memory Computing.	DFT	2021	DBLP DOI BibTeX RDF
9	Pietro Inglese, Elena Ioana Vatajelu, Giorgio Di Natale	On the Limitations of Concatenating Boolean Operations in Memristive-Based Logic-In-Memory Solutions.	DTIS	2021	DBLP DOI BibTeX RDF
9	Cédric Marchand 0002, Ian O'Connor, Mayeul Cantan, Evelyn T. Breyer, Stefan Slesazeck, Thomas Mikolajick	FeFET based Logic-in-Memory: an overview.	DTIS	2021	DBLP DOI BibTeX RDF
9	Tommaso Zanotti, Francesco Maria Puglisi, Paolo Pavan	Circuit Reliability Analysis of RRAM-based Logic-in-Memory Crossbar Architectures Including Line Parasitic Effects, Variability, and Random Telegraph Noise.	IRPS	2020	DBLP DOI BibTeX RDF
9	Esteban Garzón, Benjamin Zambrano, Tatiana Moposita, Ramiro Taco, Luis-Miguel Prócel, Lionel Trojman	Reconfigurable CMOS/STT-MTJ Non-Volatile Circuit for Logic-in-Memory Applications.	LASCAS	2020	DBLP DOI BibTeX RDF
9	Tommaso Zanotti, Francesco Maria Puglisi, Paolo Pavan	Smart Logic-in-Memory Architecture For Ultra-Low Power Large Fan-In Operations.	AICAS	2020	DBLP DOI BibTeX RDF
9	Mingyen Lee, Wenjun Tang, Bowen Xue, Juejian Wu, Mingyuan Ma, Yu Wang 0002, Yongpan Liu, Deliang Fan, Vijaykrishnan Narayanan, Huazhong Yang, Xueqing Li	FeFET-based low-power bitwise logic-in-memory with direct write-back and data-adaptive dynamic sensing interface.	ISLPED	2020	DBLP DOI BibTeX RDF
9	Himanshu Thapliyal, S. Dinesh Kumar	Special Session: A Novel Low-Power and Energy-Efficient Adiabatic Logic-In-Memory Architecture Using CMOS/MTJ.	ICCD	2020	DBLP DOI BibTeX RDF
9	Mario Cofano, Marco Vacca, Giulia Santoro, Giovanni Causapruno, Giovanna Turvani, Mariagrazia Graziano	Exploiting the Logic-In-Memory paradigm for speeding-up data-intensive algorithms.	Integr.	2019	DBLP DOI BibTeX RDF
9	Ashkan Samiee, Yunchuan Sun, Ronald F. DeMara, Yoonsuk Choi, Yu Bai 0004	Energy Efficient Mobile Service Computing With Differential Spintronic-C-Elements: A Logic-in-Memory Asynchronous Computing Paradigm.	IEEE Access	2019	DBLP DOI BibTeX RDF
9	Xunzhao Yin, Xiaoming Chen 0003, Michael T. Niemier, Xiaobo Sharon Hu	Ferroelectric FETs-Based Nonvolatile Logic-in-Memory Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2019	DBLP DOI BibTeX RDF
9	Daisuke Suzuki, Takahiro Oka, Takahiro Hanyu	Circuit optimization technique of nonvolatile logic-in-memory based lookup table circuits using magnetic tunnel junction devices.	Microelectron. J.	2019	DBLP DOI BibTeX RDF
9	Francesco Maria Puglisi, Tommaso Zanotti, Paolo Pavan	SIMPLY: Design of a RRAM-Based Smart Logic-in-Memory Architecture using RRAM Compact Model.	ESSDERC	2019	DBLP DOI BibTeX RDF
9	Xiaoming Chen 0003, Longxiang Yin, Bosheng Liu, Yinhe Han 0001	Merging Everything (ME): A Unified FPGA Architecture Based on Logic-in-Memory Techniques.	DAC	2019	DBLP DOI BibTeX RDF
9	Advait Madhavan, Tim Sherwood, Dmitri B. Strukov	High-Throughput Pattern Matching With CMOL FPGA Circuits: Case for Logic-in-Memory Computing.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
9	Soheil Salehi, Ronald F. DeMara	SLIM-ADC: Spin-based Logic-In-Memory Analog to Digital Converter leveraging SHE-enabled Domain Wall Motion devices.	Microelectron. J.	2018	DBLP DOI BibTeX RDF
9	Sandeep Kaur Kingra, Vivek Parmar, Che-Chia Chang, Boris Hudec, Tuo-Hung Hou, Manan Suri	SLIM: Simultaneous Logic-in-Memory Computing Exploiting Bilayer Analog OxRAM Devices.	CoRR	2018	DBLP BibTeX RDF
9	Francesco Maria Puglisi, Lorenzo Pacchioni, Nicolo Zagni, Paolo Pavan	Energy-Efficient Logic-in-Memory I-bit Full Adder Enabled by a Physics-Based RRAM Compact Model.	ESSDERC	2018	DBLP DOI BibTeX RDF
9	Marco Vacca, Yaswanth Tavva, Anupam Chattopadhyay, Andrea Calimera	Logic-In-Memory Architecture For Min/Max Search.	ICECS	2018	DBLP DOI BibTeX RDF
9	Saransh Gupta, Mohsen Imani, Tajana Rosing	FELIX: fast and energy-efficient logic in memory.	ICCAD	2018	DBLP DOI BibTeX RDF
9	Saeideh Shirinzadeh	Synthesis and optimization for logic-in-memory computing using memristive devices.		2018	RDF
9	Hao Cai, You Wang 0002, Lirida Alves de Barros Naviner, Weisheng Zhao	Robust Ultra-Low Power Non-Volatile Logic-in-Memory Circuits in FD-SOI Technology.	IEEE Trans. Circuits Syst. I Regul. Pap.	2017	DBLP DOI BibTeX RDF
9	Kai Yang 0028, Robert Karam, Swarup Bhunia	Interleaved logic-in-memory architecture for energy-efficient fine-grained data processing.	MWSCAS	2017	DBLP DOI BibTeX RDF
9	Saeideh Shirinzadeh, Mathias Soeken, Pierre-Emmanuel Gaillardon, Giovanni De Micheli, Rolf Drechsler	Endurance management for resistive Logic-In-Memory computing architectures.	DATE	2017	DBLP DOI BibTeX RDF
9	Sumit Dutta, Saima A. Siddiqui, Felix Buttner, Luqiao Liu, Caroline A. Ross, Marc A. Baldo	A logic-in-memory design with 3-terminal magnetic tunnel junction function evaluators for convolutional neural networks.	NANOARCH	2017	DBLP DOI BibTeX RDF
9	Javad Talafy, Hamid R. Zarandi	Soft error analysis of MTJ-based logic-in-memory full adder: Threats and solution.	IOLTS	2017	DBLP DOI BibTeX RDF
9	Pilin Junsangsri, Jie Han 0001, Fabrizio Lombardi	Logic-in-Memory With a Nonvolatile Programmable Metallization Cell.	IEEE Trans. Very Large Scale Integr. Syst.	2016	DBLP DOI BibTeX RDF
9	Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Anne Siemon, Eike Linn, Rainer Waser, Anupam Chattopadhyay, Giovanni De Micheli	The Programmable Logic-in-Memory (PLiM) computer.	DATE	2016	DBLP BibTeX RDF
9	Daisuke Suzuki, Takahiro Hanyu	A low-power MTJ-based nonvolatile FPGA using self-terminated logic-in-memory structure.	FPL	2016	DBLP DOI BibTeX RDF
9	Xunzhao Yin, Ahmedullah Aziz, Joseph Nahas, Suman Datta, Sumeet Kumar Gupta, Michael T. Niemier, Xiaobo Sharon Hu	Exploiting ferroelectric FETs for low-power non-volatile logic-in-memory circuits.	ICCAD	2016	DBLP DOI BibTeX RDF
9	Mathias Soeken, Saeideh Shirinzadeh, Pierre-Emmanuel Gaillardon, Luca Gaetano Amarù, Rolf Drechsler, Giovanni De Micheli	An MIG-based compiler for programmable logic-in-memory architectures.	DAC	2016	DBLP DOI BibTeX RDF
9	Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu	Nonvolatile Logic-in-Memory LSI Using Cycle-Based Power Gating and its Application to Motion-Vector Prediction.	IEEE J. Solid State Circuits	2015	DBLP DOI BibTeX RDF
9	Daisuke Suzuki, Takahiro Hanyu	Design of an MTJ-based nonvolatile lookup table circuit using an energy-efficient single-ended logic-in-memory structure.	MWSCAS	2015	DBLP DOI BibTeX RDF
9	Takahiro Hanyu, Daisuke Suzuki, Naoya Onizawa, Shoun Matsunaga, Masanori Natsui, Akira Mochizuki	Spintronics-based nonvolatile logic-in-memory architecture towards an ultra-low-power and highly reliable VLSI computing paradigm.	DATE	2015	DBLP BibTeX RDF
9	Daisuke Suzuki, Masanori Natsui, Akira Mochizuki, Sadahiko Miura, Hiroaki Honjo, Hideo Sato, Shunsuke Fukami, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu	Fabrication of a 3000-6-input-LUTs embedded and block-level power-gated nonvolatile FPGA chip using p-MTJ-based logic-in-memory structure.	VLSIC	2015	DBLP DOI BibTeX RDF
9	D. Pala, Giovanni Causapruno, Marco Vacca, Fabrizio Riente, Giovanna Turvani, Mariagrazia Graziano, Maurizio Zamboni	Logic-in-Memory architecture made real.	ISCAS	2015	DBLP DOI BibTeX RDF
9	Huseyin Ekin Sumbul, Kaushik Vaidyanathan, Qiuling Zhu, Franz Franchetti, Larry T. Pileggi	A synthesis methodology for application-specific logic-in-memory designs.	DAC	2015	DBLP DOI BibTeX RDF
9	Huseyin Ekin Sumbul	A Novel Design Methodology for Synthesizing Application-Specific Logic-in-Memory Blocks.		2015	DOI RDF
9	S. Ferch, Eike Linn, Rainer Waser, Stephan Menzel	Simulation and comparison of two sequential logic-in-memory approaches using a dynamic electrochemical metallization cell model.	Microelectron. J.	2014	DBLP DOI BibTeX RDF
9	Jayita Das, Syed M. Alam, Sanjukta Bhanja	STT-Based Non-Volatile Logic-in-Memory Framework.	Field-Coupled Nanocomputing	2014	DBLP DOI BibTeX RDF
9	Shintaro Harada, Xu Bai, Michitaka Kameyama, Yoshichika Fujioka	Design of a Logic-in-Memory Multiple-Valued Reconfigurable VLSI Based on a Bit-Serial Packet Data Transfer Scheme.	ISMVL	2014	DBLP DOI BibTeX RDF
9	Fazle Sadi, Berkin Akin, Doru-Thom Popovici, James C. Hoe, Larry T. Pileggi, Franz Franchetti	Algorithm/hardware co-optimized SAR image reconstruction with 3D-stacked logic in memory.	HPEC	2014	DBLP DOI BibTeX RDF
9	Shota Ishihara, Noriaki Idobata, Masanori Hariyama, Michitaka Kameyama	Flexible Ferroelectric-Capacitor Element for Low Power and Compact Logic-in-Memory Architectures.	J. Multiple Valued Log. Soft Comput.	2013	DBLP BibTeX RDF
9	Qiuling Zhu, Berkin Akin, Huseyin Ekin Sumbul, Fazle Sadi, James C. Hoe, Larry T. Pileggi, Franz Franchetti	A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing.	3DIC	2013	DBLP DOI BibTeX RDF
9	Masanori Natsui, Daisuke Suzuki, Noboru Sakimura, Ryusuke Nebashi, Yukihide Tsuji, Ayuka Morioka, Tadahiko Sugibayashi, Sadahiko Miura, Hiroaki Honjo, Keizo Kinoshita, Shoji Ikeda, Tetsuo Endoh, Hideo Ohno, Takahiro Hanyu	Nonvolatile logic-in-memory array processor in 90nm MTJ/MOS achieving 75% leakage reduction using cycle-based power gating.	ISSCC	2013	DBLP DOI BibTeX RDF
9	Takahiro Hanyu	Challenge of MTJ/MOS-hybrid logic-in-memory architecture for nonvolatile VLSI processor.	ISCAS	2013	DBLP DOI BibTeX RDF
9	Qiuling Zhu, Tobias Graf, Huseyin Ekin Sumbul, Larry T. Pileggi, Franz Franchetti	Accelerating sparse matrix-matrix multiplication with 3D-stacked logic-in-memory hardware.	HPEC	2013	DBLP DOI BibTeX RDF
9	Qiuling Zhu, Christian R. Berger, Eric L. Turner, Larry T. Pileggi, Franz Franchetti	Polar format synthetic aperture radar in energy efficient application-specific logic-in-memory.	ICASSP	2012	DBLP DOI BibTeX RDF