Search results for "registers"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
81	Jun Yan 0008, Wei Zhang 0002	Exploiting virtual registers to reduce pressure on real registers.	ACM Trans. Archit. Code Optim.	2008	DBLP DOI BibTeX RDF	short-lived variables, virtual register, register allocation, Register file, data forwarding
70	Hagit Attiya, Faith Ellen Fich, Yaniv Kaplan	Lower bounds for adaptive collect and related objects.	PODC	2004	DBLP DOI BibTeX RDF	exclusive-write registers, sensitive objects, solo termination, weak test&set, adaptivity, contention, collect
68	Marcos Kawazoe Aguilera, Burkhard Englert, Eli Gafni	On using network attached disks as shared memory.	PODC	2003	DBLP DOI BibTeX RDF
68	Soma Chaudhuri, Jennifer L. Welch	Bounds on the Costs of Register Implementations.	WDAG	1990	DBLP DOI BibTeX RDF
66	Xiaotong Zhuang, Tao Zhang 0037, Santosh Pande	Hardware-managed register allocation for embedded processors.	LCTES	2004	DBLP DOI BibTeX RDF	architected registers, physical registers, embedded systems, power consumption, register allocation
65	Xiaotong Zhuang, Santosh Pande	Allocating architected registers through differential encoding.	ACM Trans. Program. Lang. Syst.	2007	DBLP DOI BibTeX RDF	architected register, differential encoding, Register allocation
62	Panagiota Fatourou, Faith E. Fich, Eric Ruppert	A tight time lower bound for space-optimal implementations of multi-writer snapshots.	STOC	2003	DBLP DOI BibTeX RDF	shared-memory distributed computing, lower bounds, snapshot, space-optimal
62	Yehuda Afek, Pazi Boxer, Dan Touitou	Bounds on the shared memory requirements for long-lived adaptive objects (extended abstract).	PODC	2000	DBLP DOI BibTeX RDF
62	Thomas Scholz, Michael Schäfers 0003	An improved dynamic register array concept for high-performance RISC processors.	HICSS (1)	1995	DBLP DOI BibTeX RDF	dynamic register array concept, high-performance RISC processors, processor registers, Multi Windows, Threaded Windows, dynamic register array, dynamic register allocation, general purpose registers, fast context switches, short interrupt latency, exception routines, real time systems, data structures, data structures, interrupts, storage allocation, external memory, registers, reduced instruction set computing
59	Jun Yan 0008, Wei Zhang 0002	Virtual Registers: Reducing Register Pressure Without Enlarging the Register File.	HiPEAC	2007	DBLP DOI BibTeX RDF
59	Kwanghyun Kim, Dong Sam Ha, Joseph G. Tront	On using signature registers as pseudorandom pattern generators in built-in self-testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
59	Eric Schenk	Faster Approximate Agreement with Multi-Writer Registers.	FOCS	1995	DBLP DOI BibTeX RDF	multi-writer registers, wait-free approximate agreement problem, asynchronous shared memory, single-bit multi-writer multi-reader registers, wait-free single-writer multi-reader, wait-free multi-writer multi-reader, computational complexity, complexity, distributed algorithms, lower bounds, shared memory systems, upper bounds, shared registers
55	Hans-Georg Martin	Retiming for Circuits with Enable Registers.	EUROMICRO	1996	DBLP DOI BibTeX RDF	enable registers, circuit retiming, combinational paths, D-Flipflops, retiming algorithm, sequential elements, high level synthesis, high level synthesis, digital circuits
54	Andrzej Hlawiczka, Michal Kopec	Design and testing of fast and cost effective serial seeding TPGs based on one-dimensional linear hybrid cellular automata.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	serial seeding, linear hybrid cellular automata, n-cell CA register, p CdSR registers, cellular automata quasi shift register, PCASR, n-bit input sequence, logic testing, cellular automata, integrated circuit testing, automatic test pattern generation, application specific integrated circuits, polynomials, polynomial, logic CAD, cost, TPG, flip-flops, flip-flops, shift registers, pattern generators, integrated circuit economics
54	Albrecht P. Stroele	Signature analysis and aliasing for sequential circuits.	VTS	1995	DBLP DOI BibTeX RDF	built-in self-test techniques, test registers, subcircuits, irreducible characteristic polynomial, limiting value, fault diagnosis, logic testing, built-in self test, integrated circuit testing, sequential circuits, sequential circuits, aliasing, signature analysis, shift registers, test lengths
53	Soma Chaudhuri, Martha J. Kosa, Jennifer L. Welch	Upper and lower bounds for one-write multivalued regular registers.	SPDP	1991	DBLP DOI BibTeX RDF
53	John A. Swensen, Yale N. Patt	Hierarchical registers for scientific computers.	ICS	1988	DBLP DOI BibTeX RDF	CRAY-1
52	Faith Ellen, Panagiota Fatourou, Eric Ruppert	Time lower bounds for implementations of multi-writer snapshots.	J. ACM	2007	DBLP DOI BibTeX RDF	Distributed computing, lower bound, shared memory, wait-free, snapshot, registers
50	Raid Ayoub, Alex Orailoglu	Power efficient register file update approach for embedded processors.	ICCD	2007	DBLP DOI BibTeX RDF
50	Xiaotong Zhuang, Santosh Pande	Differential register allocation.	PLDI	2005	DBLP DOI BibTeX RDF	architected register, differential dncoding, register allocation
50	Liem Tran, Nicholas Nelson 0001, Fung Ngai, Steve Dropsho, Michael C. Huang 0001	Dynamically reducing pressure on the physical register file through simple register sharing.	ISPASS	2004	DBLP DOI BibTeX RDF
50	Dennis K. Y. Tong, Evangeline F. Y. Young	Performance-driven register insertion in placement.	ISPD	2004	DBLP DOI BibTeX RDF	post-retiming, register insertion, placement
50	Xiaotong Zhuang, Santosh Pande	Balancing register allocation across threads for a multithreaded network processor.	PLDI	2004	DBLP DOI BibTeX RDF	register allocation, network processor, multithreaded processor
50	Ishwar Parulkar, Sandeep K. Gupta 0001, Melvin A. Breuer	Allocation Techniques for Reducing BIST Area Overhead of Data Paths.	J. Electron. Test.	1998	DBLP DOI BibTeX RDF
48	Kaisheng Wang, Ted Zhihong Yu, Edwin Hsing-Mean Sha	RCRS: A Framework for Loop Scheduling with Limited Number of Registers.	Great Lakes Symposium on VLSI	1998	DBLP DOI BibTeX RDF	retiming, rotation, data-flow graphs, Loop scheduling, registers
47	Yasser Sedaghat, Seyed Ghassem Miremadi	Investigation and Reduction of Fault Sensitivity in the FlexRay Communication Controller Registers.	SAFECOMP	2008	DBLP DOI BibTeX RDF	Flex- Ray protocol, Fault injection, Distributed embedded systems, Safety-critical applications
47	David W. Oehmke, Nathan L. Binkert, Trevor N. Mudge, Steven K. Reinhardt	How to Fake 1000 Registers.	MICRO	2005	DBLP DOI BibTeX RDF
47	Teresa Monreal, Víctor Viñals, José González 0002, Antonio González 0001, Mateo Valero	Late Allocation and Early Release of Physical Registers.	IEEE Trans. Computers	2004	DBLP DOI BibTeX RDF
47	Rajiv A. Ravindran, Robert M. Senger, Eric D. Marsman, Ganesh S. Dasika, Matthew R. Guthaus, Scott A. Mahlke, Richard B. Brown	Increasing the number of effective registers in a low-power processor using a windowed register file.	CASES	2003	DBLP DOI BibTeX RDF	window assignment, low-power, graph partitioning, embedded processor, instruction encoding, register window
47	Agnes Hui Chan, Mark Goresky, Andrew Klapper	On the Linear Complexity of Feedback Registers (Extended Abstract).	EUROCRYPT	1989	DBLP DOI BibTeX RDF
45	Damien Imbs, Michel Raynal	Help When Needed, But No More: Efficient Read/Write Partial Snapshot.	DISC	2009	DBLP DOI BibTeX RDF	LL/SC atomic registers, Partial snapshot, Read/Write atomic register, Concurrency, Locality, Efficiency, Atomicity, Adaptive algorithm, Asynchrony, Process crash, Linearizability, Wait-free algorithm, Asynchronous shared memory system
43	Fang Lu, Lei Wang 0004, Xiaobing Feng 0002, Zhiyuan Li 0001, Zhaoqing Zhang	Exploiting idle register classes for fast spill destination.	ICS	2008	DBLP DOI BibTeX RDF	spilling cost, data transfer
43	Yoonseo Choi, Hwansoo Han	Optimal register reassignment for register stack overflow minimization.	ACM Trans. Archit. Code Optim.	2006	DBLP DOI BibTeX RDF	register stack, sequence graph, register allocation, Register assignment
43	Noureddine Chabini, El Mostapha Aboulhamid, Ismaïl Chabini, Yvon Savaria	Scheduling and optimal register placement for synchronous circuits derived using software pipelining techniques.	ACM Trans. Design Autom. Electr. Syst.	2005	DBLP DOI BibTeX RDF	multiphase, sequential circuit, software pipelining, clock, Retiming
43	Sharad Malik, Ellen M. Sentovich, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli	Retiming and resynthesis: optimizing sequential networks with combinational techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
42	Hyunyoung Lee, Jennifer L. Welch	Randomized registers and iterative algorithms.	Distributed Comput.	2005	DBLP DOI BibTeX RDF	probabilistic quorums, randomization, distributed shared memory, iterative algorithms, registers
42	Andrew Klapper	On the Existence of Secure Feedback Registers (Extended Abstract).	EUROCRYPT	1996	DBLP DOI BibTeX RDF	nonlinear feedback registers, security, cryptography, stream ciphers, Binary sequences
42	Robert Yung, Neil C. Wilhelm	Caching processor general registers.	ICCD	1995	DBLP DOI BibTeX RDF	caching processor general registers, processor cycle time requirements, small register cache, register caching, windowed-register architectures, parallel architectures, performance model, memory architecture, cache storage, register file
41	Hiroyuki Michinishi, Tokumi Yokohira, Takuji Okamoto, Tomoo Inoue, Hideo Fujiwara	Testing for the programming circuit of LUT-based FPGAs.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	programming circuit, control circuit, configuration memory cell array, FPGA, fault model, SRAM, shift registers, shift registers, look-up table
41	W. Amendola Jr., Hosahalli R. Srinivas, Keshab K. Parhi	A 16-bit x 16-bit 1.2 μ CMOS multiplier with low latency vector merging.	VLSI Design	1995	DBLP DOI BibTeX RDF	CMOS multiplier, low latency vector merging, bit-level pipelined architecture, two's-complement binary array multiplier, multiplier architecture, signed-digit radix 2 adders, carry free adders, fast conversion scheme, pipelining registers, half adders, positive edge triggered registers, single phase clocking scheme, 16 bit, 50 MHz, 3 V, VLSI, parallel architectures, multiplication, VLSI architecture, CMOS logic circuits, multiplying circuits, data conversion, pipeline arithmetic, 1.2 micron
40	Weixiang Shen, Yici Cai, Xianlong Hong, Jiang Hu	Activity-Aware Registers Placement for Low Power Gated Clock Tree Construction.	ISVLSI	2007	DBLP DOI BibTeX RDF
40	Rachid Guerraoui, Michel Raynal	From Unreliable Objects to Reliable Objects: The Case of Atomic Registers and Consensus.	PaCT	2007	DBLP DOI BibTeX RDF
40	Ryan Collins, Fernando Alegre, Xiaotong Zhuang, Santosh Pande	Compiler assisted dynamic management of registers for network processors.	IPDPS	2006	DBLP DOI BibTeX RDF
40	Sebastian Siegel, Renate Merker	Minimum Cost for Channels and Registers in Processor Arrays by Avoiding Redundancy.	ASAP	2006	DBLP DOI BibTeX RDF
40	Andrew Klapper, Jinzhong Xu	Register Synthesis for Algebraic Feedback Shift Registers Based on Non-Primes.	Des. Codes Cryptogr.	2004	DBLP DOI BibTeX RDF	register synthesis, N-adic numbers, stream cipher, pseudorandom generator, feedback shift register
40	Marcos Kawazoe Aguilera, Burkhard Englert, Eli Gafni	Uniform Solvability with a Finite Number of MWMR Registers.	DISC	2003	DBLP DOI BibTeX RDF
40	Wonjong Kim, Seungchul Kim, Hanjin Cho, Kwang-youb Lee	A fast-serial finite field multiplier without increasing the number of registers.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
40	Soma Chaudhuri, Martha J. Kosa, Jennifer L. Welch	One-write algorithms for multivalued regular and atomic registers.	Acta Informatica	2000	DBLP DOI BibTeX RDF
40	Hyunyoung Lee, Jennifer L. Welch	Specification, implementation and application of randomized regular registers (brief announcement).	PODC	2000	DBLP DOI BibTeX RDF
40	Hiroshi Nakamura, Taisuke Boku, Hideo Wada, Hiromitsu Imori, Ikuo Nakata, Yasuhiro Inagami, Kisaburo Nakazawa, Yoshiyuki Yamashita	A Scalar Architecture for Pseudo Vector Processing Based on Slide-Windowed Registers.	International Conference on Supercomputing	1993	DBLP DOI BibTeX RDF
40	Chi-Hung Chi, Henry G. Dietz	Unified Management of Registers and Cache Using Liveness and Cache Bypass.	PLDI	1989	DBLP DOI BibTeX RDF
40	Frederic J. Mowle	An Algorithm for Generating Stable Feedback Shift Registers of Order n.	J. ACM	1967	DBLP DOI BibTeX RDF
39	Andrea Masini, Luca Viganò 0001, Margherita Zorzi	A Qualitative Modal Representation of Quantum Register Transformations.	ISMVL	2008	DBLP DOI BibTeX RDF	quantum registers, modal logic, quantum logic
39	Ali Kanso	More Generalized Clock-Controlled Alternating Step Generator.	ACNS	2004	DBLP DOI BibTeX RDF	Clock-Controlled Registers, Alternating Step Generator and Clock-Controlled Alernating Step Generator, Stream Ciphers
39	Jovan Dj. Golic, Renato Menicocci	Edit Distance Correlation Attack on the Alternating Step Generator.	CRYPTO	1997	DBLP DOI BibTeX RDF	clock-controlled shift registers, alternating step generator, cryptanalysis, Stream ciphers, edit distance, correlation attacks
39	Andrew Klapper, Mark Goresky	Large Periods Nearly de Bruijn FCSR Sequences.	EUROCRYPT	1995	DBLP DOI BibTeX RDF	deBruijn property, Binary sequences, feedback with carry shift registers, 2-adic numbers
37	Dorit Nuzman, Mircea Namolaru, Ayal Zaks, Jeff H. Derby	Compiling for an indirect vector register architecture.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	compiler controlled cache, rotating register file, vectorization, data reuse, subword parallelism, viterbi, simd
37	Marcos Kawazoe Aguilera, Svend Frølund, Vassos Hadzilacos, Stephanie Lorraine Horn, Sam Toueg	Abortable and query-abortable objects and their efficient implementation.	PODC	2007	DBLP DOI BibTeX RDF	abortable types, non-triviality, universal constructions, shared memory, memory contention, obstruction-freedom
37	Ittai Abraham, Gregory V. Chockler, Idit Keidar, Dahlia Malkhi	Byzantine disk paxos: optimal resilience with byzantine shared memory.	Distributed Comput.	2006	DBLP DOI BibTeX RDF	T-tolerant object implementations, Lower bounds, Consensus, Byzantine failures, Wait freedom, Shared-memory emulations
37	Oguz Ergin, Deniz Balkan, Dmitry Ponomarev 0001, Kanad Ghose	Early Register Deallocation Mechanisms Using Checkpointed Register Files.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	register file optimization, Superscalar processors, precise interrupts
37	Jack Liu, Youfeng Wu	Performance Characterization of the 64-bit x86 Architecture from Compiler Optimizations' Perspective.	CC	2006	DBLP DOI BibTeX RDF
37	Gokhan Memik, Mahmut T. Kandemir, Ozcan Ozturk 0001	Increasing Register File Immunity to Transient Errors.	DATE	2005	DBLP DOI BibTeX RDF
37	Liu Yang, Sun Chan, Guang R. Gao, Roy Ju, Guei-Yuan Lueh, Zhaoqing Zhang	Inter-procedural stacked register allocation for itanium® like architecture.	ICS	2003	DBLP DOI BibTeX RDF	hot region, inter-procedural stacked register allocation, quota assignment, register allocation, hotspot
37	Shanq-Jang Ruan, Edwin Naroska, Chia-Lin Ho, Feipei Lai	Power Analysis of Bipartition and Dual-Encoding Architecture for Pipelined Circuits.	ICCD	2002	DBLP DOI BibTeX RDF
37	Alex Orailoglu	Microarchitectural synthesis for rapid BIST testing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
37	Neng-Fa Zhou	Parameter Passing and Control Stack Management in Prolog Implementation Revisited.	ACM Trans. Program. Lang. Syst.	1996	DBLP DOI BibTeX RDF	prolog, abstract machine
37	Miquel Huguet, Tomás Lang	Architectural Support for Reduced Register Saving / Restoring in Single-Window Register Files.	ACM Trans. Comput. Syst.	1991	DBLP DOI BibTeX RDF
37	David W. Wall	Global register allocation at link time.	SIGPLAN Symposium on Compiler Construction	1986	DBLP DOI BibTeX RDF
37	David W. Wall	Global register allocation at link time (with retrospective)	Best of PLDI	1986	DBLP DOI BibTeX RDF
36	James Aspnes, Hagit Attiya, Keren Censor	Max registers, counters, and monotone circuits.	PODC	2009	DBLP DOI BibTeX RDF	max registers, distributed computing, shared memory, counters, monotone circuits
36	Andrew Robinson, Jim D. Garside	Sensitive registers: a technique for reducing the fetch bandwidth in low-power microprocessors.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	processors, memory bandwidth, power efficiency, registers
36	Chryssis Georgiou, Nicolas C. Nicolaou, Alexander A. Shvartsman	Fault-tolerant semifast implementations of atomic read/write registers.	SPAA	2006	DBLP DOI BibTeX RDF	communication rounds, read/write registers, fault-tolerance, distributed algorithms, atomicity
36	Chik How Tan, Xun Yi, Chee Kheong Siew	A CCA2 Secure Key Encapsulation Scheme Based on 3rd Order Shift Registers.	ACISP	2003	DBLP DOI BibTeX RDF	adaptive chosen-ciphertext attack, Public key cryptosystem, shift registers
36	Li-Ren Huang, Jing-Yang Jou, Sy-Yen Kuo, Wen-Bin Liao	Easily Testable Data Path Allocation Using Input/Output Registers.	Asian Test Symposium	1996	DBLP DOI BibTeX RDF	testable data path allocation, behavioral synthesis systems, input/output registers, interconnection allocation, module allocation, higher fault coverage, lower hardware overhead, improved testability, VLSI synthesis, optimization, algorithms, benchmarks, ATPG, DFT, register allocation, circuit optimisation, RTL design
35	Kun Zhang 0006, Tao Zhang 0037, Santosh Pande	Binary translation to improve energy efficiency through post-pass register re-allocation.	EMSOFT	2004	DBLP DOI BibTeX RDF	cache power consumption, dead registers, register re-allocation, unused registers
35	Wei-Lun Wang, Kuen-Jong Lee	Accelerated test pattern generators for mixed-mode BIST environments.	Asian Test Symposium	2000	DBLP DOI BibTeX RDF	accelerated test pattern generators, mixed-mode BIST, pseudorandom patterns, deterministic patterns, scan-based built-in self-test, multiple sub-chains, multiple sequence generator, fault diagnosis, logic testing, built-in self test, integrated circuit testing, automatic test pattern generation, fault coverage, linear feedback shift registers, cost, test pattern generator, shift registers, test application time, scan chain, mixed analogue-digital integrated circuits, clock cycle, integrated circuit economics
35	Manoj Franklin	Fast computation of C-MISR signatures.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	C-MISR signatures, built-in self-test applications, good circuit signature, faulty circuit signatures, cellular automata-based multi-input signature registers, equivalent single input circuit, VLSI, logic testing, built-in self test, cellular automata, integrated circuit testing, sequential circuits, shift registers, test responses, signature analyzers, equivalent circuits
35	Sukumar Nandi, Parimal Pal Chaudhuri	Theory and applications of cellular automata for synthesis of easily testable combinational logic.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	testable combinational logic, combinational logic blocks, test machine, data path synthesis phase, autonomous mode, aliasing error probability, associated lines, test application overheads, test parallelism, simultaneous testing, multiple combinational modules, graph theory, fault diagnosis, logic testing, high level synthesis, test generation, cellular automata, cellular automata, design for testability, combinational circuits, logic CAD, stuck-at faults, shift registers, cost effectiveness, registers, test vectors, test responses, state transition graph
35	Jacob Savir	On shrinking wide compressors.	VTS	1995	DBLP DOI BibTeX RDF	wiring overhead, detection probability loss, test length penalty, fault coverage degradation, fault diagnosis, logic testing, built-in self test, built-in self-test, integrated circuit testing, shift registers, pseudo-random test, MISRs, parity, multiple-input signature registers
35	Manoj Franklin, Kewal K. Saluja, Kyuchull Kim	Fast computation of MISR signatures.	VLSI Design	1995	DBLP DOI BibTeX RDF	MISR signatures, fast computation, test response compression, multi-input signature registers, equivalent single input circuit, logic testing, design for testability, logic design, table lookup, table lookups, shift registers, binary sequences, speedup technique, signature analyzers
34	David F. Brailsford	Automated re-typesetting, indexing and contentenhancement for scanned marriage registers.	ACM Symposium on Document Engineering	2009	DBLP DOI BibTeX RDF	GEDCOM, hyper-linking, re-typesetting, troff, indexing, OCR, genealogy
34	Herbjørn Andresen	The Policy Debate on Pseudonymous Health Registers in Norway.	BIOSTEC (Selected Papers)	2008	DBLP DOI BibTeX RDF	Public Health Policy, Privacy Regulation, Confidentiality, Data Security, Pseudonymity
34	Timothy Furtak, José Nelson Amaral, Robert Niewiadomski	Using SIMD registers and instructions to enable instruction-level parallelism in sorting algorithms.	SPAA	2007	DBLP DOI BibTeX RDF	sorting, instruction-level parallelism, SIMD, vectorization, sorting networks, quicksort
34	Lisa Higham, Colette Johnen	Relationships between communication models in networks using atomic registers.	IPDPS	2006	DBLP DOI BibTeX RDF
34	Arvind Krishnaswamy, Rajiv Gupta 0001	Efficient Use of Invisible Registers in Thumb Code.	MICRO	2005	DBLP DOI BibTeX RDF
34	Andrew Klapper	Algebraic Feedback Shift Registers Based on Function Fields.	SETA	2004	DBLP DOI BibTeX RDF
34	Van-Ly Le, Werner Schindler	How to Embed Short Cycles into Large Nonlinear Feedback-Shift Registers.	SCN	2004	DBLP DOI BibTeX RDF	short cycles, systems of algebraic equations, low-cost group identification, Nonlinear feedback shift register, invariant theory
34	Andrea G. M. Cilio, Henk Corporaal	Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation.	CC	2002	DBLP DOI BibTeX RDF
34	Paul M. B. Vitányi	Simple Wait-Free Multireader Registers.	DISC	2002	DBLP DOI BibTeX RDF
34	Frank Mayer, Albrecht P. Stroele	A Versatile BIST Technique Combining Test Registers and Accumulators.	VLSI Design	2000	DBLP DOI BibTeX RDF	test register, built-in self-test, register-transfer level, accumulator
34	Teresa Monreal, Antonio González 0001, Mateo Valero, José González 0002, Víctor Viñals	Delaying Physical Register Allocation through Virtual-Physical Registers.	MICRO	1999	DBLP DOI BibTeX RDF
34	Josep Llosa, Mateo Valero, José A. B. Fortes, Eduard Ayguadé	Using Sacks to Organize Registers in VLIW Machines.	CONPAR	1994	DBLP DOI BibTeX RDF
34	Mark Goresky, Andrew Klapper	Feedback Registers Based on Ramified Extensions of the 2-Adic Numbers (Extended Abstract).	EUROCRYPT	1994	DBLP DOI BibTeX RDF
34	André Ivanov, Vinod K. Agarwal	An analysis of the probabilistic behavior of linear feedback signature registers.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
33	S. Anand, Gurumurthi V. Ramanan	Periodicity, complementarity and complexity of 2-adic FCSR combiner generators.	AsiaCCS	2006	DBLP DOI BibTeX RDF	?-sequences, 2-adic complexity, stream ciphers, combiners, linear complexity, pseudorandom number generators, feedback shift registers, FCSR
33	Masahiro Sowa, Ben A. Abderazek, Tsutomu Yoshinaga	Parallel Queue Processor Architecture Based on Produced Order Computation Model.	J. Supercomput.	2005	DBLP DOI BibTeX RDF	produced order, queue processor, circular queue-registers, design, high performance
33	Yang Xiao 0001, Yi Pan 0001, Jie Li 0002	Design and Analysis of Location Management for 3G Cellular Networks.	IEEE Trans. Parallel Distributed Syst.	2004	DBLP DOI BibTeX RDF	3G cellular networks, gateway location registers, Location management, personal communications services
33	Jovan Dj. Golic, Renato Menicocci	Edit Probability Correlation Attacks on Stop/ Go Clocked Keystream Generators.	J. Cryptol.	2003	DBLP DOI BibTeX RDF	Stop/go clocked shift registers, Edit probability, Stream ciphers, Correlation attack
33	François Arnault, Thierry P. Berger, Abdelkader Necer	A New Class of Stream Ciphers Combining LFSR and FCSR Architectures.	INDOCRYPT	2002	DBLP DOI BibTeX RDF	2-adic expansion, Self-synchronizing stream ciphers, Pseudorandom generators, Feedback shift registers
33	Kentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada	A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing.	ICCD	1999	DBLP DOI BibTeX RDF	scientific processing, slide-windowed registers, large number of FPRs, SR8000, supercomputer, software prefetch