Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
78 | Lin Yuan, Pushkin R. Pari, Gang Qu 0001 |
Soft IP Protection: Watermarking HDL Codes. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Information Hiding ![In: Information Hiding, 6th International Workshop, IH 2004, Toronto, Canada, May 23-25, 2004, Revised Selected Papers, pp. 224-238, 2004, Springer, 3-540-24207-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
77 | Peter A. Jamieson, Kenneth B. Kent |
Odin II: an open-source verilog HDL synthesis tool for FPGA cad flows (abstract only). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 288, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
fpga, verilog hdl |
75 | Arash Saifhashemi, Hossein Pedram |
Verilog HDL, powered by PLI: a suitable framework for describing and modeling asynchronous circuits at all levels of abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 330-333, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
CHP, PLI, CSP, asynchronous circuits, channel, verilog |
68 | Shengchao Qin, Jifeng He 0001, Zongyan Qiu, Naixiao Zhang |
Hardware/Software Partitioning in Verilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICFEM ![In: Formal Methods and Software Engineering, 4th International Conference on Formal Engineering Methods, ICFEM 2002 Shanghai, China, October 21-25, 2002, Proceedings, pp. 168-179, 2002, Springer, 3-540-00029-1. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
66 | Ivan Blunno, Luciano Lavagno |
Automated Synthesis of Micro-Pipelines from Behavioral Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2-6 April 2000, Eilat, Israel, pp. 84-92, 2000, IEEE Computer Society, 0-7695-0586-4. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
59 | Choudhury A. Rahman, Wael M. Badawy |
A quarter pel full search block motion estimation architecture for H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICME ![In: Proceedings of the 2005 IEEE International Conference on Multimedia and Expo, ICME 2005, July 6-9, 2005, Amsterdam, The Netherlands, pp. 414-417, 2005, IEEE Computer Society, 0-7803-9331-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
CIF frame sequence, quarter pel full search, block motion estimation architecture, H.264-AVC encoder, Xilinx Virtex2 FPGA, field programmable gate array, hardware description language, Verilog HDL |
49 | Raik Brinkmann, Rolf Drechsler |
RTL-Datapath Verification using Integer Linear Programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 741-746, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
49 | Richard Goering, Clifford E. Cummings, Steven E. Schulz, Simon Davidman, John Sanguinetti, Joachim Kunkel, Oz Levia |
The future of system design languages (panel session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 438-439, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
40 | Xiumin Wang, Yang Zhang, Qiang Ye, Shihua Yang |
A New Algorithm for Designing Square Root Calculators Based on FPGA with Pipeline Technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HIS (1) ![In: 9th International Conference on Hybrid Intelligent Systems (HIS 2009), August 12-14, 2009, Shenyang, China, pp. 99-102, 2009, IEEE Computer Society, 978-0-7695-3745-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, algorithm, pipeline, square root, Verilog HDL |
40 | Yang Zhang, Xiumin Wang, Yuduo Wang |
A New Design of HDB3 Encoder and Decoder Based on FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HIS (1) ![In: 9th International Conference on Hybrid Intelligent Systems (HIS 2009), August 12-14, 2009, Shenyang, China, pp. 210-213, 2009, IEEE Computer Society, 978-0-7695-3745-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
HDB3, FPGA, encoder, decoder, Verilog HDL |
40 | Takao Onoye, Yukihiro Nakamura, Atsuhito Shigiya, Keishi Chikamura, Kosuke Tsujino, Tomonori Izumi, Hirofumi Yamamoto |
System-Level Design of IEEE1394 Bus Segment Bridge. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISSS ![In: Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), October 2-4, 2002, Kyoto, Japan, pp. 74-79, 2002, ACM / IEEE Computer Society, 1-58113-576-9. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
HW/SW co-simulation, IEEE1394, PLI, bus bridge, C/C++, verilog-HDL |
40 | Marcel Jacomet, Roger Wälti, Lukas Winzenried, Jaime Perez, Martin Gysel |
ProTest: A Low Cost Rapid Prototyping Test System for ASICs and FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 6th Asian Test Symposium (ATS '97), 17-18 November 1997, Akita, Japan, pp. 138-142, 1997, IEEE Computer Society, 0-8186-8209-4. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
test bench, test machine, CAT-tool, ProTest, FPGA, VHDL, rapid prototyping, Verilog-HDL |
39 | Siva Kumar Sastry Hari, Vishnu Vardhan Reddy Konda, V. Kamakoti 0001, Vivekananda M. Vedula, K. S. Maneperambil |
Automatic Constraint Based Test Generation for Behavioral HDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(4), pp. 408-421, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
39 | Sunil R. Das, Chuan Jin, Liwu Jin, Mansour H. Assaf, Emil M. Petriu, Mehmet Sahinoglu |
Altera Max Plus II Development Environment in Fault Simulation and Test Implementation of Embedded Cores-Based Sequential Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWDC ![In: Distributed Computing - IWDC 2004, 6th International Workshop, Kolkata, India, December 27-30, 2004, Proceedings, pp. 353-360, 2004, Springer, 3-540-24076-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
39 | John A. Nestor |
Teaching Computer Organization with HDLs: An Incremental Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: 2005 International Conference on Microelectronics Systems Education, MSE 2005, Anaheim, CA, USA, June 12-13, 2005, pp. 77-78, 2005, IEEE Computer Society, 0-7695-2374-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
39 | Hamid R. Zarandi, Seyed Ghassem Miremadi, Ali Reza Ejlali |
Fault Injection into Verilog Models for Dependability Evaluation of Digital Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPDC ![In: 2nd International Symposium on Parallel and Distributed Computing (ISPDC 2003), 13-14 October 2003, Ljubljana, Slovenia, pp. 281-, 2003, IEEE Computer Society, 0-7695-2069-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
37 | Anik Mallik, Sanjoy Kundu, Md. Ashikur Rahman |
An FPGA-Based Semi-Automated Traffic Control System Using Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2303.04716, 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
37 | Lekshmi S. Ajay, Sreenidhi Prabha Rajeev |
Comparative Analysis of Data Compression using Canonical Huffman and Golomb Rice Encoding in Verilog HDL and Implementation in FPGA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCCNT ![In: 14th International Conference on Computing Communication and Networking Technologies, ICCCNT 2023, Delhi, India, July 6-8, 2023, pp. 1-7, 2023, IEEE, 979-8-3503-3509-5. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
37 | Pawel Szczepankowski, Wojciech Sleszynski, Tomasz Bajdecki |
A Direct Modulation for Matrix Converters Based on the One-Cycle Atomic Operation Developed in Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Ind. Electron. ![In: IEEE Trans. Ind. Electron. 69(4), pp. 3303-3312, 2022. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
37 | K. N. Raja Praveen, Gadug Sudhamsu |
Using AIG in Verilog HDL, Autonomous Testing in a Family of Wien Bridge Cross Transducers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IC3I ![In: 5th International Conference on Contemporary Computing and Informatics, IC3I 2022, Uttar Pradesh, India, December 14-16, 2022, pp. 712-715, 2022, IEEE, 979-8-3503-9826-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
37 | K. N. Raja Praveen, Gadug Sudhamsu |
Using AIG in Verilog HDL, Autonomous Testing in a Family of Wien Bridge Cross Transducers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IC3I ![In: 5th International Conference on Contemporary Computing and Informatics, IC3I 2022, Uttar Pradesh, India, December 14-16, 2022, pp. 712-715, 2022, IEEE, 979-8-3503-9826-7. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
37 | Hye-Hyun Lee, Yeon-Seob Song, Kang-Yoon Lee |
Modeling of nano-scale PLL using Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICTC ![In: 13th International Conference on Information and Communication Technology Convergence, ICTC 2022, Jeju Island, Korea, Republic of, October 19-21, 2022, pp. 2101-2104, 2022, IEEE, 978-1-6654-9939-2. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
37 | Jin-Yang Lai, Chiung-An Chen, Shih-Lun Chen, Chun-Yu Su |
Implement 32-bit RISC-V Architecture Processor using Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPACS ![In: International Symposium on Intelligent Signal Processing and Communication Systems, ISPACS 2021, Hualien City, Taiwan, November 16-19, 2021, pp. 1-2, 2021, IEEE, 978-1-6654-1951-2. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
37 | Peter Flake, Phil Moorby, Steve Golson, Arturo Salz, Simon J. Davidmann |
Verilog HDL and its ancestors and descendants. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Proc. ACM Program. Lang. ![In: Proc. ACM Program. Lang. 4(HOPL), pp. 87:1-87:90, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
37 | Junya Miura, Hiromu Miyazaki, Kenji Kise |
A portable and Linux capable RISC-V computer system in Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CoRR ![In: CoRR abs/2002.03576, 2020. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP BibTeX RDF |
|
37 | Guo-Ming Sung, Chun-Ting Lee, Chao-Rong Chen |
IoT-Based Home Care System with a FPGA Development Board by Using RS-485 Interface and Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC ![In: 2020 IEEE International Conference on Systems, Man, and Cybernetics, SMC 2020, Toronto, ON, Canada, October 11-14, 2020, pp. 3370-3374, 2020, IEEE, 978-1-7281-8526-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
37 | Abdul Rafay Khatri, Ali Hayek, Josef Börcsök |
Validation of the Proposed Fault Injection, Test and Hardness Analysis for Combinational Data-Flow Verilog HDL Designs Under the RASP-FIT Tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DASC/PiCom/DataCom/CyberSciTech ![In: 2018 IEEE 16th Intl Conf on Dependable, Autonomic and Secure Computing, 16th Intl Conf on Pervasive Intelligence and Computing, 4th Intl Conf on Big Data Intelligence and Computing and Cyber Science and Technology Congress, DASC/PiCom/DataCom/CyberSciTech 2018, Athens, Greece, August 12-15, 2018, pp. 544-551, 2018, IEEE Computer Society, 978-1-5386-7518-2. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
37 | Mo Qiu, Simin Yu, Yuqiong Wen, Jinhu Lü, Jianbin He, Zhuosheng Lin |
Design and FPGA Implementation of a Universal Chaotic Signal Generator Based on the Verilog HDL Fixed-Point Algorithm and State Machine Control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Bifurc. Chaos ![In: Int. J. Bifurc. Chaos 27(3), pp. 1750040:1-1750040:15, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
37 | Bei Cao, Tianliang Xu, Pengfei Wu |
RSA Encryption Algorithm Design and Verification Based on Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MLICOM (1) ![In: Machine Learning and Intelligent Communications - Second International Conference, MLICOM 2017, Weihai, China, August 5-6, 2017, Proceedings, Part I, pp. 555-563, 2017, Springer, 978-3-319-73563-4. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
37 | Ryohei Kobayashi, Tomohiro Misono, Kenji Kise |
A High-speed Verilog HDL Simulation Method using a Lightweight Translator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGARCH Comput. Archit. News ![In: SIGARCH Comput. Archit. News 44(4), pp. 26-31, 2016. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
37 | Zbigniew Jaworski |
Verilog HDL model based thermometer-to-binary encoder with bubble error correction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MIXDES ![In: 2016 MIXDES - 23rd International Conference Mixed Design of Integrated Circuits and Systems, Lodz, Poland, June 23-25, 2016, pp. 249-254, 2016, IEEE, 978-83-63578-09-1. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
37 | Shinya Takamaeda-Yamazaki |
Pyverilog: A Python-Based Hardware Design Processing Toolkit for Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Applied Reconfigurable Computing - 11th International Symposium, ARC 2015, Bochum, Germany, April 13-17, 2015, Proceedings, pp. 451-460, 2015, Springer, 978-3-319-16213-3. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
37 | Tze Sin Tan, Bakhtiar Affendi Rosdi |
Verilog HDL Simulator Technology: A Survey. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 30(3), pp. 255-269, 2014. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
37 | Tariq B. Ahmad, Maciej J. Ciesielski |
Parallel Multi-core Verilog HDL Simulation Using Domain Partitioning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: IEEE Computer Society Annual Symposium on VLSI, ISVLSI 2014, Tampa, FL, USA, July 9-11, 2014, pp. 619-624, 2014, IEEE Computer Society, 978-1-4799-3763-9. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
37 | Rosario M. Reas, Anastacia B. Alvarez, Joy Alinda P. Reyes |
Simulation of Standard Benchmarks in Hardware Implementations of L2 Cache Models in Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
UKSim ![In: Proceedings of the 12th UKSim, International Conference on Computer Modelling and Simulation, Cambridge, UK, 24-26 March 2010, pp. 153-158, 2010, IEEE Computer Society, 978-0-7695-4016-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
37 | Peter Jamieson, Kenneth B. Kent, Farnaz Gharibian, Lesley Shannon |
Odin II - An Open-Source Verilog HDL Synthesis Tool for CAD Research. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FCCM ![In: 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, FCCM 2010, Charlotte, North Carolina, USA, 2-4 May 2010, pp. 149-156, 2010, IEEE Computer Society, 978-0-7695-4056-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
37 | Adam Duley, Chris Spandikow, Miryung Kim |
A program differencing algorithm for verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASE ![In: ASE 2010, 25th IEEE/ACM International Conference on Automated Software Engineering, Antwerp, Belgium, September 20-24, 2010, pp. 477-486, 2010, ACM, 978-1-4503-0116-9. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
37 | Mohammad Shokrollah-Shirazi, Seyed Ghassem Miremadi |
FPGA-Based Fault Injection into Synthesizable Verilog HDL Models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SSIRI ![In: Second International Conference on Secure System Integration and Reliability Improvement, SSIRI 2008, July 14-17, 2008, Yokohama, Japan, pp. 143-149, 2008, IEEE Computer Society, 978-0-7695-3266-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
37 | Robert B. Reese, Mitchell A. Thornton |
Introduction to Logic Synthesis using Verilog HDL ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2006 |
DOI RDF |
|
37 | Mile K. Stojcev |
Digital Computer Arithmetic Datapath Design Using Verilog HDL, James E. Stine, Kluwer Academic Publishers, Boston, 2004, ISBN 1-4020-7710-6. Hardcover, pp 180, plus XI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Microelectron. Reliab. ![In: Microelectron. Reliab. 45(7-8), pp. 1272, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
37 | Jordan Dimitriov |
Developing semantics of Verilog HDL in formal compositional design of mixed hardware/software systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2002 |
RDF |
|
37 | Daniel C. Hyde |
Using verilog HDL to teach computer architecture concepts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WCAE@ISCA ![In: Proceedings of the 1998 workshop on Computer architecture education, WCAE@ISCA 1998, Barcelona, Spain, June 1998, pp. 10, 1998, ACM, 978-1-4503-4736-5. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
37 | Gordon G. Pace |
Hardware design based on Verilog HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1998 |
RDF |
|
37 | Ulrich Golze |
VLSI-Entwurf eines RISC-Prozessors - eine Einführung in das Design großer Chips und die Hardware-Beschreibungssprache VERILOG HDL. ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
1995 |
RDF |
|
37 | Michael J. C. Gordon |
The Semantic Challenge of Verilog HDL ![Search on Bibsonomy](Pics/bibsonomy.png) |
LICS ![In: Proceedings, 10th Annual IEEE Symposium on Logic in Computer Science, San Diego, California, USA, June 26-29, 1995, pp. 136-145, 1995, IEEE Computer Society, 0-8186-7050-9. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
|
37 | Felice Balarin, Gary York |
Verilog HDL Modeling Styles for Formal Verification. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CHDL ![In: Computer Hardware Description Languages and their Applications, Proceedings of the 11th IFIP WG10.2 International Conference on Computer Hardware Description Languages and their Applications - CHDL '93, sponsored by IFIP WG10.2 and in cooperation with IEEE COMPSOC, Ottawa, Ontario, Canada, 26-28 April, 1993, pp. 453-465, 1993, North-Holland, 0-444-81641-0. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP BibTeX RDF |
|
29 | Yan Lin Aung, Douglas L. Maskell, Timothy F. Oliver, Bertil Schmidt, William Bong |
C-Based Design Methodology for FPGA Implementation of ClustalW MSA. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRIB ![In: Pattern Recognition in Bioinformatics, Second IAPR International Workshop, PRIB 2007, Singapore, October 1-2, 2007, Proceedings, pp. 11-18, 2007, Springer, 978-3-540-75285-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
ClustalW, FPGA, multiple sequence alignment, sequence analysis |
29 | Vahid Lari, Mehdi Dehbashi, Seyed Ghassem Miremadi, Navid Farazmand |
Assessment of Message Missing Failures in FlexRay-Based Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PRDC ![In: 13th IEEE Pacific Rim International Symposium on Dependable Computing (PRDC 2007), 17-19 December, 2007, Melbourne, Victoria, Australia, pp. 191-194, 2007, IEEE Computer Society, 0-7695-3054-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Ryuichi Takahashi, Noriyoshi Yoshida |
Diagonal Examples for Design Space Exploration in an Educational Environment CITY-1. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MSE ![In: IEEE International Conference on Microelectronic Systems Education, MSE 1999, Arlington, Virginia, USA, July 19-21, 1999, pp. 71-73, 1999, IEEE Computer Society, 0-7695-0312-8. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
29 | Ilker Hamzaoglu, Ozgur Tasdizen, Esra Sahin |
An efficient H.264 intra frame coder system design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2007, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Atlanta, GA, USA, 15-17 October 2007, pp. 200-205, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Esra Sahin, Ilker Hamzaoglu |
Interactive presentation: An efficient hardware architecture for H.264 intra prediction algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 183-188, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Esra Sahin, Ilker Hamzaoglu |
An Efficient Intra Prediction Hardware Architecture for H.264 Video Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 448-454, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Serkan Oktem, Ilker Hamzaoglu |
An Efficient Hardware Architecture for Quarter-Pixel Accurate H.264 Motion Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSD ![In: Tenth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2007), 29-31 August 2007, Lübeck, Germany, pp. 444-447, 2007, IEEE Computer Society, 0-7695-2978-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Himanshu Arora, Nikolaus Klemmer, Thomas Jochum, Patrick D. Wolf |
Design Methodology and CAD Tools for Prototyping Delta-Sigma Fractional-N Frequency Synthesizers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE International Workshop on Rapid System Prototyping ![In: 18th IEEE International Workshop on Rapid System Prototyping (RSP 2007), 28-30 May 2007, Porto Alegre, RS, Brazil, pp. 150-156, 2007, IEEE Computer Society, 978-0-7695-2834-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
29 | Sinan Yalcin, Ilker Hamzaoglu |
A High Performance Hardware Architecture for Half-Pixel Accurate H.264 Motion Estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 63-67, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Mustafa Parlak, Ilker Hamzaoglu |
An Efficient Hardware Architecture for H.264 Adaptive Deblocking Filter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: First NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2006), 15-18 June 2006, Istanbul, Turkey, pp. 381-385, 2006, IEEE Computer Society, 0-7695-2614-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
29 | Ivan Blunno, Luciano Lavagno |
Designing an Asynchronous Microcontroller Using Pipefitter. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 20th International Conference on Computer Design (ICCD 2002), VLSI in Computers and Processors, 16-18 September 2002, Freiburg, Germany, Proceedings, pp. 488-493, 2002, IEEE Computer Society, 0-7695-1700-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
29 | Jordan Dimitrov |
Operational Semantics for Verilog. ![Search on Bibsonomy](Pics/bibsonomy.png) |
APSEC ![In: 8th Asia-Pacific Software Engineering Conference (APSEC 2001), 4-7 December 2001, Macau, China, pp. 161-168, 2001, IEEE Computer Society, 0-7695-1408-1. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
29 | Alessandro Bogliolo, Luca Benini, Giovanni De Micheli, Bruno Riccò |
Gate-level power and current simulation of CMOS integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 5(4), pp. 473-488, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | Junguk Cho, Shahnam Mirzaei, Jason Oberg, Ryan Kastner |
Fpga-based face detection system using Haar classifiers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 17th International Symposium on Field Programmable Gate Arrays, FPGA 2009, Monterey, California, USA, February 22-24, 2009, pp. 103-112, 2009, ACM, 978-1-60558-410-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
haar classifier, fpga, image processing, real-time, architecture, face detection, adaboost |
19 | Jaeyoung Yi, Karam Park, Joonseok Park, Won Woo Ro |
Fully Pipelined Hardware Implementation of 128-Bit SEED Block Cipher Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARC ![In: Reconfigurable Computing: Architectures, Tools and Applications, 5th International Workshop, ARC 2009, Karlsruhe, Germany, March 16-18, 2009. Proceedings, pp. 181-192, 2009, Springer, 978-3-642-00640-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Block Cipher Algorithm, Field Programmable Gate Arrays (FPGA), Cryptography, SEED |
19 | Chun-Lung Hsu, Yu-Sheng Huang |
A Fast-Deblocking Boundary-strength Based Architecture Design of Deblocking Filter in H.264/AVC Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Signal Process. Syst. ![In: J. Signal Process. Syst. 52(3), pp. 211-229, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FDBS, H.264/AVC, PSNR, bit-rate, deblocking filter |
19 | Christian Haufe, Frank Rogin |
Ad-Hoc Translations to Close Verilog Semantics Gap. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DDECS ![In: Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008, pp. 195-200, 2008, IEEE Computer Society, 978-1-4244-2276-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Jaume Joven, Oriol Font-Bach, David Castells-Rufas, Ricardo Martínez, Lluís Terés, Jordi Carrabina |
xENoC - An eXperimental Network-On-Chip Environment for Parallel Distributed Computing on NoC-based MPSoC Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 16th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2008), 13-15 February 2008, Toulouse, France, pp. 141-148, 2008, IEEE Computer Society, 978-0-7695-3089-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
NoC-based MPSoCs, Message Passing Interface, Distributed Programming, Design Tools and Techniques |
19 | Mehdi Dehbashi, Vahid Lari, Seyed Ghassem Miremadi, Mohammad Shokrollah-Shirazi |
Fault Effects in FlexRay-Based Networks with Hybrid Topology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARES ![In: Proceedings of the The Third International Conference on Availability, Reliability and Security, ARES 2008, March 4-7, 2008, Technical University of Catalonia, Barcelona , Spain, pp. 491-496, 2008, IEEE Computer Society, 978-0-7695-3102-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FlexRay Protocol, Fault Injection, Error Propagation, Distributed Embedded Systems, Dependability Evaluation |
19 | Ruchika Verma, Ali Akoglu |
A coarse grained and hybrid reconfigurable architecture with flexible NoC router for variable block size motion estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 22nd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2008, Miami, Florida USA, April 14-18, 2008, pp. 1-8, 2008, IEEE. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Miaoqing Huang, Kris Gaj, Soonhak Kwon, Tarek A. El-Ghazawi |
An Optimized Hardware Architecture for the Montgomery Multiplication Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Public Key Cryptography ![In: Public Key Cryptography - PKC 2008, 11th International Workshop on Practice and Theory in Public-Key Cryptography, Barcelona, Spain, March 9-12, 2008. Proceedings, pp. 214-228, 2008, Springer, 978-3-540-78439-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MWR2MM Algorithm, Field Programmable Gate Arrays, Montgomery Multiplication |
19 | Koji Nakano, Kensuke Kawakami, Koji Shigemoto, Yuki Kamada, Yasuaki Ito |
A Tiny Processing System for Education and Small Embedded Systems on the FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUC (2) ![In: 2008 IEEE/IPIP International Conference on Embedded and Ubiquitous Computing (EUC 2008), Shanghai, China, December 17-20, 2008, Volume II: Workshops, pp. 472-479, 2008, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Shahid Rizwan |
Retimed Decomposed Serial Berlekamp-Massey (BM) Architecture for High-Speed Reed-Solomon Decoding. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 21st International Conference on VLSI Design (VLSI Design 2008), 4-8 January 2008, Hyderabad, India, pp. 53-58, 2008, IEEE Computer Society, 0-7695-3083-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
19 | Xiang Xiao, Jaehwan John Lee |
A Novel Parallel Deadlock Detection Algorithm and Hardware for Multiprocessor System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Comput. Archit. Lett. ![In: IEEE Comput. Archit. Lett. 6(2), pp. 41-44, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Maria Stepanova, Feng Lin 0002, Valerie C.-L. Lin |
A Hopfield Neural Classifier and Its FPGA Implementation for Identification of Symmetrically Structured DNA Motifs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 48(3), pp. 239-254, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
DNA motifs, sequence structure identification, hopfield classifier, field-programmable gate arrays, recurrent neural network |
19 | Muhammad T. Anan, Ghulam M. Chaudhry |
A Real-Time Hardware-Based Scheduler For Next-Generation Optical Burst Switches. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICC ![In: Proceedings of IEEE International Conference on Communications, ICC 2007, Glasgow, Scotland, UK, 24-28 June 2007, pp. 2289-2293, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Xiao Hu, Pengyong Ma, Shuming Chen |
Scheduling for Combining Traffic of On-Chip Trace Data in Embedded Multi-core Processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICESS ![In: Embedded Software and Systems, [Third] International Conference, ICESS 2007, Daegu, Korea, May 14-16, 2007, Proceedings, pp. 67-79, 2007, Springer, 978-3-540-72684-5. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Jin-Oh Jeon, Su-Bong Ryu, Tae-Min Chang, Ho-Yong Choi, Min-Sup Kang |
Digital Codec Design for RFID Tag Based on Cryptographic Authentication Protocol. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FGCN (2) ![In: Future Generation Communication and Networking, FGCN 2007, Ramada Plaza Jeju, Jeju-Island, Korea, December 6-8, 2007, Proceedings, pp. 119-124, 2007, IEEE Computer Society. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Ik-Jae Chun, Tae Moon Roh, Bo-Gwan Kim |
Binary-Truncated CDMA-Based On-Chip Network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2007), 27-20 May 2007, New Orleans, Louisiana, USA, pp. 397-400, 2007, IEEE, 1-4244-0920-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Jun Wang 0010, Kyeong-Yuk Min, Jong-Wha Chong |
A Hybrid Image Coding in Overdriving for Motion Blur Reduction in LCD. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEC ![In: Entertainment Computing - ICEC 2007, 6th International Conference, Shanghai, China, September 15-17, 2007, Proceedings, pp. 263-270, 2007, Springer, 978-3-540-74872-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Overdriving, Block Truncation Coding, Adaptive Quantization Coding, Compression, LCD, Motion blur |
19 | Mustafa Parlak, Ilker Hamzaoglu |
A Low Power Implementation of H.264 Adaptive Deblocking Filter Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AHS ![In: Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), August 5-8, 2007, University of Edinburgh, Scotland, United Kingdom, pp. 127-133, 2007, IEEE Computer Society, 0-7695-2866-X. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
19 | Jin-Oh Jeon, Su-Bong Ryu, Sang-Jo Park, Min-Sup Kang |
Strong Authentication Protocol for RFID Tag Using SHA-1 Hash Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCSA (1) ![In: Computational Science and Its Applications - ICCSA 2007, International Conference, Kuala Lumpur, Malaysia, August 26-29, 2007. Proceedings, Part I, pp. 634-643, 2007, Springer, 978-3-540-74468-9. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Strong authentication protocol, SHA-1 hash algorithm, Three-way challenge response, ISO/IEC 1800-3 standard, Digital Codec design, RFID Tag |
19 | Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong |
An Efficient VLSI Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MMM (2) ![In: Advances in Multimedia Modeling, 13th International Multimedia Modeling Conference, MMM 2007, Singapore, January 9-12, 2007. Proceedings, Part II, pp. 41-50, 2007, Springer, 978-3-540-69428-1. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
VBSME, VLSI, motion estimation, H.264/AVC, block matching algorithm |
19 | Jaehwan John Lee, Vincent John Mooney |
A Novel {O(n)} Parallel Banker's Algorithm for System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Parallel Distributed Syst. ![In: IEEE Trans. Parallel Distributed Syst. 17(12), pp. 1377-1389, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Parallel Banker's Algorithm, deadlock avoidance in hardware, multiprocessor system-on-a-chip |
19 | Alexander Kamkin |
The UniTESK Approach to Specification-Based Validation of Hardware Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISoLA ![In: Leveraging Applications of Formal Methods, Second International Symposium, ISoLA 2006, Paphos, Cyprus, 15-19 November 2006, pp. 60-66, 2006, IEEE Computer Society, 978-0-7695-3071-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Baofeng Li, Qiang Shao |
Deeply Parallel Architecture for Lifting-Based 2D DWT in JPEG2000. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIT ![In: Sixth International Conference on Computer and Information Technology (CIT 2006), 20-22 September 2006, Seoul, Korea, pp. 178, 2006, IEEE Computer Society, 0-7695-2687-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Choudhury A. Rahman, Wael M. Badawy |
An Area Efficient Real-time CAVLC IP-Block towards the H.264/AVC Encoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SiPS ![In: Proceedings of the IEEE Workshop on Signal Processing Systems, SiPS 2006, Proceedings, October 2-4, 2006, Banff, Alberta, Canada, pp. 368-371, 2006, IEEE, 1-4244-0382-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Seung-Man Pyen, Kyeong-Yuk Min, Jong-Wha Chong, Satoshi Goto |
An Efficient Hardware Architecture for Full-Search Variable Block Size Motion Estimation in H.264/AVC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVC (2) ![In: Advances in Visual Computing, Second International Symposium, ISVC 2006 Lake Tahoe, NV, USA, November 6-8, 2006. Proceedings, Part II, pp. 554-563, 2006, Springer. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Zude Zhou, Songlin Cheng, Quan Liu |
Application of DDR Controller for High-speed Data Acquisition Board. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICICIC (2) ![In: First International Conference on Innovative Computing, Information and Control (ICICIC 2006), 30 August - 1 September 2006, Beijing, China, pp. 611-614, 2006, IEEE Computer Society, 0-7695-2616-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Pawel Garstecki, Adam Luczak, Marta Stepniewska |
A bit-serial implementation of mode decision algorithm for AVC encoders. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Kimo Kim, In-Cheol Park |
Combined image signal processing for CMOS image sensors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Junhao Zheng, Di Wu 0022, Lei Deng 0007, Don Xie, Wen Gao 0001 |
A Motion Vector Predictor Architecture for AVS and MPEG-2 HDTV Decoder. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PCM ![In: Advances in Multimedia Information Processing - PCM 2006, 7th Pacific Rim Conference on Multimedia, Hangzhou, China, November 2-4, 2006, Proceedings, pp. 424-431, 2006, Springer, 3-540-48766-2. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
Motion vector prediction, MPEG, Motion compensation, VLSI architecture, AVS |
19 | Wonwoo Jang, Hyunsik Kim, Sungmok Lee, Jooyoung Ha, Bongsoon Kang |
Implementation of the Gamma Line System Similar to Non-linear Gamma Curve with 2bit Error(LSB). ![Search on Bibsonomy](Pics/bibsonomy.png) |
APCCAS ![In: IEEE Asia Pacific Conference on Circuits and Systems 2006, APCCAS 2006, Singapore, 4-7 December 2006, pp. 283-286, 2006, IEEE, 1-4244-0387-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Insu Song, Guido Governatori |
Designing agent chips. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AAMAS ![In: 5th International Joint Conference on Autonomous Agents and Multiagent Systems (AAMAS 2006), Hakodate, Japan, May 8-12, 2006, pp. 1311-1313, 2006, ACM, 1-59593-303-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
agent chips, agent architecture, agent programming languages |
19 | Jung L. Lee, Myung Hoon Sunwoo |
Implementation of a Wireless Multimedia DSP Chip for Mobile Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 40(3), pp. 281-287, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multimedia, DSP, instruction |
19 | Saranyan A. Vigraham, John C. Gallagher |
A space saving digital VLSI evolutionary engine for CTRNN-EH devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Congress on Evolutionary Computation ![In: Proceedings of the IEEE Congress on Evolutionary Computation, CEC 2005, 2-4 September 2005, Edinburgh, UK, pp. 2483-2490, 2005, IEEE, 0-7803-9363-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Jaehwan John Lee, Vincent John Mooney III |
A novel O(n) parallel banker's algorithm for System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1304-1308, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Mathias Halbach, Rolf Hoffmann |
Optimal Behavior of a Moving Creature in the Cellular Automata Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PaCT ![In: Parallel Computing Technologies, 8th International Conference, PaCT 2005, Krasnoyarsk, Russia, September 5-9, 2005, Proceedings, pp. 129-140, 2005, Springer, 3-540-28126-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Gyu-Sung Yeon, Chi-Hun Jun, Tae-Jin Hwang, Seongsoo Lee, Jae-Kyung Wee |
Low-Power MPEG-4 Motion Estimator Design for Deep Sub-Micron Multimedia SoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
KES (3) ![In: Knowledge-Based Intelligent Information and Engineering Systems, 9th International Conference, KES 2005, Melbourne, Australia, September 14-16, 2005, Proceedings, Part III, pp. 449-455, 2005, Springer, 3-540-28896-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Hua Li, Jianzhou Li |
A High Performance Sub-Pipelined Architecture for AES. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 23rd International Conference on Computer Design (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, pp. 491-496, 2005, IEEE Computer Society, 0-7695-2451-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
sub-pipelined architecture, FPGA, cryptography, AES |
19 | Tadashi Saito, Moto Maeda, Tetsuo Hironaka, Kazuya Tanigawa, Tetsuya Sueyoshi, Ken-ichi Aoyama, Tetsushi Koide, Hans Jürgen Mattausch |
Design of superscalar processor with multi-bank register file. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3507-3510, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Yasuhiro Takahashi, Michio Yokoyama |
New cost-effective VLSI implementation of multiplierless FIR filter using common subexpression elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (2) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 1445-1448, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Donghyun Kim, Kangmin Lee, Se-Joong Lee, Hoi-Jun Yoo |
A reconfigurable crossbar switch with adaptive bandwidth control for networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2369-2372, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Ping Dong, Xiangdong Shi, Jiehui Yang |
Design of a New Kind of Encryption Kernel Based on RSA Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CIS (2) ![In: Computational Intelligence and Security, International Conference, CIS 2005, Xi'an, China, December 15-19, 2005, Proceedings, Part II, pp. 27-32, 2005, Springer, 3-540-30819-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|