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Publication years (Num. hits)
1984-1989 (16) 1990-1991 (18) 1992-1993 (31) 1994 (15) 1995-1996 (31) 1997 (30) 1998 (24) 1999 (38) 2000 (54) 2001 (53) 2002 (67) 2003 (58) 2004 (61) 2005 (88) 2006 (71) 2007 (84) 2008 (55) 2009 (30) 2010 (25) 2011 (27) 2012 (31) 2013 (25) 2014 (29) 2015 (21) 2016 (21) 2017 (26) 2018-2019 (26) 2020-2022 (16) 2023-2024 (5)
Publication types (Num. hits)
article(258) book(2) incollection(4) inproceedings(786) phdthesis(26)
Venues (Conferences, Journals, ...)
MICRO(44) DATE(38) ICCD(24) DAC(22) ASAP(21) CASES(19) IEEE Trans. Computers(17) IEEE Trans. Very Large Scale I...(15) IPDPS(15) ASP-DAC(14) ISSS(14) J. Signal Process. Syst.(13) VLSI Design(13) Euro-Par(12) IEEE PACT(12) ISCAS(12) More (+10 of total 312)
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The graphs summarize 908 occurrences of 401 keywords

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Found 1076 publication records. Showing 1076 according to the selection in the facets
Hits ? Authors Title Venue Year Link Author keywords
106Hans M. Mulder, Robert J. Portier Cost-effective design of application specific VLIW processors using the SCARCE framework. Search on Bibsonomy MICRO The full citation details ... 1989 DBLP  DOI  BibTeX  RDF
103Weifeng Xu, Russell Tessier Tetris-XL: A performance-driven spill reduction technique for embedded VLIW processors. Search on Bibsonomy ACM Trans. Archit. Code Optim. The full citation details ... 2009 DBLP  DOI  BibTeX  RDF Very Long Instruction Word (VLIW) processor, instruction level parallelism, Register pressure
103Rahul Nagpal, Y. N. Srikant Compiler-assisted leakage energy optimization for clustered VLIW architectures. Search on Bibsonomy EMSOFT The full citation details ... 2006 DBLP  DOI  BibTeX  RDF scheduling, leakage energy, energy-aware scheduling, clustered VLIW processors
95Seongbae Park, SangMin Shim, Soo-Mook Moon Evaluation of Scheduling Techniques on a SPARC-based VLIW Testbed. Search on Bibsonomy MICRO The full citation details ... 1997 DBLP  DOI  BibTeX  RDF SPARC-based VLIW testbed, VLIW microprocessors, Very Long Instruction Word microprocessors, all-path speculation, gcc-generated optimized SPARC code, high-performance VLIW code, nongreedy enhanced pipeline scheduling, nonspeculative operations, profile-based all-path speculation, restricted speculative loads, scheduling compiler, speculative operations, trace-based speculation, performance, compiler, computer architecture, parallel machines, software pipelining, loop unrolling, renaming, memory disambiguation, copies, scheduling techniques
93Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuchi, Masaharu Imai A low power VLIW processor generation method by means of extracting non-redundant activation conditions. Search on Bibsonomy CODES+ISSS The full citation details ... 2007 DBLP  DOI  BibTeX  RDF low power, ASIP, clock gating, VLIW processor
90Anup Gangwar, M. Balakrishnan, Anshul Kumar Impact of intercluster communication mechanisms on ILP in clustered VLIW architectures. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF performance evaluation, VLIW, ASIP, clustered VLIW processors
84Jun Yan 0008, Wei Zhang 0002 A time-predictable VLIW processor and its compiler support. Search on Bibsonomy Real Time Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF if-conversion, Compiler, VLIW, WCET analysis, Time-predictability
84Weifeng Xu, Russell Tessier Tetris: a new register pressure control technique for VLIW processors. Search on Bibsonomy LCTES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF register pressure control, very long instruction word (VLIW) processor, instruction level parallelism
84Emre Özer 0001, Thomas M. Conte High-Performance and Low-Cost Dual-Thread VLIW Processor Using Weld Architecture Paradigm. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Multithreaded processors, VLIW architectures, modeling of computer architecture
84Alberto Ferreira de Souza, Peter Rounce On the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture. Search on Bibsonomy IPDPS The full citation details ... 2000 DBLP  DOI  BibTeX  RDF DTSVLIW, VLIW, Instruction scheduling
81Andrew Wolfe, Jason Fritts, Santanu Dutta, Edil S. T. Fernandes Datapath Design for a VLIW Video Signal Processor. Search on Bibsonomy HPCA The full citation details ... 1997 DBLP  DOI  BibTeX  RDF datapath design, VLIW video signal processor, very long instruction word, high parallelism, high-level language programmability, high-bandwidth interconnect, high-connectivity register files, parameterizable versions, VLSI, video signal processing, VLIW architectures, compiler design
75Andrei Sergeevich Terechko, Henk Corporaal Inter-cluster communication in VLIW architectures. Search on Bibsonomy ACM Trans. Archit. Code Optim. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF intercluster communication, pipelining, Instruction-level parallelism, register allocation, VLIW, instruction scheduler, optimizing compiler, clock frequency, cluster assignment
72Tetsuya Hara, Hideki Ando, Chikako Nakanishi, Masao Nakaya Performance Comparison of ILP Machines with Cycle Time Evaluation. Search on Bibsonomy ISCA The full citation details ... 1996 DBLP  DOI  BibTeX  RDF
70Zhixiong Zhou, Hu He 0001, Yanjun Zhang, Yihe Sun, Adriel Cheng A 2-Dimension Force-Directed Scheduling Algorithm for Register-File-Connectivity Clustered VLIW Architecture. Search on Bibsonomy ASAP The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
70Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael S. Schlansker A Distributed Control Path Architecture for VLIW Processors. Search on Bibsonomy IEEE PACT The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
70Bharath Iyer, Sadagopan Srinivasan, Bruce L. Jacob Extended Split-Issue: Enabling Flexibility in the Hardware Implementation of NUAL VLIW DSPs. Search on Bibsonomy ISCA The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
70Marco Danelutto, Marco Vanneschi VLIW-in-the-large: a model for fine grain parallelism exploitation on distributed memory multiprocessors. Search on Bibsonomy MICRO The full citation details ... 1990 DBLP  BibTeX  RDF
69Partha Biswas, Nikil D. Dutt Code Size Reduction in Heterogeneous-Connectivity-Based DSPs Using Instruction Set Extensions. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2005 DBLP  DOI  BibTeX  RDF DSP, VLIW, ASIP, Coprocessors, instruction set extensions, code size reduction
69Ivano Barbieri, Massimo Bariani, Alberto Cabitto, Marco Raggio A Simulation and Exploration Technology for Multimedia-Application-Driven Architectures. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2005 DBLP  DOI  BibTeX  RDF Hw-Sw co-design, simulation speed, simulation accuracy, simulation, multimedia, system on chip, DSP, flexibility, VLIW, architecture exploration, ISA
66Chung-Kai Chen, Ling-Hua Tseng, Shih-Chang Chen, Young-Jia Lin, Yi-Ping You, Chia-Han Lu, Jenq Kuen Lee Enabling compiler flow for embedded VLIW DSP processors with distributed register files. Search on Bibsonomy LCTES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF distributed register files, embedded VLIW DSP compilers, software pipelining
66Milos Becvár, Stanislav Kahánek VLIW-DLX simulator for educational purposes. Search on Bibsonomy WCAE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF simulation, education, computer architecture, VLIW
66Chingren Lee, Jenq Kuen Lee, TingTing Hwang, Shi-Chun Tsai Compiler optimization on VLIW instruction scheduling for low power. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2003 DBLP  DOI  BibTeX  RDF VLIW instruction scheduling, instruction bus optimizations, low-power optimization, Compilers
66Xiushan Feng, Alan J. Hu Automatic formal verification for scheduled VLIW code. Search on Bibsonomy LCTES-SCOPES The full citation details ... 2002 DBLP  DOI  BibTeX  RDF theory of equality with uninterpreted functions, formal verification, DSP, symbolic execution, VLIW
66Sunghyun Jee, Kannappan Palaniappan Performance evaluation for a compressed-VLIW processor. Search on Bibsonomy SAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF CVLIW processor, individual instruction scheduling, VLIW, ILP
66Sunghyun Jee, Kannappan Palaniappan Dynamically Scheduling VLIW Instructions with Dependency Information. Search on Bibsonomy Interaction between Compilers and Computer Architectures The full citation details ... 2002 DBLP  DOI  BibTeX  RDF DISVLIW, VLIW, Dynamic Scheduling, Processor Architecture, ILP
66Andrea Bona, Mariagiovanna Sami, Donatella Sciuto, Vittorio Zaccaria, Cristina Silvano, Roberto Zafalon Energy estimation and optimization of embedded VLIW processors based on instruction clustering. Search on Bibsonomy DAC The full citation details ... 2002 DBLP  DOI  BibTeX  RDF power estimation, vliw architectures
66Shyh-Kwei Chen, W. Kent Fuchs Compiler-Assisted Multiple Instruction Word Retry for VLIW Architectures. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF compilers, Fault-tolerant computing, instruction level parallelism, VLIW architectures, instruction retry
63Anup Gangwar, M. Balakrishnan, Preeti Ranjan Panda, Anshul Kumar Evaluation of Bus Based Interconnect Mechanisms in Clustered VLIW Architectures. Search on Bibsonomy Int. J. Parallel Program. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Performance evaluation, VLIW, ASIP, Clustered VLIW processors
63Soo-Mook Moon, Scott D. Carson Generalized Multiway Branch Unit for VLIW Microprocessors. Search on Bibsonomy IEEE Trans. Parallel Distributed Syst. The full citation details ... 1995 DBLP  DOI  BibTeX  RDF generalized multiway branching, VLIW microprocessor, condition tree, mirror normalization, VLIW compiler, Instruction-level parallelism, superscalar microprocessor
61Yingchao Zhao 0001, Chun Jason Xue, Minming Li, Bessie C. Hu Energy-aware register file re-partitioning for clustered VLIW architectures. Search on Bibsonomy ASP-DAC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
61Manoj Gupta 0001, Fermín Sánchez, Josep Llosa Cluster-level simultaneous multithreading for VLIW processors. Search on Bibsonomy ICCD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
61Andrei Sergeevich Terechko, Manish Garg, Henk Corporaal Evaluation of Speed and Area of Clustered VLIW Processors. Search on Bibsonomy VLSI Design The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
61Pradeep Rao, S. K. Nandy 0001, M. N. V. Satya Kiran Simultaneous MultiStreaming for Complexity-Effective VLIW Architectures. Search on Bibsonomy Asia-Pacific Computer Systems Architecture Conference The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
61Christoforos E. Kozyrakis, David A. Patterson 0001 Vector vs. superscalar and VLIW architectures for embedded multimedia benchmarks. Search on Bibsonomy MICRO The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
61Tarun Nakra, Rajiv Gupta 0001, Mary Lou Soffa Value Prediction in VLIW Machines. Search on Bibsonomy ISCA The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
61Wolfgang Karl Some Design Aspects for VLIW Architectures Exploiting Fine - Grained Parallelism. Search on Bibsonomy PARLE The full citation details ... 1993 DBLP  DOI  BibTeX  RDF
60Kemal Ebcioglu, Erik R. Altman DAISY: Dynamic Compilation for 100% Architectural Compatibility. Search on Bibsonomy ISCA The full citation details ... 1997 DBLP  DOI  BibTeX  RDF object code compatible VLIW, instruction-level parallelism, superscalar, binary translation, dynamic compilation
57Anupam Chattopadhyay, Harold Ishebabi, Xiaolin Chen, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr Prefabrication and postfabrication architecture exploration for partially reconfigurable VLIW processors. Search on Bibsonomy ACM Trans. Embed. Comput. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF coarse-grained FPGA, VLIW, ASIP
57Kun-Yuan Hsieh, Yung-Chia Lin, Chien-Ching Huang, Jenq Kuen Lee Enhancing Microkernel Performance on VLIW DSP Processors via Multiset Context Switch. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF VLIW DSP processor, optimizing context switch overhead, microkernel design
57Yuki Kobayashi, Murali Jayapala, Praveen Raghavan, Francky Catthoor, Masaharu Imai Methodology for operation shuffling and L0 cluster generation for low energy heterogeneous VLIW processors. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF Compilers for low energy, loop buffers, VLIW processors
57Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster 0001 An FPGA-based VLIW processor with custom hardware execution. Search on Bibsonomy FPGA The full citation details ... 2005 DBLP  DOI  BibTeX  RDF NIOS, parallelism, compiler, synthesis, kernels, VLIW
57Kostas Masselos, Francky Catthoor, Constantinos E. Goutis, Hugo De Man Combined Application of Data Transfer and Storage Optimizing Transformations and Subword Parallelism Exploitation for Power Consumption and Execution Time Reduction in VLIW Multimedia Processors. Search on Bibsonomy J. VLSI Signal Process. The full citation details ... 2004 DBLP  DOI  BibTeX  RDF low-power-dissipation, performance, memory, VLIW processors, multi-media, code transformations, subword parallelism, system level
57Andrei Sergeevich Terechko, Erwan Le Thenaff, Henk Corporaal Cluster assignment of global values for clustered VLIW processors. Search on Bibsonomy CASES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF compiler, register allocation, VLIW, instruction scheduler, ILP, cluster assignment
57Osvaldo Colavin, Davide Rizzo A scalable wide-issue clustered VLIW with a reconfigurable interconnect. Search on Bibsonomy CASES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF clustered VLIW, reconfigurable co-processor (RCP), modulo scheduling, IDCT
57Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon Branch prediction techniques for low-power VLIW processors. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2003 DBLP  DOI  BibTeX  RDF low-power design, branch prediction, VLIW processors
57Carles Rodoreda Sala, Natalino G. Busá A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor. Search on Bibsonomy ISSS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF VLIW processors, reconfigurable logic, architectural synthesis
57Emre Özer 0001, Sumedh W. Sathaye, Kishore N. Menezes, Sanjeev Banerjia, Matthew D. Jennings, Thomas M. Conte A Fast Interrupt Handling Scheme for VLIW Processors. Search on Bibsonomy IEEE PACT The full citation details ... 1998 DBLP  DOI  BibTeX  RDF Interrupt, VLIW, Embedded Processors, ILP, Superscalar, Out-of-order Issue
52Talal Bonny, Jörg Henkel FBT: filled buffer technique to reduce code size for VLIW processors. Search on Bibsonomy ICCAD The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
52Mario Schölzel Interactive presentation: Time-constrained clustering for DSE of clustered VLIW-ASP. Search on Bibsonomy DATE The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
52Manoj Gupta 0001, Fermín Sánchez, Josep Llosa Merge Logic for Clustered Multithreaded VLIW Processors. Search on Bibsonomy DSD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
52Rahul Nagpal, Y. N. Srikant Register File Energy Optimization for Snooping Based Clustered VLIW Architectures. Search on Bibsonomy SBAC-PAD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
52Chi Wu, Kun-Yuan Hsieh, Yung-Chia Lin, Chung-Ju Wu, Wen-Li Shih, Shih-Chang Chen, Chung-Kai Chen, Chien-Ching Huang, Yi-Ping You, Jenq Kuen Lee Integrating Compiler and System Toolkit Flow for Embedded VLIW DSP Processors. Search on Bibsonomy RTCSA The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Chung-Ju Wu, Sheng-Yuan Chen, Jenq Kuen Lee Copy Propagation Optimizations for VLIW DSP Processors with Distributed Register Files. Search on Bibsonomy LCPC The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Peter Rounce, Alberto Ferreira de Souza The mDTSVLIW: a Multi-Threaded Trace-based VLIW Architecture. Search on Bibsonomy SBAC-PAD The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Jiangjiang Liu 0002, Brian Bell, Tan Truong Analysis and Characterization of Intel Itanium Instruction Bundles for Improving VLIW Processor Performance. Search on Bibsonomy IMSCCS (1) The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
52Alberto Ferrante, Giuseppe Piscopo, Stefano Scaldaferri Application-Driven Optimization of VLIW Architectures: A Hardware-Software Approach. Search on Bibsonomy IEEE Real-Time and Embedded Technology and Applications Symposium The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
52Esther Salamí, Mateo Valero A Vector-µSIMD-VLIW Architecture for Multimedia Applications. Search on Bibsonomy ICPP The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
52Diviya Jain, Anshul Kumar, Laura Pozzi, Paolo Ienne Automatically Customising VLIW Architectures with Coarse Grained Application-Specific Functional Units. Search on Bibsonomy SCOPES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF
52Partha Biswas, Nikil D. Dutt Reducing code size for heterogeneous-connectivity-based VLIW DSPs through synthesis of instruction set extensions. Search on Bibsonomy CASES The full citation details ... 2003 DBLP  DOI  BibTeX  RDF dependence conflict graph, heterogeneous-connectivity-based DSP, restricted data dependence graph, instruction set extensions, instruction set architecture, static single assignment
52Tay-Jyi Lin, Chin-Chi Chang, Chen-Chia Lee, Chein-Wei Jen An Efficient VLIW DSP Architecture for Baseband Processing. Search on Bibsonomy ICCD The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
52Yuan Xie 0001, Wayne H. Wolf, Haris Lekatsas A code decompression architecture for VLIW processors. Search on Bibsonomy MICRO The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
52Jae-Woo Ahn, Soo-Mook Moon, Wonyong Sung Feedback-directed memory disambiguation for embedded multimedia VLIW computing. Search on Bibsonomy ISCAS (2) The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
52Ram Lakhan Gupta, Anshul Kumar, Aalbert Van Der Werf, Natalino G. Busá Synthesizing A Long Latency Unit Within Vliw Processor. Search on Bibsonomy VLSI Design The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
52Deependra Talla, Lizy Kurian John, Viktor S. Lapinskii, Brian L. Evans Evaluating Signal Processing and Multimedia Applications on SIMD, VLIW and Superscalar Architectures. Search on Bibsonomy ICCD The full citation details ... 2000 DBLP  DOI  BibTeX  RDF
52Alberto Ferreira de Souza, Peter Rounce Dynamically Scheduling the Trace Produced During Program Execution into VLIW Instructions. Search on Bibsonomy IPPS/SPDP The full citation details ... 1999 DBLP  DOI  BibTeX  RDF
52Monica S. Lam Software pipelining: an effective scheduling technique for VLIW machines (with retrospective) Search on Bibsonomy Best of PLDI The full citation details ... 1988 DBLP  DOI  BibTeX  RDF
48Manoj Gupta 0001, Fermín Sánchez, Josep Llosa Hybrid multithreading for VLIW processors. Search on Bibsonomy CASES The full citation details ... 2009 DBLP  DOI  BibTeX  RDF multithreading, clustered VLIW processors
48Yung-Chia Lin, Chia-Han Lu, Chung-Ju Wu, Chung-Lin Tang, Yi-Ping You, Ya-Chiao Moo, Jenq Kuen Lee Effective Code Generation for Distributed and Ping-Pong Register Files: A Case Study on PAC VLIW DSP Cores. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF ping-pong register files, clustering, parallel processing, compiler, DSP, VLIW
48Tay-Jyi Lin, Shin-Kai Chen, Yu-Ting Kuo, Chih-Wei Liu, Pi-Chen Hsiao Design and Implementation of a High-Performance and Complexity-Effective VLIW DSP for Multimedia Applications. Search on Bibsonomy J. Signal Process. Syst. The full citation details ... 2008 DBLP  DOI  BibTeX  RDF register organization, VLIW, digital signal processor, micro-architecture, instruction encoding
48Shu Xiao 0001, Edmund Ming-Kit Lai VLIW instruction scheduling for minimal power variation. Search on Bibsonomy ACM Trans. Archit. Code Optim. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF power variation reduction, Instruction scheduling, VLIW processors
48Shan Yan, Bill Lin 0001 Stream execution on wide-issue clustered VLIW architectures. Search on Bibsonomy LCTES The full citation details ... 2007 DBLP  DOI  BibTeX  RDF scheduling, compilers, VLIW processors, stream programming
48Madhu Mutyam, Feihui Li, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin Compiler-directed thermal management for VLIW functional units. Search on Bibsonomy LCTES The full citation details ... 2006 DBLP  DOI  BibTeX  RDF VLIW, thermal, IPC
48Antonio Carlos Schneider Beck, Luigi Carro A VLIW low power Java processor for embedded applications. Search on Bibsonomy SBCCI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF Java, power consumption, VLIW
48Binu K. Mathew, Al Davis A loop accelerator for low power embedded VLIW processors. Search on Bibsonomy CODES+ISSS The full citation details ... 2004 DBLP  DOI  BibTeX  RDF embedded systems, low power design, VLIW
48Montserrat Ros, Peter Sutton A hamming distance based VLIW/EPIC code compression technique. Search on Bibsonomy CASES The full citation details ... 2004 DBLP  DOI  BibTeX  RDF VLIW, hamming distance, code compression
48Matteo Monchiero, Gianluca Palermo, Mariagiovanna Sami, Cristina Silvano, Vittorio Zaccaria, Roberto Zafalon Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors. Search on Bibsonomy ACM Great Lakes Symposium on VLSI The full citation details ... 2004 DBLP  DOI  BibTeX  RDF low-power design, branch prediction, VLIW processors
48Alberto Macii, Enrico Macii, Fabrizio Crudo, Roberto Zafalon A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors. Search on Bibsonomy DATE The full citation details ... 2003 DBLP  DOI  BibTeX  RDF Data compression algorithms, system-level energy optimization, VLIW embedded processors
48V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff An Implementation for Test-Time Reduction in VLIW Transport-Triggered Architectures. Search on Bibsonomy J. Electron. Test. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF VLIW processor test, test-time analysis, Design for Testability (DfT), test synthesis
48Enric Gibert, F. Jesús Sánchez, Antonio González 0001 An interleaved cache clustered VLIW processor. Search on Bibsonomy ICS The full citation details ... 2002 DBLP  DOI  BibTeX  RDF attraction buffers, modulo scheduling, VLIW processors, distributed cache, clustered microarchitectures
48Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats. Search on Bibsonomy ACM Trans. Design Autom. Electr. Syst. The full citation details ... 2000 DBLP  DOI  BibTeX  RDF code size minimization, custom templates, instruction format design, noop compression, retargetable assembly, VLIW, design automation, EPIC
48Zhao Wu, Wayne H. Wolf Design Study of Shared Memory in VLIW Video Signal Processors. Search on Bibsonomy IEEE PACT The full citation details ... 1998 DBLP  DOI  BibTeX  RDF VSP, stride prediction table, cache, shared memory, VLIW, trace-driven simulation, memory system, stream buffer, multi-cluster
47Clifford Liem, Pierre G. Paulin, Marco Cornero, Ahmed Amine Jerraya Industrial experience using rule-driven retargetable code generation for multimedia applications. Search on Bibsonomy ISSS The full citation details ... 1995 DBLP  DOI  BibTeX  RDF VideoPhone codec controller, audio telecommunications, dedicated compiler availability, high-fidelity audio, optimization abilities, rule-driven retargetable code generation, video telecommunications, knowledge based systems, computer architecture, multiprocessing systems, multimedia systems, application specific integrated circuits, multimedia applications, application-specific instruction set processors, instruction sets, telecommunication computing, codecs, VLIW processor, VLIW architecture, transformation rules, controller architecture, optimising compilers, industrial experience, videotelephony, target architecture, MPEG audio
45Hai Lin 0004, Yunsi Fei Harnessing Horizontal Parallelism and Vertical Instruction Packing of Programs to Improve System Overall Efficiency. Search on Bibsonomy DATE The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
44Manoj Gupta 0001, Fermín Sánchez, Josep Llosa CSMT: Simultaneous Multithreading for Clustered VLIW Processors. Search on Bibsonomy IEEE Trans. Computers The full citation details ... 2010 DBLP  DOI  BibTeX  RDF clustered VLIW architectures, ILP, simultaneous multithreading, multithreaded processors, VLIW architectures
43Samir Ammenouche, Sid Ahmed Ali Touati, William Jalby On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors. Search on Bibsonomy HPCC The full citation details ... 2009 DBLP  DOI  BibTeX  RDF
43Markus Koester, Wayne Luk, Geoffrey Brown A hardware compilation flow for instance-specific VLIW cores. Search on Bibsonomy FPL The full citation details ... 2008 DBLP  DOI  BibTeX  RDF
43Ihor O. Kirenko, René J. van der Vleuten, Ling Shao 0001 Optimizing Scalable Video Compression for Efficient Implementation on a VLIW Media Processor. Search on Bibsonomy IEEE Trans. Multim. The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Manoj Gupta, Mayank Gupta, Neeraj Goel, M. Balaksrishnan Energy Based Design Space Exploration of Multiprocessor VLIW Architectures. Search on Bibsonomy DSD The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Anupam Chattopadhyay, Zoltan Endre Rakosi, Kingshuk Karuri, David Kammler, Rainer Leupers, Gerd Ascheid, Heinrich Meyr Pre- and Post-Fabrication Architecture Exploration for Partially Reconfigurable VLIW Processors. Search on Bibsonomy IEEE International Workshop on Rapid System Prototyping The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Abhishek Pillai, Wei Zhang 0002, Dimitrios Kagaris Detecting VLIW Hard Errors Cost-Effectively through a Software-Based Approach. Search on Bibsonomy AINA Workshops (1) The full citation details ... 2007 DBLP  DOI  BibTeX  RDF
43Yuan Xie 0001, Wayne H. Wolf, Haris Lekatsas Code Compression for Embedded VLIW Processors Using Variable-to-Fixed Coding. Search on Bibsonomy IEEE Trans. Very Large Scale Integr. Syst. The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Ricardo Santos 0002, Rodolfo Azevedo, Guido Araujo 2D-VLIW: An Architecture Based on the Geometry of Computation. Search on Bibsonomy ASAP The full citation details ... 2006 DBLP  DOI  BibTeX  RDF
43Kazutoshi Kobayashi, Masao Aramoto, Yoichi Yuyama, Akihiko Higuchi, Hidetoshi Onodera A resource-shared VLIW processor architecture for area-efficient on-chip multiprocessing. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Shu Xiao 0001, Edmund Ming-Kit Lai Instruction scheduling of VLIW architectures for balanced power consumption. Search on Bibsonomy ASP-DAC The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Chia-Hsien Liu, Tay-Jyi Lin, Chie-Min Chao, Pi-Chen Hsiao, Li-Chun Lin, Shin-Kai Chen, Chao-Wei Huang, Chih-Wei Liu, Chein-Wei Jen Hierarchical instruction encoding for VLIW digital signal processors. Search on Bibsonomy ISCAS (4) The full citation details ... 2005 DBLP  DOI  BibTeX  RDF
43Andrei Sergeevich Terechko, Erwan Le Thenaff, Manish Garg, Jos T. J. van Eijndhoven, Henk Corporaal Inter-Cluster Communication Models for Clustered VLIW Processors. Search on Bibsonomy HPCA The full citation details ... 2003 DBLP  DOI  BibTeX  RDF
43Mariagiovanna Sami, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria An instruction-level energy model for embedded VLIW architectures. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
43Atsushi Mizuno, Kazuyoshi Kohno, Ryuichiro Ohyama, Takahiro Tokuyoshi, Hironori Uetani, Hans Eichel, Takashi Miyamori, Nobu Matsumoto, Masataka Matsui Design Methodology and System for a Configurable Media Embedded Processor Extensible to VLIW Architecture. Search on Bibsonomy ICCD The full citation details ... 2002 DBLP  DOI  BibTeX  RDF
43Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. Search on Bibsonomy IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
43Emre Özer 0001, Thomas M. Conte, Saurabh Sharma Weld: A Multithreading Technique Towards Latency-Tolerant VLIW Processors. Search on Bibsonomy HiPC The full citation details ... 2001 DBLP  DOI  BibTeX  RDF
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