Search results for "ETW"

Hits ?▲	Authors	Title	Venue	Year	Link
1	Sandeep Kumar Goel, Erik Jan Marinissen	Control-aware test architecture design for modular SOC testing.	ETW	2003	DBLP DOI BibTeX RDF
1	Alessandra Fudoli, Alberto Ascagni, Davide Appello, Hans A. R. Manhaeve	A practical evaluation of IDDQ test strategies for deep submicron production test application. Experiences and targets from the field.	ETW	2003	DBLP DOI BibTeX RDF
1	Ozgur Sinanoglu, Alex Orailoglu	Parity-based output compaction for core-based SOCs [logic testing].	ETW	2003	DBLP DOI BibTeX RDF
1	M. J. Geuzebroek, Ad J. van de Goor	TPI for improving PR fault coverage of Boolean and three-state circuits.	ETW	2003	DBLP DOI BibTeX RDF
1	H. J. Vermaak, Hans G. Kerkhoff	Enhanced P1500 compliant wrapper suitable for delay fault testing of embedded cores.	ETW	2003	DBLP DOI BibTeX RDF
1	Salvador Manich, L. García, Luz Balado, Emili Lupon, Josep Rius 0001, Rosa Rodríguez-Montañés, Joan Figueras	On the selection of efficient arithmetic additive test pattern generators [logic test].	ETW	2003	DBLP DOI BibTeX RDF
1	Simone Borri, Magali Hage-Hassan, Patrick Girard 0001, Serge Pravossoudovitch, Arnaud Virazel	Defect-oriented dynamic fault models for embedded-SRAMs.	ETW	2003	DBLP DOI BibTeX RDF
1	Daniel Arumí-Delgado, Rosa Rodríguez-Montañés, José Pineda de Gyvez, Guido Gronthoud	Process-variability aware delay fault testing of ΔVT and weak-open defects.	ETW	2003	DBLP DOI BibTeX RDF
1	Fulvio Corno, Giovanni Squillero, Matteo Sonza Reorda	Code generation for functional validation of pipelined microprocessors.	ETW	2003	DBLP DOI BibTeX RDF
1	Octavian Petre, Hans G. Kerkhoff	Scan test strategy for asynchronous-synchronous interfaces [SoC testing].	ETW	2003	DBLP DOI BibTeX RDF
1	Marco Rona, Gunter Krampl, Fritz Raczkowski	Automating the device interface board modeling for virtual test.	ETW	2003	DBLP DOI BibTeX RDF
1	Marten Seth	RF ATE equipment benefit from advanced network analyzer technology.	ETW	2003	DBLP DOI BibTeX RDF
1		8th European Test Workshop, ETW 2003, Maastricht, The Netherlands, May 25-28, 2003	ETW	2003	DBLP BibTeX RDF
1	Said Hamdioui, Rob Wadsworth, John Delos Reyes, Ad J. van de Goor	Importance of dynamic faults for new SRAM technologies.	ETW	2003	DBLP DOI BibTeX RDF
1	Timm Ostermann, Bernd Deutschmann	Characterization of the EME of integrated circuits with the help of the IEC standard 61967 [electromagnetic emission].	ETW	2003	DBLP DOI BibTeX RDF
1	Anuja Sehgal, Aishwarya Dubey, Erik Jan Marinissen, Clemens Wouters, Harald P. E. Vranken, Krishnendu Chakrabarty	Yield analysis for repairable embedded memories.	ETW	2003	DBLP DOI BibTeX RDF
1	Bharath Seshadri, Irith Pomeranz, Sudhakar M. Reddy, Sandip Kundu	On path selection for delay fault testing considering operating conditions [logic IC testing].	ETW	2003	DBLP DOI BibTeX RDF
1	Erik Moerman, Sébastien Bocq, Johan Verfaillie	Debug architecture for system on chip taking full advantage of the test access port.	ETW	2003	DBLP DOI BibTeX RDF
1	Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker 0001	Modeling feedback bridging faults with non-zero resistance.	ETW	2003	DBLP DOI BibTeX RDF
1	Victor Avendaño, Víctor H. Champac, Joan Figueras	Signal integrity loss in bus lines due to open shielding defects.	ETW	2003	DBLP DOI BibTeX RDF
1	Julien Pouget, Erik Larsson, Zebo Peng, Marie-Lise Flottes, Bruno Rouzeyre	An efficient approach to SoC wrapper design, TAM configuration and test scheduling.	ETW	2003	DBLP DOI BibTeX RDF
1	Eric Liau, Doris Schmitt-Landsiedel	Automatic worst case pattern generation using neural networks & genetic algorithm for estimation of switching noise on power supply lines in CMOS circuits.	ETW	2003	DBLP DOI BibTeX RDF
1	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	Requirements for delay testing of look-up tables in SRAM-based FPGAs.	ETW	2003	DBLP DOI BibTeX RDF
1	Helmut Lang, Bhuwnesh Pande, Heiko Ahrens	Automating test program generation in STIL - expectations and experiences using IEEE 1450 [standard test interface language].	ETW	2003	DBLP DOI BibTeX RDF
1	Hans A. R. Manhaeve, Joseph S. Vaccaro, Loren Benecke, David Prystasz	A real world application used to implement a true IDDQ based test strategy (facts and figures).	ETW	2002	DBLP DOI BibTeX RDF
1	Ozgur Sinanoglu, Ismet Bayraktaroglu, Alex Orailoglu	Dynamic test data transformations for average and peak power reductions.	ETW	2002	DBLP DOI BibTeX RDF
1	Lars Schäfer, Rainer Dorsch, Hans-Joachim Wunderlich	RESPIN++ - deterministic embedded test.	ETW	2002	DBLP DOI BibTeX RDF
1	Sandeep Kumar Goel, Erik Jan Marinissen	A novel test time reduction algorithm for test architecture design for core-based system chips.	ETW	2002	DBLP DOI BibTeX RDF
1	Gregory S. Spirakis	Silicon technology advances and implications on test.	ETW	2002	DBLP DOI BibTeX RDF
1	Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell	A high accuracy triangle-wave signal generator for on-chip ADC testing.	ETW	2002	DBLP DOI BibTeX RDF
1	Srikanth Arekapudi, Fei Xin, Jinzheng Peng, Ian G. Harris	ATPG for timing-induced functional errors on trigger events in hardware-software systems.	ETW	2002	DBLP DOI BibTeX RDF
1	Yun Shao 0002, Sudhakar M. Reddy, Irith Pomeranz, Seiji Kajihara	On selecting testable paths in scan designs.	ETW	2002	DBLP DOI BibTeX RDF
1	Martin John Burbidge, Frédéric Poullet, Jim Tijou, Andrew M. D. Richardson	Investigations for minimum invasion digital only built-in "ramp" based test techniques for charge pump PLL's.	ETW	2002	DBLP DOI BibTeX RDF
1	Harald P. E. Vranken, Florian Meister, Hans-Joachim Wunderlich	Combining deterministic logic BIST with test point insertion.	ETW	2002	DBLP DOI BibTeX RDF
1	Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand	Modeling gate oxide short defects in CMOS minimum transistors.	ETW	2002	DBLP DOI BibTeX RDF
1	Xiao Liu 0010, Michael S. Hsiao, Sreejit Chakravarty, Paul J. Thadikaran	Novel ATPG algorithms for transition faults.	ETW	2002	DBLP DOI BibTeX RDF
1		7th European Test Workshop, ETW 2002, Corfu, Greece, May 26-29, 2002	ETW	2002	DBLP BibTeX RDF
1	Jonathan Bradford, Hartmut Delong, Ilia Polian, Bernd Becker 0001	Simulating realistic bridging and crosstalk faults in an industrial setting.	ETW	2002	DBLP DOI BibTeX RDF
1	Erik Larsson, Hideo Fujiwara	Power constrained preemptive TAM scheduling.	ETW	2002	DBLP DOI BibTeX RDF
1	Sandeep Kumar Goel, Bart Vermeulen	Data invalidation analysis for scan-based debug on multiple-clock system chips.	ETW	2002	DBLP DOI BibTeX RDF
1	Andrzej Hlawiczka, Michal Kopec	Dependable testing of compactor MISR: an imperceptible problem?	ETW	2002	DBLP DOI BibTeX RDF
1	Tiziana Margaria, Oliver Niese, Bernhard Steffen, Andrei Erochok	System level testing of virtual switch (re-)configuration over IP.	ETW	2002	DBLP DOI BibTeX RDF
1	D. C. L. (Erik) van Geest, Frans G. M. de Jong	System-level DFT for consumer products.	ETW	2001	DBLP DOI BibTeX RDF
1	Rainer Dorsch, Hans-Joachim Wunderlich	Reusing scan chains for test pattern decompression.	ETW	2001	DBLP DOI BibTeX RDF
1	Wilfried Daehn	Demodulation based testing of off-chip driver performance.	ETW	2001	DBLP DOI BibTeX RDF
1		6th European Test Workshop, ETW 2001, Stockholm, Sweden, May 29 - June 1, 2001	ETW	2001	DBLP BibTeX RDF
1	Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira 0001	RTL design validation, DFT and test pattern generation for high defects coverage.	ETW	2001	DBLP DOI BibTeX RDF
1	Oliver Niese, Tiziana Margaria, Andreas Hagerer, Bernhard Steffen, Georg Brune, Werner Goerigk, Hans-Dieter Ide	Automated regression testing of CTI-systems.	ETW	2001	DBLP DOI BibTeX RDF
1	Matthew Worsman, Mike W. T. Wong, Yim-Shu Lee	The use of equivalent fault analysis to improve static D.C. fault diagnosis - a potentiometric DAC case study.	ETW	2001	DBLP DOI BibTeX RDF
1	Jean-Michel Portal, Annie Pérez	Analyzing bridging faults impact on EEPROM cell array.	ETW	2001	DBLP DOI BibTeX RDF
1	Magnus Eckersand, Fredrik Franzon, Ken Filliter	Using at-speed BIST to test LVDS serializer/deserializer function.	ETW	2001	DBLP DOI BibTeX RDF
1	Liquan Fang, Guido Gronthoud, Hans G. Kerkhoff	Reducing analogue fault-simulation time by using high-level modelling in dotss for an industrial design.	ETW	2001	DBLP DOI BibTeX RDF
1	Maisaa Khalil, Chantal Robach	System level diagnosis - a comparison of two alternative approaches.	ETW	2001	DBLP DOI BibTeX RDF
1	Yukiya Miura, Shuichi Seno	Internal feedback bridging faults in combinational CMOS circuits: analysis and testing.	ETW	2001	DBLP DOI BibTeX RDF
1	Marco Rona, Gunter Krampl	A VHDL-based virtual test concept for pre-silicon test-program debug.	ETW	2001	DBLP DOI BibTeX RDF
1	Mohsen Nahvi, André Ivanov	A packet switching communication-based test access mechanism for system chips.	ETW	2001	DBLP DOI BibTeX RDF
1	René David, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch, Arnaud Virazel	On hardware generation of random single input change test sequences.	ETW	2001	DBLP DOI BibTeX RDF
1	Joonhwan Yi, John P. Hayes	A fault model for function and delay testing.	ETW	2001	DBLP DOI BibTeX RDF
1	V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff	An implementation for test-time reduction in VLIW transport-triggered architectures.	ETW	2001	DBLP DOI BibTeX RDF
1	Herman J. Vermaak, Hans G. Kerkhoff	Reducing the susceptibility of design-for-delay-testability structures to process- and application-induced variations.	ETW	2001	DBLP DOI BibTeX RDF
1	Daniela De Venuto, M. J. Ohletzo, Bruno Riccò	On-chip signal level evaluation for mixed-signal ICs using digital window comparators.	ETW	2001	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	On the use of multiple fault detection times in a method for built-in test pattern generation for synchronous sequential circuits.	ETW	2000	DBLP DOI BibTeX RDF
1	Marcelino B. Santos, Fernando M. Gonçalves, Isabel C. Teixeira, João Paulo Teixeira 0001	RTL-based functional test generation for high defects coverage in digital SOCs.	ETW	2000	DBLP DOI BibTeX RDF
1	Marco Boschini, Xiaoming Yu, Franco Fummi, Elizabeth M. Rudnick	Combining symbolic and genetic techniques for efficient sequential circuit test generation.	ETW	2000	DBLP DOI BibTeX RDF
1	Yiorgos Makris, Jamison Collins, Alex Orailoglu	How to avoid random walks in hierarchical test path identification.	ETW	2000	DBLP DOI BibTeX RDF
1	Bram Kruseman	Comparison of defect detection capabilities of current-based and voltage-based test methods.	ETW	2000	DBLP DOI BibTeX RDF
1	Anton Chichkov, Dirk Merlier, Peter Cox	Current testing procedure for deep submicron devices.	ETW	2000	DBLP DOI BibTeX RDF
1	Tomasz Garbolino, Andrzej Hlawiczka, Adam Kristof	Fast and low-area TPGs based on T-type flip-flops can be easily integrated to the scan path.	ETW	2000	DBLP DOI BibTeX RDF
1	Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante	CA-CSTP: a new BIST architecture for sequential circuits.	ETW	2000	DBLP DOI BibTeX RDF
1	Nuno Cardoso, Carlos Beltrán Almeida, José Carlos da Silva 0001	A system level boundary scan controller board for VME applications [to CERN experiments].	ETW	2000	DBLP DOI BibTeX RDF
1	Jörg E. Vollrath, Ulf Lederer, Thomas Hladschik	Compressed bit fail maps for memory fail pattern classification.	ETW	2000	DBLP DOI BibTeX RDF
1	David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre	A method for trading off test time, area and fault coverage in datapath BIST synthesis.	ETW	2000	DBLP DOI BibTeX RDF
1	Daniela De Venuto, Michael J. Ohletz, G. Matarrese	Static and dynamic on-chip test response evaluation using a two-mode comparator.	ETW	2000	DBLP DOI BibTeX RDF
1	Ismet Bayraktaroglu, Alex Orailoglu	Low cost concurrent test implementation for linear digital systems.	ETW	2000	DBLP DOI BibTeX RDF
1		5th European Test Workshop, ETW 2000, Cascais, Portugal, May 23-26, 2000	ETW	2000	DBLP BibTeX RDF
1	Masaru Sanada	Defect detection from visual abnormalities in manufacturing process using IDDQ.	ETW	2000	DBLP DOI BibTeX RDF
1	Monica Lobetti Bodoni, Alfredo Benso, Silvia Chiusano, Stefano Di Carlo, Giorgio Di Natale, Paolo Prinetto	An effective distributed BIST architecture for RAMs.	ETW	2000	DBLP DOI BibTeX RDF
1	Michel Renovell, Jean-Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian	Analyzing the test generation problem for an application-oriented test of FPGAs.	ETW	2000	DBLP DOI BibTeX RDF
1	Andrew Burdass, Gary Campbell, Richard Grisenthwaite, David Gwilt, Peter Harrod, Richard York	Microprocessor cores.	ETW	2000	DBLP DOI BibTeX RDF
1	Arnaud Virazel, René David, Patrick Girard 0001, Christian Landrault, Serge Pravossoudovitch	Delay fault testing: choosing between random SIC and random MIC test sequences.	ETW	2000	DBLP DOI BibTeX RDF
1	Florence Azaïs, Serge Bernard, Y. Betrand, Michel Renovell	Towards an ADC BIST scheme using the histogram test technique.	ETW	2000	DBLP DOI BibTeX RDF
1	Antoni Ferré, Joan Figueras	LEAP: An accurate defect-free IDDQ estimator.	ETW	2000	DBLP DOI BibTeX RDF
1	Piet Engelke, Bernd Becker 0001, Martin Keim	A parameterizable fault simulator for bridging faults.	ETW	2000	DBLP DOI BibTeX RDF
1	Han Speek, Hans G. Kerkhoff, Manoj Sachdev, Mansour Shashaani	Bridging the testing speed gap: design for delay testability.	ETW	2000	DBLP DOI BibTeX RDF
1	Sandip Kundu, Sanjay Sengupta, Rajesh Galivanche	Test challenges in nanometer technologies.	ETW	2000	DBLP DOI BibTeX RDF
1	Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno	System-level test bench generation in a co-design framework.	ETW	2000	DBLP DOI BibTeX RDF
1	Mykola Blyzniuk, T. Cibáková, Elena Gramatová, Wieslaw Kuzmicz, M. Lobur, Witold A. Pleskacz, Jaan Raik, Raimund Ubar	Hierarchical defect-oriented fault simulation for digital circuits.	ETW	2000	DBLP DOI BibTeX RDF
1	R. H. Beurze, Y. Xing, R. van Kleef, Ronald J. W. T. Tangelder, Nur Engin	Practical implementation of defect-oriented testing for a mixed-signal class-D amplifier.	ETW	1999	DBLP DOI BibTeX RDF
1	Marie-Lise Flottes, Christian Landrault, A. Petitqueux	Partial set for flip-flops based on state requirement for non-scan BIST scheme.	ETW	1999	DBLP DOI BibTeX RDF
1	Gustavo Ribeiro Alves, José Manuel Martins Ferreira	Using the BS register for capturing and storing n-bit sequences in real-time.	ETW	1999	DBLP DOI BibTeX RDF
1	Peter Muhmenthaler	Cost effective testing of systems on silicon: areas for optimization.	ETW	1999	DBLP DOI BibTeX RDF
1	Sheng-Jer Kuo, Chung Len Lee 0001, Soon-Jyh Chang, Jwu E. Chen	A DFT for semi-DC fault diagnosis for switched-capacitor circuits.	ETW	1999	DBLP DOI BibTeX RDF
1	Michel Renovell, Florence Azaïs, J.-C. Bodin, Yves Bertrand	Functional and structural testing of switched-current circuits.	ETW	1999	DBLP DOI BibTeX RDF
1	Salvador Mir, Benoît Charlot, Bernard Courtois	Extending fault-based testing to microelectromechanical systems.	ETW	1999	DBLP DOI BibTeX RDF
1	Harald P. E. Vranken	Debug facilities in the TriMedia CPU64 architecture.	ETW	1999	DBLP DOI BibTeX RDF
1	Irith Pomeranz, Sudhakar M. Reddy	On avoiding undetectable faults during test generation.	ETW	1999	DBLP DOI BibTeX RDF
1	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	Test configuration minimization for the logic cells of SRAM-based FPGAs: a case study.	ETW	1999	DBLP DOI BibTeX RDF
1	Toshiyuki Maeda, Kozo Kinoshita	Compaction of IDDQ test sequence using reassignment method.	ETW	1999	DBLP DOI BibTeX RDF
1	Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante	A new BIST architecture for low power circuits.	ETW	1999	DBLP DOI BibTeX RDF
1	Jaan Raik, Raimund Ubar	High-level path activation technique to speed up sequential circuit test generation.	ETW	1999	DBLP DOI BibTeX RDF

Publications at "ETW"( http://dblp.L3S.de/Venues/ETW )