Search results for "MOSFET"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
25	Suet Fong Tin, Ashraf A. Osman, Kartikeya Mayaram	Comments on "A small-signal MOSFET model for radio frequency IC applications".	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1998	DBLP DOI BibTeX RDF
25	Xinghai Tang, Vivek De, James D. Meindl	Intrinsic MOSFET parameter fluctuations due to random dopant placement.	IEEE Trans. Very Large Scale Integr. Syst.	1997	DBLP DOI BibTeX RDF
25	Ming-Jer Chen, Jib-Shin Ho	A three-parameters-only MOSFET subthreshold current CAD model considering back-gate bias and process variation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
25	Mitiko Miura-Mattausch, Ute Feldmann, Alexander Rahm, Michael Bollu, Dominique Savignac	Unified complete MOSFET model for analysis of digital and analog circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1996	DBLP DOI BibTeX RDF
25	Abhijit Chatterjee, Charles F. Machala III, Ping Yang 0001	A submicron DC MOSFET model for simulation of analog circuits.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
25	Mark G. Graham, John J. Paulos, Douglas W. Nychka	Template-based MOSFET device model.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1995	DBLP DOI BibTeX RDF
25	Rupert Howes, William Redman-White, Ken G. Nichols, Peter J. Mole, Michael J. Robinson, Simon Bird	An SOS MOSFET model based on calculation of the surface potential.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
25	Mitiko Miura-Mattausch, Ute Feldmann, Alexander Rahm, Michael Bollu, Dominique Savignac	Unified complete MOSFET model for analysis of digital and analog circuits.	ICCAD	1994	DBLP DOI BibTeX RDF
25	Yu Hen Hu, ShaoWei Pan	SaPOSM: an optimization method applied to parameter extraction of MOSFET models.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
25	Victor Martin Agostinelli Jr., Gregory Munson Yeric, A. F. Tasch Jr.	Universal MOSFET hole mobility degradation models for circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
25	Hiroyoshi Tanimoto, Naoyuki Shigyo	Discretization error in MOSFET device simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
25	James A. Power, W. A. Lane	An enhanced SPICE MOSFET model suitable for analog applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
25	Hong June Park, Ping Keung Ko, Chenming Hu	A non-quasi-static MOSFET model for SPICE-AC analysis.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
25	A. R. Boothroyd, Stan W. Tarasewicz, Cezary Slaby	MISNAN-a physically based continuous MOSFET model for CAD applications.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
25	Martin Thurner, Philipp Lindorfer, Siegfried Selberherr	Numerical treatment of nonrectangular field-oxide for 3-D MOSFET simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1990	DBLP DOI BibTeX RDF
25	Lee-Sup Kim, Robert W. Dutton	Modeling of the distributed gate RC effect in MOSFET's.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
25	Jerry G. Fossum, Surya Veeraraghavan, Dan Fitzpatrick	Model selection for SOI MOSFET circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
22	Giovanni Stracquadanio, Concetta Drago, Vittorio Romano, Giuseppe Nicosia	Multi-objective optimization of doping profile in semiconductor design.	GECCO	2010	DBLP DOI BibTeX RDF	semiconductor design, multi-objective optimization, electronic design automation
22	Ken Ueno, Tetsuya Hirose, Tetsuya Asai, Yoshihito Amemiya	A 300 nW, 7 ppm/degreeC CMOS voltage reference circuit based on subthreshold MOSFETs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
22	Samed Maltabas, Martin Margala, Ugur Çilingiroglu	Varicap threshold logic.	ACM Great Lakes Symposium on VLSI	2009	DBLP DOI BibTeX RDF	minnick tl network, variable capacitance, threshold logic, parallel counter
22	Mian Dong, Lin Zhong 0001	Logic Synthesis with Nanowire Crossbar: Reality Check and Standard Cell-based Integration.	DATE	2008	DBLP DOI BibTeX RDF
22	Jader A. De Lima, Wallace A. Pimenta	A current limiter for DC/DC regulators with internal compensation for process and temperature.	SBCCI	2008	DBLP DOI BibTeX RDF	DC/DC converter, LDO, PVT compensation, current limitation, switcher
22	Hamilton Klimach, Márcio C. Schneider, Carlos Galup-Montoro	An M-2M digital-to-analog converter design methodology based on a physical mismatch model.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Jader A. De Lima, Wallace A. Pimenta	A current limiter for LDO regulators with internal compensation for process and temperature variations.	ISCAS	2008	DBLP DOI BibTeX RDF
22	Jyotirmoy Ghosh, Siddhartha Mukhopadhyay, Amit Patra, Barry Culpepper, Tawen Mei	A New Approach for Estimation of On-Resistance and Current Distribution in Power Array Layouts.	VLSI Design	2008	DBLP DOI BibTeX RDF
22	Hsiao-Chun Wu, Sameer R. Herlekar, M. Saquib, Ashok Srivastava	Hot Carrier Effects in Wireless Communication Systems Built on Short-Channel MOSFETs.	IEEE Trans. Wirel. Commun.	2007	DBLP DOI BibTeX RDF
22	Bipul C. Paul, Shinobu Fujita, Masaki Okajima, Thomas Lee	Prospect of ballistic CNFET in high performance applications: Modeling and analysis.	ACM J. Emerg. Technol. Comput. Syst.	2007	DBLP DOI BibTeX RDF	Ballistic carbon nanotube FET (CNFET), circuit compatible model, parasitic capacitance, process variability, circuit performance
22	Il Song Han	Membership Function Circuit for Neural/Fuzzy Hardware of Analog-Mixed Operation Based on the Programmable Conductance.	FUZZ-IEEE	2007	DBLP DOI BibTeX RDF
22	Reza Navid, Thomas H. Lee, Robert W. Dutton	A Circuit-Based Noise Parameter Extraction Technique for MOSFETs.	ISCAS	2007	DBLP DOI BibTeX RDF
22	Erik J. Mentze, Herbert L. Hess, Kevin M. Buck, T. G. Windley	A Scalable High-Voltage Output Driver for Low-Voltage CMOS Technologies.	IEEE Trans. Very Large Scale Integr. Syst.	2006	DBLP DOI BibTeX RDF
22	Mutlu Avci, Tülay Yildirim	Neural Network Based MOS Transistor Geometry Decision for TSMC 0.18µ Process Technology.	International Conference on Computational Science (4)	2006	DBLP DOI BibTeX RDF
22	Shih-Ching Lo, Shao-Ming Yu	A Quantum Hydrodynamic Simulation of Strained Nanoscale VLSI Device.	International Conference on Computational Science (1)	2006	DBLP DOI BibTeX RDF
22	Arijit Raychowdhury, Xuanyao Fong, Qikai Chen, Kaushik Roy 0001	Analysis of super cut-off transistors for ultralow power digital logic circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	carbon nanotube FETs, tunneling transistors
22	Nasser Talebbeydokhti, Pavan Kumar Hanumolu, Peter Kurahashi, Un-Ku Moon	Constant transconductance bias circuit with an on-chip resistor.	ISCAS	2006	DBLP DOI BibTeX RDF
22	Yajie Chen, Steve Hall, Liam McDaid, Octavian Buiu, Peter M. Kelly	On the Design of a Low Power Compact Spiking Neuron Cell Based on Charge-Coupled Synapses.	IJCNN	2006	DBLP DOI BibTeX RDF
22	Victor Bourenkov, Kevin G. McCarthy, Alan Mathewson	MOS table models for circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
22	Gerard Villar, Eduard Alarcón, Jordi Madrenas, Francesc Guinjoan, Alberto Poveda	Energy optimization of tapered buffers for CMOS on-chip switching power converters.	ISCAS (5)	2005	DBLP DOI BibTeX RDF
22	Jin He 0003, Jane Xi, Mansun Chan, Hui Wan 0003, Mohan V. Dunga, Babak Heydari, Ali M. Niknejad, Chenming Hu	Charge-Based Core and the Model Architecture of BSIM5.	ISQED	2005	DBLP DOI BibTeX RDF
22	Yanjie Wang, Yanbin Wang, Garry Tarr, Kris Iniewski	A Temperature, Supply Voltage Compensated Floating-Gate MOS Dosimeter Using V_TH Extractor.	IWSOC	2005	DBLP DOI BibTeX RDF
22	Shanthi Pavan	A fixed transconductance bias technique for CMOS analog integrated circuits.	ISCAS (1)	2004	DBLP DOI BibTeX RDF
22	Ram Suryanarayan, Anubhav Gupta, Travis N. Blalock	A slew rate enhancement technique for operational amplifiers based on a tunable active Gm-based capacitance multiplication circuit.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	opamp, feedback, CMOS, compensation, operational amplifier, slew rate
22	J. Veerendra Kumar, K. Radhakrishna Rao	A Low-Voltage Low Power CMOS Companding Filter.	VLSI Design	2003	DBLP DOI BibTeX RDF
22	Sunay Shah, Steve Collins	A temperature independent trimmable current source.	ISCAS (1)	2002	DBLP DOI BibTeX RDF
22	Volney C. Vincence, Carlos Galup-Montoro, Márcio C. Schneider	A low-voltage CMOS class-AB operational amplifier.	ISCAS (3)	2002	DBLP DOI BibTeX RDF
22	Azeez J. Bhavnagarwala, Blanca Austin, Keith A. Bowman, James D. Meindl	A minimum total power methodology for projecting limits on CMOS GSI.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
22	Hongchin Lin, Kai-Hsun Chang, Shyh-Chyi Wong	Novel high positive and negative pumping circuits for low supply voltage.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
22	Hanspeter Schmid, George S. Moschytz	A tunable, video-frequency, low-power, single-amplifier biquadratic filter in CMOS.	ISCAS (2)	1999	DBLP DOI BibTeX RDF
22	James D. Meindl	XXI Century Gigascale Integration (GSI) : The Interconnect Problem.	ARVLSI	1999	DBLP DOI BibTeX RDF
22	Abdolreza Nabavi-Lishi, Nicholas C. Rumin	Inverter models of CMOS gates for supply current and delay evaluation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1994	DBLP DOI BibTeX RDF
22	Masayoshi Shirahata, Hiromi Kusano, Norihiko Kotani, Shigeru Kusanoki, Yoichi Akasaka	A mobility model including the screening effect in MOS inversion layer.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
22	Hiroo Masuda, Jun'ichi Mano, Ryuichi Ikematsu, Hitoshi Sugihara, Yukio Aoki	A submicrometer MOS transistor I-V model for circuit simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1991	DBLP DOI BibTeX RDF
22	Chang G. Hwang, Robert W. Dutton	Improved physical modeling of submicron MOSFETs based on parameter extraction using 2-D simulation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
22	Alessandro Forghieri, Roberto Guerrieri, Paolo Ciampolini, Antonio Gnudi, Massimo Rudan, Giorgio Baccarani	A new discretization strategy of the semiconductor equations comprising momentum and energy balance.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1988	DBLP DOI BibTeX RDF
21	Binjie Cheng, Daryoosh Dideban, Negin Moezi, Campbell Millar, Gareth Roy, Xingsheng Wang, Scott Roy, Asen Asenov	Statistical-Variability Compact-Modeling Strategies for BSIM4 and PSP.	IEEE Des. Test Comput.	2010	DBLP DOI BibTeX RDF	statistical variability, statistical compact modeling, design and test, MOSFET, mismatch
21	Tuck-Boon Chan, Rani S. Ghaida, Puneet Gupta 0001	Electrical Modeling of Lithographic Imperfections.	VLSI Design	2010	DBLP DOI BibTeX RDF	lithographic imperfections, non-rectangular, transistor, mosfet
21	Subhas Chandra Mukhopadhyay, Gourab Sen Gupta, Ray Yueh-Min Huang	A Combined Platform of Wireless Sensors and Actuators Based on Embedded Controller.	SUTC	2008	DBLP DOI BibTeX RDF	Wireless sensors and actuators, Fireworks, Embedded Microcontroller, Detonation, Electric-Match, Wireless, MOSFET
21	Zhiyu Liu, Sherif A. Tawfik, Volkan Kursun	Statistical Data Stability and Leakage Evaluation of FinFET SRAM Cells with Dynamic Threshold Voltage Tuning under Process Parameter Fluctuations.	ISQED	2008	DBLP DOI BibTeX RDF	static noise margin distribution, robust operation, active power, standby power distribution, double gate MOSFET, process variations, Cache memory
21	Alessandro Girardi, Fernando da Rocha Paixão Cortes, Eduardo Conrad Jr., Sergio Bampi	T-shaped association of transistors: modeling of multiple channel lengths and regular associations.	SBCCI	2005	DBLP DOI BibTeX RDF	associations of transistors, modeling, analog design, MOSFET
21	Edgar Mauricio Camacho-Galeano, Carlos Galup-Montoro, Márcio C. Schneider	An ultra-low-power self-biased current reference.	SBCCI	2004	DBLP DOI BibTeX RDF	inversion level, self-cascode MOSFET, design methodology, low-voltage, ultra-low-power, current reference
21	Hamilton Klimach, Alfredo Arnaud, Márcio C. Schneider, Carlos Galup-Montoro	Characterization of MOS transistor current mismatch.	SBCCI	2004	DBLP DOI BibTeX RDF	matching, analog design, MOSFET, mismatch, compact models
21	Keunwoo Kim, Rajiv V. Joshi, Ching-Te Chuang	Strained-si devices and circuits for low-power applications.	ISLPED	2003	DBLP DOI BibTeX RDF	band offset, strained-Si MOSFET, mobility, SOI, SiGe
21	Christoph Wasshuber	Recent advances and future prospects in single-electronics.	DAC	2003	DBLP DOI BibTeX RDF	random background charge, single-electron logic, SET, MOSFET
21	Yiming Li 0005, S. M. Sze, Tien-Sheng Chao	A Practical Implementation of Parallel Dynamic Load Balancing for Adaptive Computing in VLSI Device Simulation.	Eng. Comput.	2002	DBLP DOI BibTeX RDF	DTMOS, Dynamic domain decomposition, Parallel I-V points calculation, VLSI device simulation, Load balancing, MOSFET, Linux cluster
21	Kaveh Shakeri, James D. Meindl	Temperature Variable Supply Voltage for Power Reduction.	ISVLSI	2002	DBLP DOI BibTeX RDF	CMOS, Temperature, Power reduction, Dynamic Power, MOSFET, Static Power
21	John P. Denton, Sang Woo Pae, Gerold W. Neudeck	Vertical integration of submicron MOSFETs in two separate layers of SOI islands formed by silicon epitaxial lateral overgrowth.	ACM Great Lakes Symposium on VLSI	2001	DBLP DOI BibTeX RDF	SOI MOSFET, selective epitaxial growth, silicon, silicon on insulator, thin film SOI, three dimensional circuits
21	Noriaki Muranaka, Shigenobu Arai, Shigeru Imanishi, D. Michael Miller	A Ternary Systolic Product-Sum Circuit for GF(3m) using Neuron MOSFETs.	ISMVL	1996	DBLP DOI BibTeX RDF	neuron MOSFET, product sum computation, systolic array, Ternary logic
14	Jae-Sub Ko, Cheol Woong Choi, Woongkul Lee, Dae-Kyong Kim	Novel Phase Shift Angle Compensation Method of DAB Converter Considering Parasitic Capacitance of SiC MOSFET.	IEEE Access	2024	DBLP DOI BibTeX RDF
14	Vibhav Pandey, Sougata Nayak, Kamalesh Hatua, Subhashish Bhattacharya	A PCB-Incorporated Inductor Based Filter Design Solution for Differential Mode Noise of 3-Phase SiC-MOSFET Based VSI.	IEEE Access	2024	DBLP DOI BibTeX RDF
14	Haihua Wang, Zekun Zhao, Qiumeng Chen, Yu-Long Jiang, Jing Wan	Back-Gate Fully Depleted Silicon-on-Insulator P-Channel Schottky Barrier MOSFET With Ultrahigh Voltage Sensitivity for Label-Free Virus RNA Detection.	IEEE Trans. Instrum. Meas.	2024	DBLP DOI BibTeX RDF
14	Mohammad Radpour, Leonid Belostotski	Induced Back-Gate Noise in FDSOI MOSFET.	IEEE Trans. Circuits Syst. II Express Briefs	2024	DBLP DOI BibTeX RDF
14	Lei Zhou, Chune Wang, Xiaozhong Chen	A GHz-level memristor emulator with only MOSFET.	Int. J. Circuit Theory Appl.	2024	DBLP DOI BibTeX RDF
14	Soomin Kim, Seongjae Cho	Effects of Misaligned Gate Lapping Over the Channel on Performances of Ultra-Thin Vertical-Pillar MOSFET.	ICEIC	2024	DBLP DOI BibTeX RDF
14	Victor R. R. de Oliveira, Mirella M. de O. Carneiro, Carlos Fernando T. Soares, Fernanda D. V. R. Oliveira, José Gabriel R. C. Gomes	MOSFET-C Filter Design using Genetic Algorithm with Restricted Mutation for Gate Multiplicity.	LASCAS	2024	DBLP DOI BibTeX RDF
14	Monika Kumari, Manodipan Sahoo	Sensitivity Enhancement of TMD MOSFET-Based Biosensor by Modeling and Optimization of Back Gate Parameters.	VLSID	2024	DBLP DOI BibTeX RDF
14	Alba Ordonez Rodriguez, Fabien Gilibert, Francois Paolini, Pascal Urard, Roberto Guizzetti, John Samuel 0003, Remy Cellier, Lioua Labrak, Bastien Deveautour	Artificial neural network-based solution for PSP MOSFET model card extraction.	VLSID	2024	DBLP DOI BibTeX RDF
14	Xin Lei, Xingguo Gao, Jun Deng, Zhou Shu, Fang Tang	A 15-V Tolerant and Radiation-Hardened MOSFET Driver With Positive and Negative References.	IEEE Trans. Aerosp. Electron. Syst.	2023	DBLP DOI BibTeX RDF
14	Elliot O. Omoru, Viranjay M. Srivastava	Switching Speed Analysis of MOSFET-Based Absorber Integrated Antenna for 5G/WiMAX/WLAN.	J. Commun.	2023	DBLP DOI BibTeX RDF
14	Sneha Narasimhan, Ajit Kanale, Subhashish Bhattacharya, B. Jayant Baliga	Performance Evaluation of 3.3 kV SiC MOSFET and Schottky Diode Based Reverse Voltage Blocking Switch for Medium Voltage Current Source Inverter Application.	IEEE Access	2023	DBLP DOI BibTeX RDF
14	Nishant Anurag, Shabari Nath	Switching Investigation of SiC MOSFET Based 4-Quadrant Switch.	IEEE Access	2023	DBLP DOI BibTeX RDF
14	Yufang Lu, Jiecheng Ai, Luyang Wei, Kai Meng, Chengfu Han	A Novel Current Limiting Protection Control Strategy by Power MOSFET Thermal Management for Solid-State Power Controller.	IEEE Access	2023	DBLP DOI BibTeX RDF
14	Dayana A. Pino-Monroy, Patrick Scheer, Mohamed Khalil Bouchoucha, Carlos Galup-Montoro, Manuel J. Barragán, Philippe Cathelin, Jean-Michel Fournier, Andreia Cathelin, Sylvain Bourdel	Corrections to "Design-Oriented All-Regime All-Region 7-Parameter Short-Channel MOSFET Model Based on Inversion Charge".	IEEE Access	2023	DBLP DOI BibTeX RDF
14	Karimeldeen Mohamed, Khaled Y. Yasseen, Boris Murmann, Hesham Omran	Capturing Layout Dependent Effects in MOSFET Circuit Sizing Using Precomputed Lookup Tables.	IEEE Access	2023	DBLP DOI BibTeX RDF
14	Nilesh Kumar Jaiswal, V. N. Ramakrishnan	An Optimized Vertical GaN Parallel Split Gate Trench MOSFET Device Structure for Improved Switching Performance.	IEEE Access	2023	DBLP DOI BibTeX RDF
14	Hiroshi Oka, Takumi Inaba, Shunsuke Shitakata, Kimihiko Kato, Shota Iizuka, Hidehiro Asai, Hiroshi Fuketa, Takahiro Mori	Origin of Low-Frequency Noise in Si n-MOSFET at Cryogenic Temperatures: The Effect of Interface Quality.	IEEE Access	2023	DBLP DOI BibTeX RDF
14	Donglin Xu, Ming Yang 0006, Kaiyuan Hu, Dianguo Xu 0001	A Transistor-Based Assist Gate Driver of SiC MOSFET for Crosstalk Suppression in a Phase-Leg Configuration.	IEEE Access	2023	DBLP DOI BibTeX RDF
14	Yusuke Kikuchi, Jun Matsusue, Fuma Yamada, Takafumi Okuda, Takashi Nakamura	Repetitive Partial Discharge Phenomena on Electrical Motor Coil Windings Under High-Repetition Nanosecond Pulsed Voltages Driven by SiC MOSFET Inverter.	IEEE Access	2023	DBLP DOI BibTeX RDF
14	Haiguo Li, Zihan Gao, Fei Wang 0045, Yiwei Ma, Yu Su, Dingrui Li, Pengfei Yao, Shiqi Ji, Zhe Yang, Ruirui Chen 0003	Design, Development, and Testing of a Flexible Combined Heat and Power (F-CHP) System With 10-kV SiC MOSFET-Based Power Conditioning System (PCS) Converter.	IEEE Access	2023	DBLP DOI BibTeX RDF
14	Fatma A. Khera, Serhiy Bozhko, Pat Wheeler	Design Analysis of SiC-MOSFET Based Bidirectional SSPC for Aircraft High Voltage DC Distribution Network.	IEEE Access	2023	DBLP DOI BibTeX RDF
14	Jacek Rabkowski, Mariusz Zdanowski, Rafal Kopacz, Fernando Gonzalez-Hernando, Irma Villar, Uxue Larrañaga	From the Measurement of COSS-VDS Characteristic to the Estimation of the Channel Current in Medium Voltage SiC MOSFET Power Modules.	IEEE Trans. Instrum. Meas.	2023	DBLP DOI BibTeX RDF
14	Hocine Boulharts, Rudolf Fehringer, David Lechat	Active dv/dt filter with SiC MOSFET - interlock-delay effect on the overvoltage at motor terminals.	Elektrotech. Informationstechnik	2023	DBLP DOI BibTeX RDF
14	Jianwen Cao, Ze-kun Zhou, Yue Shi 0001, Bo Zhang 0027	On-Chip Active Turn-Off Driving Technique to Prevent Channel Current From Disappearing Prematurely in SiC MOSFET's Applications.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
14	Valentyn Solomko, Semen Syroiezhin, Robert Weigel	High-Voltage Analog Switch Inspired by Stacked MOSFET-Based RF Switches.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
14	Faisal Bashir, Furqan Zahoor, Ali S. Alzahrani, Abdul Raouf Khan	A Single Schottky Barrier MOSFET-Based Leaky Integrate and Fire Neuron for Neuromorphic Computing.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
14	Jongmin Park, Young Kim, Yosep Cho, Jinwook Burm	Multi-Stage Reconfigurable RF-DC Converter With Deep-n-Well Biasing Using Body-Isolated MOSFET in 180-nm BCDMOS Process.	IEEE Trans. Circuits Syst. II Express Briefs	2023	DBLP DOI BibTeX RDF
14	Hasan Serdar	MOSFET-C Shadow Filters Based on FDCCII for Cognitive Communications.	J. Circuits Syst. Comput.	2023	DBLP DOI BibTeX RDF
14	JiaHao Wei, Haihua Wang, Tian Zhao, Yu-Long Jiang, Jing Wan	A New Compact MOSFET Model Based on Artificial Neural Network With Unique Data Preprocessing and Sampling Techniques.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
14	Kun Wu, Nanlin Guo, Fei Li, Nengyong Zhu, Jun Tao 0001, Xin Li 0001	Efficient Statistical Parameter Extraction for Modeling MOSFET Mismatch.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
14	Girish Pahwa, Ayushi Sharma, Ravi Goel, Garima Gill, Harshit Agarwal, Yogesh Singh Chauhan, Chenming Hu	Robust Compact Model of High-Voltage MOSFET's Drift Region.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2023	DBLP DOI BibTeX RDF
14	Madan Mohan Tripathi, Ajay Kumar 0004	Small-Signal Modeling of GaN-BTG MOSFET for Wireless Applications.	Wirel. Pers. Commun.	2023	DBLP DOI BibTeX RDF
14	Roshan Sharma, Akash Patnaik, Pankaj Sharma	Impact of doping concentration and recess depth to achieve enhancement mode operation in β-Ga2O3 MOSFET.	Microelectron. J.	2023	DBLP DOI BibTeX RDF