Search results for "Arrays"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
27	Sy-Yen Kuo, W. Kent Fuchs	Efficient spare allocation in reconfigurable arrays.	DAC	1986	DBLP DOI BibTeX RDF
27	P. Geoffrey Lowney	Carrier Arrays: An Idiom-Preserving Extension to APL.	POPL	1981	DBLP DOI BibTeX RDF
27	Arnold L. Rosenberg, Larry J. Stockmeyer	Hashing Schemes for Extendible Arrays.	J. ACM	1977	DBLP DOI BibTeX RDF
27	Arnold L. Rosenberg	Allocating Storage for Extendible Arrays.	J. ACM	1974	DBLP DOI BibTeX RDF
25	Richard L. W. Brown	Interest made simple with arrays.	APL	2000	DBLP DOI BibTeX RDF	APL
25	Adrian Vrouwenvelder, Keith R. Allen, Roy P. Pargas	Translating systolic arrays into instruction systolic arrays.	ACM Conference on Computer Science	1988	DBLP DOI BibTeX RDF	SAGE
25	Marc Levoy, Billy Chen, Vaibhav Vaish, Mark Horowitz, Ian McDowall, Mark T. Bolas	Synthetic aperture confocal imaging.	ACM Trans. Graph.	2004	DBLP DOI BibTeX RDF	camera arrays, coded aperture, confocal microscopy, projector arrays, shaped illumination, Light fields, synthetic aperture
25	Ivana Mikic, Kohsia S. Huang, Mohan M. Trivedi	Activity Monitoring and Summarization for an Intelligent Meeting Room.	Workshop on Human Motion	2000	DBLP DOI BibTeX RDF	microphones, intelligent meeting room, multimodal sensor network, static cameras, interesting events, multi-person interactions, past-event reviews, active network control procedures, real-time system, summarization, active vision, cameras, arrays, intelligent environments, office automation, activity monitoring, microphone arrays, system specifications, integration framework, computerised monitoring, image processing equipment, office environment, active cameras
25	William L. Freking, Keshab K. Parhi	Performance-Scalable Array Architectures for Modular Multiplication.	ASAP	2000	DBLP DOI BibTeX RDF	high-radix algorithms, cylindrical arrays, folding transformation, systolic arrays, modular multiplication, scalable architectures
25	Yoshinori Yamaguchi, Kenji Toda, Kenji Nishida, Eiichi Takahashi	CODA-R: a reconfigurable testbed for real-time parallel computation.	RTCSA	1997	DBLP DOI BibTeX RDF	CODA-R, reconfigurable testbed, real-time parallel computation, reconfigurable field programmable gate arrays, total execution time, prototype reconfigurable real-time parallel system, real-time parallel architecture, field programmable gate arrays, real-time system, processing elements, computing engine
25	Mostafa I. H. Abd-El-Barr, Muhammad Nayyar Hasan	New MVL-PLA Structures Based on Current-Mode CMOS Technology.	ISMVL	1996	DBLP DOI BibTeX RDF	MVL-PLA structures, current-mode CMOS technology, PLA structures, min, tsum, constants, r-valued one-variable functions, type-C PLA, type-A PLA, type-B PLA, cyclic generator blocks, programmable logic arrays, programmable logic arrays, CMOS logic circuits, cycle, multivalued logic circuits, multivalued logic circuits, current-mode logic
25	István Vassányi, István Erényi	Implementation of Processor Cells for Array Algorithms on FPGAs.	EUROMICRO	1996	DBLP DOI BibTeX RDF	array algorithms, processor cells, fine-grain array architectures, cellular image processing algorithms, placement-routing tool, field programmable gate arrays, FPGA, processor arrays
25	Minesh I. Patel, N. Ranganathan	A VLSI System Architecture For Real-Time Intelligent Decision Making.	ASAP	1996	DBLP DOI BibTeX RDF	VLSI system architecture, real-time intelligent decision making, backpropagation based neural network, rule based fuzzy expert system, real-time decision, CMOS VLSI chip, real-time systems, VLSI, expert systems, systolic arrays, neural nets, backpropagation, CMOS integrated circuits, adaptive learning, linear systolic arrays
25	Mandyam-Komar Srinivas, Vishwani D. Agrawal, Michael L. Bushnell	Functional test generation for path delay faults.	Asian Test Symposium	1995	DBLP DOI BibTeX RDF	growth faults, disappearance faults, robustly detectable path delay faults, two-level circuit, algebraic transformations, generated vectors, algebraically factored multilevel circuit, scan/hold versions, ISCAS89 circuits, fault diagnosis, logic testing, delays, timings, fault coverages, fault location, programmable logic arrays, programmable logic arrays, PLA, multivalued logic, path delay faults, functional test generation, stuck faults
25	Joseph L. Ganley, James P. Cohoon	Thumbnail rectilinear Steiner trees.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	full-set decomposition algorithm, minimum-length set, thumbnail rectilinear Steiner tree problem, VLSI placement algorithms, geometric partitioning, field programmable gate arrays, field-programmable gate arrays, VLSI, dynamic programming, network topology, logic CAD, trees (mathematics), network routing, circuit layout CAD, global routing, line segments
25	Jae-Tack Yoo, Erik Brunvand, Kent F. Smith	Automatic rapid prototyping of semi-custom VLSI circuits using Actel FPGAs.	Great Lakes Symposium on VLSI	1995	DBLP DOI BibTeX RDF	automatic rapid prototyping, semicustom VLSI circuits, Actel FPGAs, cell-matrix based environment, synchronous pipelined version, asynchronous pipelined version, field programmable gate arrays, field programmable gate arrays, VLSI, logic CAD, integrated circuit design, CMOS logic circuits, circuit CAD, array multiplier, CMOS IC
25	Oscar H. Ibarra, Stephen M. Sohn	On Mapping Systolic Algorithms onto the Hypercube.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	parallel to parallel mappings, time-space graph, one way linear systolic array, systolic array algorithms, fixed-size hypercube architecture, two-dimensional systolic arrays, 64-node NCUBE/7 MIMD hypercube machine, shuffle scheduling problem, finite impulse response filtering, linear context-free language recognition, Boolean transitive closure, performance evaluation, parallel algorithms, computational complexity, parallel computers, parallel architectures, hypercube, matrix multiplication, interprocessor communication, cellular arrays, systolic algorithms, local computation
24	Jia Di, Parag K. Lala	Cellular Array-based Delay-insensitive Asynchronous Circuits Design and Test for Nanocomputing Systems.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	Reed-Muller expression, nanoscale circuit, layout, stuck-at fault, cellular arrays, delay-insensitive circuit
24	Brett W. Bader, Tamara G. Kolda	Algorithm 862: MATLAB tensor classes for fast algorithm prototyping.	ACM Trans. Math. Softw.	2006	DBLP DOI BibTeX RDF	Higher-order tensors, N-way arrays, MATLAB, multilinear algebra
24	Chun-Yuan Lin, Jen-Shiuh Liu, Yeh-Ching Chung	Efficient Representation Scheme for Multidimensional Array Operations.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	extended Karnaugh map representation, traditional matrix representation, data structure, multidimensional arrays, array operations
24	Sek M. Chai, D. Scott Wills	Systolic Opportunities for Multidimensional Data Streams.	IEEE Trans. Parallel Distributed Syst.	2002	DBLP DOI BibTeX RDF	area I/O, design and performance evaluation, systolic arrays, parallel computer architecture
24	Alessandro Armando, Silvio Ranise, Michaël Rusinowitch	Uniform Derivation of Decision Procedures by Superposition.	CSL	2001	DBLP DOI BibTeX RDF	Arrays with Extensionality, Term Rewriting, Decision Procedures, Homomorphism, Automated Deduction, Lists, Superposition, Equational Logic
24	V. B. Fyodorov	Bit-Parallel Selfrouting Optoelectronic Switching Fabrics for Massively Parallel Wide-Format Data Processing: Principle and Optical Architecture.	ISPAN	1997	DBLP DOI BibTeX RDF	Free space optical interconnections, Completely connected networks, Smart pixel arrays, VCSEL technology
24	Issei Numata, Susumu Horiguchi	Efficient reconfiguration scheme for mesh-connected network: the recursive shift approach.	ISPAN	1996	DBLP DOI BibTeX RDF	mesh-connected network, recursive shift, faulty processing elements, mesh arrays, redundant processing elements, fault tolerance, parallel architectures, fault tolerant computing, multiprocessor interconnection networks, reconfigurable architectures, massively parallel system, reconfiguration scheme
24	Chun-Lin Liu, P. P. Vaidyanathan	Super nested arrays: Sparse arrays with less mutual coupling than nested arrays.	ICASSP	2016	DBLP DOI BibTeX RDF
24	Christian Wimmer, Hanspeter Mössenböck	Automatic array inlining in java virtual machines.	CGO	2008	DBLP DOI BibTeX RDF	array inlining, object inlining, java, optimization, performance, garbage collection, just-in-time compilation
24	James K. Beard	Costas array generator polynomials in finite fields.	CISS	2008	DBLP DOI BibTeX RDF
24	Brent Gold, Michael J. Roan, Marty Johnson, Elizabeth Hoppe	Source localization performance of a multi-array network under sensor orientation and position uncertainty.	CISS	2008	DBLP DOI BibTeX RDF
24	Chunhui Zhang, Fadi J. Kurdahi	Reducing Off-Chip Memory Access via Stream-Conscious Tiling on Multimedia Applications.	Int. J. Parallel Program.	2007	DBLP DOI BibTeX RDF	low power, DSP, memory hierarchy, tiling, data locality, iteration space
24	Robert Bernecky	Shape cliques.	ACM SIGAPL APL Quote Quad	2007	DBLP DOI BibTeX RDF
24	Hongwei Zhu 0001, Ilie I. Luican, Florin Balasa	Mapping multi-dimensional signals into hierarchical memory organizations.	DATE	2007	DBLP DOI BibTeX RDF
24	Johan Ditmar, Steve McKeever	Array Synthesis in SystemC Hardware Compilation.	FPL	2007	DBLP DOI BibTeX RDF
24	Marco A. Panduro, Ángel G. Andrade, David Covarrubias	An Evaluation on the Signal-to-Interference Ratio Performance of a Circular Array in CDMA Systems.	CONIELECOMP	2006	DBLP DOI BibTeX RDF
24	Christopher Dahn, Spiros Mancoridis	Using Program Transformation to Secure C Programs Against Buffer Overflows.	WCRE	2003	DBLP DOI BibTeX RDF
24	Amir Ben-Dor, Richard M. Karp, Benno Schwikowski, Zohar Yakhini	Universal DNA tag systems: a combinatorial design scheme.	RECOMB	2000	DBLP DOI BibTeX RDF
24	Peter Baumann 0001	A Database Array Algebra for Spatio-Temporal Data and Beyond.	NGITS	1999	DBLP DOI BibTeX RDF
24	Richard L. W. Brown	Writing optimization software in APL, J, and MATLAB: a comparison.	APL	1998	DBLP DOI BibTeX RDF
24	Weng-Long Chang, Chih-Ping Chu	The I+ Test.	LCPC	1998	DBLP DOI BibTeX RDF
24	Xiaoxiong Zhong, Sanjay V. Rajopadhye, Ivan Wong	Systematic generation of linear allocation functions in systolic array design.	J. VLSI Signal Process.	1992	DBLP DOI BibTeX RDF
24	Steven Anderson, Paul Hudak	Compilation of Haskell Array Comprehensions for Scientific Computing.	PLDI	1990	DBLP DOI BibTeX RDF
24	Carl McCrosky	The elimination of intermediate containers in the evaluation of first-class array expressions.	ICCL	1988	DBLP DOI BibTeX RDF
23	Timothy de Vries, Hui Ke, Sanjay Chawla, Peter Christen	Robust record linkage blocking using suffix arrays.	CIKM	2009	DBLP DOI BibTeX RDF	blocking, suffix arrays, record linkage
23	Alejandro Castillo Atoche, Deni Torres Román, Yuriy Shkvarko	Near Real Time Enhancement of Remote Sensing Imagery Based on a Network of Systolic Arrays.	CIARP	2009	DBLP DOI BibTeX RDF	Network of Systolic Arrays, Remote Sensing, Hardware/Software Co-Design
23	Theodoros Kaifas, Katherine Siakavara, Dimitrios Babas, George Miaris, Elias Vafiadis, John N. Sahalos	On the Design of Direct Radiating Antenna Arrays with Reduced Number of Controls for Satellite Communications.	MOBILIGHT	2009	DBLP DOI BibTeX RDF	Array Synthesis, Direct Radiating Arrays (DRA), Fractal Antennas, Orthogonal Method (OM)
23	Qiang Wang, Subodh Gupta, Jason Helge Anderson	Clock power reduction for virtex-5 FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, clocking
23	Michael Eagle, Tiffany Barnes	Wu's castle: teaching arrays and loops in a game.	ITiCSE	2008	DBLP DOI BibTeX RDF	CS1 education, Game2Learn, games, iteration, arrays
23	Song Fu, Cheng-Zhong Xu 0001, Brian Wims, Ramzi Basharahil	Distributed shared arrays: A distributed virtual machine with mobility support for reconfiguration.	Clust. Comput.	2006	DBLP DOI BibTeX RDF	Distributed shared arrays (DSA), Distributed virtual machine, DSA service migration, Parallel programming model
23	Giby Samson, Lawrence T. Clark	Circuit architecture for low-power race-free programmable logic arrays.	ACM Great Lakes Symposium on VLSI	2006	DBLP DOI BibTeX RDF	circuit timing, low power, programmable logic arrays
23	Jean-Paul Calvi	Intertwining unisolvent arrays for multivariate Lagrange interpolation.	Adv. Comput. Math.	2005	DBLP DOI BibTeX RDF	unisolvent arrays, multivariate polynomials, Lagrange interpolation
23	Mihai Udrescu, Lucian Prodan, Mircea Vladutiu	Improving quantum circuit dependability with reconfigurable quantum gate arrays.	Conf. Computing Frontiers	2005	DBLP DOI BibTeX RDF	accuracy threshold, reconfigurable quantum gate arrays, coding
23	Avik Chakraborty	Synthesis of Reversible Circuits for Testing with Universal Test Set and C-Testability of Reversible Iterative Logic Arrays.	VLSI Design	2005	DBLP DOI BibTeX RDF	Fault models, Testability, Design for test, Iterative logic arrays, Universal test sets, Reversible circuits
23	Dean S. Hoskins, Renée Turban, Charles J. Colbourn	Experimental designs in software engineering: d-optimal designs and covering arrays.	WISER	2004	DBLP DOI BibTeX RDF	d-optimal designs, factorial experiments, covering arrays
23	Marcus Bednara, Jürgen Teich	Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	regular processor arrays, FPGA, design automation, space-time mapping
23	Peter Vanbroekhoven, Henk Corporaal, Francky Catthoor	Advanced copy propagation for arrays.	LCTES	2003	DBLP DOI BibTeX RDF	copy propagation, optimization, arrays, single assignment
23	Amit Chowdhary, John P. Hayes	General technology mapping for field-programmable gate arrays based on lookup tables.	ACM Trans. Design Autom. Electr. Syst.	2002	DBLP DOI BibTeX RDF	lookup tables (LUTs), multiple-LUT blocks, nonrooted trees, field-programmable gate arrays, mapping, synthesis, circuit partitioning, rooted trees, Basis
23	Josef Pieprzyk, Xian-Mo Zhang	Ideal Threshold Schemes from Orthogonal Arrays.	ICICS	2002	DBLP DOI BibTeX RDF	Orthogonal Arrays, Nonlinear Functions, Threshold Secret Sharing, Cheating Detection
23	Pedro C. Diniz, Joonseok Park	Data reorganization engines for the next generation of system-on-a-chip FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF	field-programmable-gate-arrays (FPGAs), high-level synthesis, data reorganization
23	Sriram Swaminathan, Russell Tessier, Dennis Goeckel, Wayne P. Burleson	A dynamically reconfigurable adaptive viterbi decoder.	FPGA	2002	DBLP DOI BibTeX RDF	field-programmable-gate-arrays (FPGAs), high-level synthesis, data reorganization
23	Mihalis Psarakis, Dimitris Gizopoulos, Antonis M. Paschalis, Yervant Zorian	Sequential Fault Modeling and Test Pattern Generation for CMOS Iterative Logic Arrays.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Sequential fault modeling, test pattern generation, robust testing, iterative logic arrays
23	Tadayoshi Horita, Itsuo Takanami	Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	The 1$frac{1}{2}$-track switch model, reconfiguration, yield enhancement, wafer scale integration, mesh-connected processor arrays
23	Behrooz Parhami, Ding-Ming Kwai	Data-Driven Control Scheme for Linear Arrays: Application to a Stable Insertion Sorter.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	stable sorting, tagged insertion sorter, VLSI, priority queue, distributed control, FIFO, linear processor arrays, Data-driven architectures
23	Tadayoshi Horita, Itsuo Takanami	Fault Tolerant Processor Arrays Based on 1 1/2-Track Switch with Generalized Spare Distributions.	ISPAN	1999	DBLP DOI BibTeX RDF	The 1 1/2-track switch model, wefer scale integration, reconfiguration, yield enhancement, mesh-connected processor arrays
23	Itsuo Takanami, Tadayoshi Horita	Self-reconstruction of mesh-arrays with 1 1/2 -track switches by digital neural circuits.	DFT	1997	DBLP DOI BibTeX RDF	self-reconstruction, digital neural circuits, Hopfield-type neural algorith, 1 1/2 -track switches, compensation paths, subcircuits, stable state, parallel state transitions, VLSI, mesh-connected processor arrays
23	Dimitris Gizopoulos, Mihalis Psarakis, Antonis M. Paschalis	Robust Sequential Fault Testing of Iterative Logic Arrays.	VTS	1997	DBLP DOI BibTeX RDF	Sequential Faults, Linear-testability, Fault Modeling, Automatic Test Generation, C-testability, Iterative Logic Arrays
23	Dirk Fimmel, Renate Merker	Propagation of I/O-Variables in Massively Parallel Processor Arrays.	PDP	1996	DBLP DOI BibTeX RDF	parallel processor arrays, systems of recurrence equations, automatic design methods, massive parallelism
23	Sandy Pavel, Selim G. Akl	Efficient Algorithms for the Hough Transform on Arrays with Reconfigurable Optical Buses.	IPPS	1996	DBLP DOI BibTeX RDF	arrays with reconfigurable optical buses, Hough transform
23	Koray Öner, Luiz André Barroso, Sasan Iman, Jaeheon Jeong, Krishnan Ramamurthy, Michel Dubois 0001	The Design of RPM: An FPGA-based Multiprocessor Emulator.	FPGA	1995	DBLP DOI BibTeX RDF	field-programmable gate arrays, VHDL, rapid prototyping, shared-memory multiprocessors, logic emulation, message-passing multicomputers
23	Stephen D. Scott 0001, Ashok Samal, Sharad C. Seth	HGA: A Hardware-Based Genetic Algorithm.	FPGA	1995	DBLP DOI BibTeX RDF	performance acceleration, performance evaluation, field programmable gate arrays, function optimization, parallel genetic algorithms
23	Biing-Feng Wang, Gen-Huey Chen	Constant Time Algorithms for the Transitive Closure and Some Related Graph Problems on Processor Arrays with Reconfigurable Bus Systems.	IEEE Trans. Parallel Distributed Syst.	1990	DBLP DOI BibTeX RDF	related graph problems, reconfigurable bus systems, parallel algorithms, graph theory, minimum spanning trees, bipartite graphs, transitive closure, transitive closure, connected components, processor arrays, undirected graph, bridges, biconnected components, graph problems, articulation points
22	Yang Li, Lijun Ji, Jianxing Yin	Covering arrays of strength 3 and 4 from holey difference matrices.	Des. Codes Cryptogr.	2009	DBLP DOI BibTeX RDF	Mathematics Subject Classification (2000) 05B20, 94C12, 05B15
22	Jacek Dmochowski, Jacob Benesty, Sofiène Affes	On Spatial Aliasing in Microphone Arrays.	IEEE Trans. Signal Process.	2009	DBLP DOI BibTeX RDF
22	Osman Hasan, Naeem Abbasi, Sofiène Tahar	Formal Probabilistic Analysis of Stuck-at Faults in Reconfigurable Memory Arrays.	IFM	2009	DBLP DOI BibTeX RDF
22	Peyman Nayeri, Charles J. Colbourn, Goran Konjevod	Randomized Postoptimization of Covering Arrays.	IWOCA	2009	DBLP DOI BibTeX RDF
22	Wei Liu 0001, Stephan Weiss 0001	Design of Frequency Invariant Beamformers for Broadband Arrays.	IEEE Trans. Signal Process.	2008	DBLP DOI BibTeX RDF
22	Myong Hyon Cho, Chih-Chi Cheng, Michel A. Kinsy, G. Edward Suh, Srinivas Devadas	Diastolic arrays: throughput-driven reconfigurable computing.	ICCAD	2008	DBLP DOI BibTeX RDF
22	Konstantinos Drakakis, Rod Gow	Two experimental pearls in Costas arrays.	CISS	2008	DBLP DOI BibTeX RDF
22	Solomon W. Golomb, Guang Gong	The Status of Costas Arrays.	IEEE Trans. Inf. Theory	2007	DBLP DOI BibTeX RDF
22	Pascal Chevalier 0001, Anne Ferréol, Laurent Albera, Gwénaël Birot	Higher Order Direction Finding From Arrays With Diversely Polarized Antennas: The PD-2q-MUSIC Algorithms.	IEEE Trans. Signal Process.	2007	DBLP DOI BibTeX RDF
22	Vijay Ganesh, David L. Dill	A Decision Procedure for Bit-Vectors and Arrays.	CAV	2007	DBLP DOI BibTeX RDF
22	Jehan-François Pâris, Thomas J. E. Schwarz, Darrell D. E. Long	Self-Adaptive Two-Dimensional RAID Arrays.	IPCCC	2007	DBLP DOI BibTeX RDF
22	Demba E. Ba, Dinei A. F. Florêncio, Cha Zhang	Enhanced MVDR Beamforming for Arrays of Directional Microphones.	ICME	2007	DBLP DOI BibTeX RDF
22	Alessandro Armando, Massimo Benerecetti, Jacopo Mantovani	Abstraction Refinement of Linear Programs with Arrays.	TACAS	2007	DBLP DOI BibTeX RDF
22	Wing On Fung, Tughrul Arslan, Sami Khawam	A Hybrid Engine for the Placement of Domain-Specific Reconfigurable Arrays.	AHS	2007	DBLP DOI BibTeX RDF
22	Minh Quang Do, Mindaugas Drazdziulis, Per Larsson-Edefors, Lars Bengtsson	Leakage-Conscious Architecture-Level Power Estimation for Partitioned and Power-Gated SRAM Arrays.	ISQED	2007	DBLP DOI BibTeX RDF
22	Taylan Yemliha, Guangyu Chen, Ozcan Ozturk 0001, Mahmut T. Kandemir, Vijay Degalahal	Compiler-Directed Code Restructuring for Operating with Compressed Arrays.	VLSI Design	2007	DBLP DOI BibTeX RDF
22	Sriram Krishnamoorthy, Gerald Baumgartner, Chi-Chung Lam, Jarek Nieplocha, P. Sadayappan	Layout transformation support for the disk resident arrays framework.	J. Supercomput.	2006	DBLP DOI BibTeX RDF
22	Charles J. Colbourn, Sosina Martirosyan, Tran van Trung, Robert A. Walker	Roux-type constructions for covering arrays of strengths three and four.	Des. Codes Cryptogr.	2006	DBLP DOI BibTeX RDF	AMS Classification 05B40, 68N30, 05B15
22	Martin Rötteler, Pawel Wocjan	Equivalence of Decoupling Schemes and Orthogonal Arrays.	IEEE Trans. Inf. Theory	2006	DBLP DOI BibTeX RDF
22	Lidan Miao, Hairong Qi 0001	The design and evaluation of a generic method for generating mosaicked multispectral filter arrays.	IEEE Trans. Image Process.	2006	DBLP DOI BibTeX RDF
22	Masakazu Kumakiri, Li Bei, Tatsuo Tsuji, Ken Higuchi	Flexibly Resizable Multidimensional Arrays.	ICDE Workshops	2006	DBLP DOI BibTeX RDF
22	Marco A. Panduro, Aldo Mendez, Gerardo Romero, René F. Dominguez	Design of Non-uniform Circular Phased Arrays using Genetic Algorithms to Reduce the Maximum Side Lobe During Scanning.	VTC Spring	2006	DBLP DOI BibTeX RDF
22	Wu Jigang, Thambipillai Srikanthan, Xiaodong Wang	New Reconfiguration Algorithm for Degradable VLSI Arrays.	APCCAS	2006	DBLP DOI BibTeX RDF
22	Garrett S. Rose, Mircea R. Stan	A programmable majority logic array using molecular scale electronics.	FPGA	2006	DBLP DOI BibTeX RDF
22	Li Wang, Amutha Ramaswamy, Ilya P. Ioshikhes	Global Dynamics of Nucleosome Arrays: Influence of Variant Histone H2A.Z.	BIBE	2005	DBLP DOI BibTeX RDF
22	Stefan Janson, Martin Middendorf	Flexible Particle Swarm Optimization Tasks for Reconfigurable Processor Arrays.	IPDPS	2005	DBLP DOI BibTeX RDF
22	Jeong Seop Sim	Time and Space Efficient Search for Small Alphabets with Suffix Arrays.	FSKD (1)	2005	DBLP DOI BibTeX RDF
22	A. S. Sawires, Nagwa M. El-Makky, Khalil M. Ahmed	Multilevel chunking of multidimensional arrays.	AICCSA	2005	DBLP DOI BibTeX RDF
22	Ilyas Potamitis, Huimin Chen, George Tremoulis	Tracking of multiple moving speakers with multiple microphone arrays.	IEEE Trans. Speech Audio Process.	2004	DBLP DOI BibTeX RDF
22	Zhijin Wu, Rafael A. Irizarry	Stochastic models inspired by hybridization theory for short oligonucleotide arrays.	RECOMB	2004	DBLP DOI BibTeX RDF	affymetrix probe-level data, background adjustment, stochastic models, microarrays, physical models
22	Alexander Thomasian, Chunqi Han, Gang Fu, Chang Liu	A Performance Evaluation Tool for RAID Disk Arrays.	QEST	2004	DBLP DOI BibTeX RDF