Search results for "FPGA"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
37	Stephen Jang, Dennis Wu, Mark Jarvin, Billy Chan, Kevin Chung, Alan Mishchenko, Robert K. Brayton	SmartOpt: an industrial strength framework for logic synthesis.	FPGA	2009	DBLP DOI BibTeX RDF	abc, blif, edge flow, smartopt, fpga, interface, technology mapping
37	Zuo Wang, Feng Shi 0009, Qi Zuo, Weixing Ji, Mengxiao Liu	N-port memory mapping for LUT-based FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	logical-to-physical mapping, n-port memory, fpga, hierarchy
37	Paul Teehan, Guy G. Lemieux, Mark R. Greenstreet	Towards reliable 5Gbps wave-pipelined and 3Gbps surfing interconnect in 65nm FPGAs.	FPGA	2009	DBLP DOI BibTeX RDF	on-chip serdes, fpga, reliable, network-on-chip, interconnect, programmable, wave pipelining, bit-serial, surfing
37	David M. Lewis, Elias Ahmed, David Cashman, Tim Vanderhoek, Christopher Lane, Andy Lee, Philip Pan	Architectural enhancements in Stratix-IIITM and Stratix-IVTM.	FPGA	2009	DBLP DOI BibTeX RDF	power management, memory, fpga architecture, static power
37	Jason Yu, Guy G. Lemieux, Christopher Eagleston	Vector processing as a soft-core CPU accelerator.	FPGA	2008	DBLP DOI BibTeX RDF	C2H, FPGA, configurable, embedded processor, application specific, soft processor, data-level parallelism
37	Mingjie Lin, Abbas El Gamal	TORCH: a design tool for routing channel segmentation in FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA, performance analysis, segmentation, routing architecture
37	Sumanta Chaudhuri, Jean-Luc Danger, Philippe Hoogvorst, Sylvain Guilley	Efficient tiling patterns for reconfigurable gate arrays.	FPGA	2008	DBLP DOI BibTeX RDF	FPGA hexagonal octagonal, tiling interconnect
37	Yohei Matsumoto, Masakazu Hioki, Takashi Kawanami, Toshiyuki Tsutsumi, Tadashi Nakagawa, Toshihiro Sekigawa, Hanpei Koike	Performance and yield enhancement of FPGAs with within-die variation using multiple configurations.	FPGA	2007	DBLP DOI BibTeX RDF	FPGA, configuration, within-die variation, timing yield
37	N. Pete Sedcole, Peter Y. K. Cheung	Parametric yield in FPGAs due to within-die delay variations: a quantitative analysis.	FPGA	2007	DBLP DOI BibTeX RDF	statistical theory, within-die variability, modelling, FPGA, delay, reconfiguration, process variation, yield
37	Satish Sivaswamy, Kia Bazargan	Variation-aware routing for FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	statistical timing analysis, FPGA routing
37	Jason Cong, Kirill Minkovich	Improved SAT-based Boolean matching using implicants for LUT-based FPGAs.	FPGA	2007	DBLP DOI BibTeX RDF	logic synthesis, SAT, implicant, boolean matching, FPGA lookup table
37	David Slogsnat, Alexander Giese, Ulrich Brüning 0001	A versatile, low latency HyperTransport core.	FPGA	2007	DBLP DOI BibTeX RDF	HTX, HyperTransport, FPGA, prototyping, RTL
37	Lilian Atieno, Jonathan Allen, Dennis Goeckel, Russell Tessier	An adaptive Reed-Solomon errors-and-erasures decoder.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, power reduction, Reed-Solomon
37	Christopher R. Clark, David E. Schimmel	Modeling the data-dependent performance of pattern-matching architectures.	FPGA	2006	DBLP DOI BibTeX RDF	FPGA, pattern matching
37	Timothy F. Oliver, Bertil Schmidt, Douglas L. Maskell	Hyper customized processors for bio-sequence database scanning on FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	dynamic re-configuration, FPGA, bio-informatics, Smith-Waterman
37	Greg Stitt, Zhi Guo, Walid A. Najjar, Frank Vahid	Techniques for synthesizing binaries to an advanced register/memory structure.	FPGA	2005	DBLP DOI BibTeX RDF	smart buffers, FPGA, embedded systems, synthesis, decompilation, binaries
37	Aman Gayasen, Yuh-Fang Tsai, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Tim Tuan	Reducing leakage energy in FPGAs using region-constrained placement.	FPGA	2004	DBLP DOI BibTeX RDF	region-constrained placement, FPGA, leakage power
37	Sergio López-Buedo, Eduardo I. Boemo	Making visible the thermal behaviour of embedded microprocessors on FPGAs: a progress report.	FPGA	2004	DBLP DOI BibTeX RDF	JBits, FPGA, embedded processors, run-time reconfiguration, ring-oscillator, temperature measurement
37	Peter Suaris, Lung-Tien Liu, Yuzheng Ding, Nan-Chi Chou	Incremental physical resynthesis for timing optimization.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, placement, logic synthesis, timing optimization
37	François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat	A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL.	FPGA	2003	DBLP DOI BibTeX RDF	AES RIJNDAEL, high encryption rates, FPGA, cryptography, reconfigurable hardware
37	Alan Daly, William P. Marnane	Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA, encryption, RSA, public key, exponentiation, modular multiplication, montgomery
36	Chen Huang 0005, Frank Vahid	Server-side coprocessor updating for mobile devices with FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	coprocessing, fpgas, dynamic optimization, acceleration
36	Masaki Kobata, Masahiro Iida, Toshinori Sueyoshi	Effective clustering technique to optimize routability of outer cluster nets.	FPGA	2006	DBLP DOI BibTeX RDF
36	Manuel Saldaña, Lesley Shannon, Paul Chow	The routability of multiprocessor network topologies in FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
36	Joseph Zambreno, Rahul Simha, Alok N. Choudhary	Addressing application integrity attacks using a reconfigurable architecture.	FPGA	2004	DBLP DOI BibTeX RDF
36	Elaheh Bozorgzadeh, Majid Sarrafzadeh	Customized regular channel design in FPGAs.	FPGA	2003	DBLP DOI BibTeX RDF
36	Mike Estlick, Miriam Leeser, James Theiler, John J. Szymanski	Algorithmic transformations in the implementation of K- means clustering on reconfigurable hardware.	FPGA	2001	DBLP DOI BibTeX RDF
36	Atsushi Takahara, Toshiaki Miyazaki, Takahiro Murooka, Masaru Katayama, Kazuhiro Hayashi, Akihiro Tsutsui, Takaki Ichimori, Ken-nosuke Fukami	More Wires and Fewer LUTs: A Design Methodology for FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
36	Benjamin A. Levine, Senthil Natarajan, Chandra Tan, Danny F. Newport, Donald W. Bouldin	Mapping of an Automated Target Recognition Application from a Graphical Software Environment to FPGA-Based Reconfigurable Hardware.	FCCM	1999	DBLP DOI BibTeX RDF	high-level design tools, FPGA design tools, Khoros, FPGA, configurable computing
36	Krzysztof Kepa, Fearghal Morgan, Krzysztof Kosciuszkiewicz, Lars Braun, Michael Hübner 0001, Jürgen Becker 0001	FPGA Analysis Tool: High-Level Flows for Low-Level Design Analysis in Reconfigurable Computing.	ARC	2009	DBLP DOI BibTeX RDF	design assurance, bitstream debugging, security, FPGA, Reconfigurable Computing, design verification, EDA tools
36	Julien Lamoureux, Steven J. E. Wilton	On the trade-off between power and flexibility of FPGA clock networks.	ACM Trans. Reconfigurable Technol. Syst.	2008	DBLP DOI BibTeX RDF	clock-aware placement, FPGA, low-power design, clock distribution networks
36	Khalil Dayo, Abdul Qadeer Khan Rajput, Bhawani Shankar Chowdhry, Narinder P. Chowdhry	Impact of Cluster Size on Efficient LUT-FPGA Architecture for Best Area and Delay Trade-Off.	IMTIC	2008	DBLP DOI BibTeX RDF	CLBs, BLE, FPGA, Lookup table
36	Lerong Cheng, Phoebe Wong, Fei Li 0003, Yan Lin 0001, Lei He 0001	Device and architecture co-optimization for FPGA power reduction.	DAC	2005	DBLP DOI BibTeX RDF	Psim, Ptrace, powergating, FPGA, low power
36	Brad L. Hutchings, Brent E. Nelson	GigaOp DSP on FPGA.	J. VLSI Signal Process.	2004	DBLP DOI BibTeX RDF	FPGA, DSP
36	Taraneh Taghavi, Soheil Ghiasi, Abhishek Ranjan, Salil Raje, Majid Sarrafzadeh	Innovate or perish: FPGA physical design.	ISPD	2004	DBLP DOI BibTeX RDF	FPGA, partitioning, placement, physical design, floorplanning, delay estimation, routing architecture
36	Jing Huang 0001, Mehdi Baradaran Tahoori, Fabrizio Lombardi	Probabilistic Analysis of Fault Tolerance of FPGA Switch Block Array.	IPDPS	2004	DBLP DOI BibTeX RDF	fault tolerance, FPGA, routing, testing
36	Máire McLoone, John V. McCanny	Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm.	FPL	2001	DBLP DOI BibTeX RDF	Encryption, AES, Rijndael, FPGA Implementation
36	Akihiro Tsutsui, Toshiaki Miyazaki, Kazuhisa Yamada, Naohisa Ohta	Special purpose FPGA for high-speed digital telecommunication systems.	ICCD	1995	DBLP DOI BibTeX RDF	special purpose FPGA, high-speed digital telecommunication systems, high-speed transport data processing, inter-chip connection mechanism, dedicated CAD system, field programmable gate arrays, field programmable gate array, programmable logic arrays, digital communication
36	Dan Fay, Alex Shye, Sayantan Bhattacharya, Daniel A. Connors, Steve Wichmann	An Adaptive Fault-Tolerant Memory System for FPGA-based Architectures in the Space Environment.	AHS	2007	DBLP DOI BibTeX RDF
36	Young-Su Kwon, Chong-Min Kyung	Performance-driven event-based synchronization for multi-FPGA simulation accelerator with event time-multiplexing bus.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
36	Toshiaki Miyazaki, Atsushi Takahara, Takahiro Murooka, Masaru Katayama, Takaki Ichimori, Kazuhiro Shirakawa, Akihiro Tsutsui, Ken-nosuke Fukami	PROTEUS-Lite project: dedicated to developing a telecommunication-oriented FPGA and its applications.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
35	Taiga Takata, Yusuke Matsunaga	A heuristic algorithm for LUT-based FPGA technology mapping using the lower bound for DAG covering problem (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, technology mapping
35	Akira Yamawaki 0002, Masahiko Iwane	An intermediate hardware model with load/store unit for C to FPGA.	FPGA	2009	DBLP DOI BibTeX RDF	fpga., memory, design method, buffering
35	Kirill Minkovich, Jason Cong	Mapping for better than worst-case delays in LUT-based FPGA designs.	FPGA	2008	DBLP DOI BibTeX RDF	better than worst-case, razor, switching probabilities, simulation, logic synthesis, technology mapping, FPGA lookup table
35	Stephen Jang, Billy Chan, Kevin Chung, Alan Mishchenko	WireMap: FPGA technology mapping for improved routability.	FPGA	2008	DBLP DOI BibTeX RDF	area flow, cut enumeration, edge flow, FPGA, technology mapping
35	Edward C. Lin, Kai Yu, Rob A. Rutenbar, Tsuhan Chen	A 1000-word vocabulary, speaker-independent, continuous live-mode speech recognizer implemented in a single FPGA.	FPGA	2007	DBLP DOI BibTeX RDF	in silico vox, FPGA, speech recognition, DSP
35	Andrea Lodi 0002, Luca Ciccarelli, Roberto Giansante	Combining low-leakage techniques for FPGA routing design.	FPGA	2005	DBLP DOI BibTeX RDF	low leakage, FPGA, power
35	Raphael Rubin, André DeHon	Design of FPGA interconnect for multilevel metalization.	FPGA	2003	DBLP DOI BibTeX RDF	multi-level metalization, FPGA, interconnect, hierarchical, mesh-of-trees
35	Srdjan Coric, Miriam Leeser, Eric L. Miller 0001, Marc Trepanier	Parallel-beam backprojection: an FPGA implementation optimized for medical imaging.	FPGA	2002	DBLP DOI BibTeX RDF	Viterbi coding, FPGA, dynamic reconfiguration
35	Ian Robertson, James Irvine 0001, Patrick Lysaght, David Robinson	Timing verification of dynamically reconfigurable logic for the xilinx virtex FPGA series.	FPGA	2002	DBLP DOI BibTeX RDF	FPGA, verification, dynamic reconfiguration, run-time reconfiguration
35	Wei-Je Huang, Edward J. McCluskey	A memory coherence technique for online transient error recovery of FPGA configurations.	FPGA	2001	DBLP DOI BibTeX RDF	fault tolerance, FPGA, error recovery, memory coherence
35	Ali M. Shankiti, Miriam Leeser	Implementing a RAKE receiver for wireless communications on an FPGA-based computer system.	FPGA	2000	DBLP DOI BibTeX RDF	FPGA, wireless communications, RAKE receiver
35	John Marty Emmert, Dinesh Bhatia	A Methodology for Fast FPGA Floorplanning.	FPGA	1999	DBLP DOI BibTeX RDF	clustering, FPGA, placement, Tabu search, floorplanning
35	Rick Amerson, Richard J. Carter, W. Bruce Culbertson, Philip Kuekes, Greg Snider, Lyle Albertson	Plasma: An FPGA for Million Gate Systems.	FPGA	1996	DBLP DOI BibTeX RDF	custom computing, FPGA, register files
35	Jason Helge Anderson, Chirag Ravishankar	FPGA power reduction by guarded evaluation.	FPGA	2010	DBLP DOI BibTeX RDF	optimization, field-programmable gate arrays, fpgas, low-power design, power, logic synthesis, technology mapping
35	Yi-Hua E. Yang, Viktor K. Prasanna	High throughput and large capacity pipelined dynamic search tree on FPGA.	FPGA	2010	DBLP DOI BibTeX RDF	2-3 tree, in-place update, ip forwarding, pipelined tree, b-tree, dynamic update, incremental update, openflow
35	Tim Tuan, Sean Kao, Arifur Rahman, Satyaki Das, Steven Trimberger	A 90nm low-power FPGA for battery-powered applications.	FPGA	2006	DBLP DOI BibTeX RDF	FPGAs, field-programmable gate arrays, low-power design, programmable logic
35	Paulo Sérgio B. do Nascimento, Paulo Romero Martins Maciel, Manoel Eusébio de Lima, Remy Eskinazi Sant'Anna, Abel Guilhermino Silva-Filho	A partial reconfigurable FPGA implementation for industrial controllers using SFC-petri net description (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
35	Nicola Bruti Liberati, Eckhard Platen, Filippo Martini, Massimo Piccardi	An FPGA generator for multipoint distributed random variables (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
35	Sven Heithecker, Rolf Ernst	An FPGA based SDRAM controller with complex QoS scheduling and traffic shaping (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
35	Alex K. Jones, Raymond Hoare, Dara Kusic, Joshua Fazekas, John Foster 0001	An FPGA-based VLIW processor with custom hardware execution.	FPGA	2005	DBLP DOI BibTeX RDF	NIOS, parallelism, compiler, synthesis, kernels, VLIW
35	Sherif M. Saif, Hazem M. Abbas, Salwa M. Nassar	An FPGA implementation of block truncation coding for gray and color images.	FPGA	2004	DBLP DOI BibTeX RDF
35	Pronita Mehrotra, Mrugendra Singhai, Mike Pratt, Mark Cassada, Patrick Hamilton	FPGA implementation of a high speed network interface card for optical burst switched networks.	FPGA	2004	DBLP DOI BibTeX RDF
35	Roland E. Wunderlich, James C. Hoe	In-system FPGA prototyping of an itanium microarchitecture.	FPGA	2004	DBLP DOI BibTeX RDF
35	Jae-Jin Lee, Gi-Yong Song	Bit-level super-systolic array for FIR filter with a FPGA-based bit-serial semi-systolic multiplier.	FPGA	2004	DBLP DOI BibTeX RDF
35	Anatole D. Ruslanov, Jeremy R. Johnson	An FPGA implementation of bene permutation networks.	FPGA	2004	DBLP DOI BibTeX RDF
35	Parag K. Lala, B. Kiran Kumar	An FPGA architecture with built-in error correction capability.	FPGA	2003	DBLP DOI BibTeX RDF
35	Zdenek Pohl, Rudolf Matousek, Jiri Kadlec, Milan Tichý, Miroslav Lícko	Lattice adaptive filter implementation for FPGA.	FPGA	2003	DBLP DOI BibTeX RDF
35	Abdsamad Benkrid, Danny Crookes, Khaled Benkrid	Design framework for the implementation of the 2-D orthogonal discrete wavelet transform on FPGA.	FPGA	2003	DBLP DOI BibTeX RDF
35	Stuart McCracken, Zeljko Zilic	FPGA test time reduction through a novel interconnect testing scheme.	FPGA	2002	DBLP DOI BibTeX RDF
35	Seetharaman Ramachandran, S. Srinivasan 0001	FPGA implementation of a novel, fast motion estimation algorithm for real-time video compression.	FPGA	2001	DBLP DOI BibTeX RDF	quantization and variable length code, sum of absolute pixel intensity difference, motion estimation, discrete cosine transform, block matching algorithm, macroblock
35	Chandra Mulpuri, Scott Hauck	Runtime and quality tradeoffs in FPGA placement and routing.	FPGA	2001	DBLP DOI BibTeX RDF	fast CAD for FPGAs, FPGAs, routing, computer-aided design, placement
35	Gerhard Lienhart, Reinhard Männer, Klaus-Henning Noffz, Ralf Lay	An FPGA-based video compressor for H.263 compatible bit streams.	FPGA	2001	DBLP DOI BibTeX RDF	distributed arithmetic
35	Amit Singh 0001, Arindam Mukherjee 0001, Malgorzata Marek-Sadowska	Interconnect pipelining in a throughput-intensive FPGA architecture.	FPGA	2001	DBLP DOI BibTeX RDF
35	Herman Schmit, Ray Andraka, Philip Friedin, Satnam Singh, Tim Southgate	The John Henry Syndrome (panel session)(abstract only): humans vs. machines as FPGA designers.	FPGA	2000	DBLP DOI BibTeX RDF
35	Lan Zhao, D. M. H. Walker, Fabrizio Lombardi	Bridging Fault Detection in FPGA Interconnects Using IDDQ.	FPGA	1998	DBLP DOI BibTeX RDF
35	Pak K. Chan, Martine D. F. Schlag, Jason Y. Zien	Spectral-Based Multi-Way FPGA Partitioning.	FPGA	1995	DBLP DOI BibTeX RDF
34	Vasilios Kalenteridis, Haroula Pournara, Kostas Siozios, Konstantinos Tatas, George Koutroumpezis, Ilias Pappas 0001, Spiridon Nikolaidis 0001, Stilianos Siskos, D. J. Soudris, Adonios Thanailakis	An Integrated FPGA Design Framework: Custom Designed FPGA Platform and Application Mapping Toolset Development.	IPDPS	2004	DBLP DOI BibTeX RDF	Low Power FPGA interconnect architecture, CLB Architecture, Graphical User Interface
34	Roman L. Lysecky, Frank Vahid, Sheldon X.-D. Tan	Dynamic FPGA routing for just-in-time FPGA compilation.	DAC	2004	DBLP DOI BibTeX RDF	FPGA, dynamic optimization, system-on-a-chip, platforms, codesign, hardware/software partitioning, just-in-time compilation, configurable logic, place and route, warp processors
34	Eric S. Chung, Michael Papamichael, Eriko Nurvitadhi, James C. Hoe, Ken Mai, Babak Falsafi	ProtoFlex: Towards Scalable, Full-System Multiprocessor Simulations Using FPGAs.	ACM Trans. Reconfigurable Technol. Syst.	2009	DBLP DOI BibTeX RDF	simulator, FPGA, prototype, multiprocessor, multicore, emulator
34	Valeri Kirischian, Vadim Geurkov, Lev Kirischian	A multi-mode video-stream processor with cyclically reconfigurable architecture.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	cost-performance ratio, video-stream processor, FPGA, computer architecture, reconfigurable computing, dynamic reconfiguration, pre-fetching, temporal partitioning
34	Zhen Luo, Margaret Martonosi	Accelerating Pipelined Integer and Floating-Point Accumulations in Configurable Hardware with Delayed Addition Techniques.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	Delayed addition, multiply-accumulate, FPGA, MAC, accumulation
34	Charles E. Stroud, John Sunwoo, Srinivas M. Garimella, Jonathan Harris	Built-In Self-Test for System-on-Chip: A Case Study.	ITC	2004	DBLP DOI BibTeX RDF
33	Muhammed Kawser Ahmed, Christophe Bobda	ISO-TENANT: Rethinking FPGA Power Distribution Network (PDN): A Hardware Based Solution for Remote Power Side Channel Attacks in FPGA.	FPGA	2024	DBLP DOI BibTeX RDF
33	Qianfeng Clark Shen, Jun Zheng, Paul Chow	RIFL: A Reliable Link Layer Network Protocol for FPGA-to-FPGA Communication.	FPGA	2021	DBLP DOI BibTeX RDF
33	Raymond X. Nijssen	FPGAs will Never be the Same Again: How the Newest FPGA Architectures are Totally Disrupting the Entire FPGA Ecosystem as We Know It.	FPGA	2020	DBLP DOI BibTeX RDF
33	Michaela Blott, Johannes Kath, Lisa Halder, Yaman Umuroglu, Nicholas J. Fraser, Giulio Gambardella, Miriam Leeser, Linda Doyle	Evaluation of Optimized CNNs on FPGA and non-FPGA based Accelerators using a Novel Benchmarking Approach.	FPGA	2020	DBLP DOI BibTeX RDF
33	Dario Korolija, Mirjana Stojilovic	Design and Implementation of a Deterministic FPGA Router on a CPU+FPGA Acceleration Platform.	FPGA	2019	DBLP DOI BibTeX RDF
33	Qingshan Tang, Matthieu Tuna, Habib Mehrez	Future inter-FPGA communication architecture for multi-FPGA based prototyping (abstract only).	FPGA	2014	DBLP DOI BibTeX RDF
33	Jason Cong, Bingjun Xiao	FPGA-RR: an enhanced FPGA architecture with RRAM-based reconfigurable interconnects (abstract only).	FPGA	2012	DBLP DOI BibTeX RDF
32	Charles Eric LaForest, J. Gregory Steffan	Efficient multi-ported memories for FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	fpga, parallel, memory, multi-port
32	Chun Zhang, Yu Hu 0002, Lingli Wang, Lei He 0001, Jiarong Tong	Building a faster boolean matcher using bloom filter.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, SAT, bloom filter, boolean matching, re-synthesis
32	Shaoshan Liu, Richard Neil Pittman, Alessandro Forin	Minimizing partial reconfiguration overhead with fully streaming DMA engines and intelligent ICAP controller (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, partial reconfiguration
32	Doris Chen, Deshanand P. Singh, Jeffrey Chromczak, David M. Lewis, Ryan Fung, David Neto, Vaughn Betz	A comprehensive approach to modeling, characterizing and optimizing for metastability in FPGAs.	FPGA	2010	DBLP DOI BibTeX RDF	mtbf, fpga, metastability
32	Edward A. Stott, Justin S. J. Wong, N. Pete Sedcole, Peter Y. K. Cheung	Degradation in FPGAs: measurement and modelling.	FPGA	2010	DBLP DOI BibTeX RDF	FPGA, self test
32	Gregory Lucas, Chen Dong 0003, Deming Chen	Variation-aware placement for FPGAs with multi-cycle statistical timing analysis.	FPGA	2010	DBLP DOI BibTeX RDF	multi-cycle, variation-aware, fpga, placement, ssta, statistical static timing analysis
32	Hao Wang, Shi Pu, Gabriel Knezek, Jyh-Charn Liu	A modular NFA architecture for regular expression matching.	FPGA	2010	DBLP DOI BibTeX RDF	character class constraint repetition, overlapped matching, FPGA, regular expression, NFA
32	Shaoshan Liu, Richard Neil Pittman, Alessandro Forin	Energy reduction with run-time partial reconfiguration (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	fpga, energy
32	Hoang Le, Yi-Hua E. Yang, Viktor K. Prasanna	Memory efficient string matching: a modular approach on FPGAs (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	deep packet classification, fpga, packet filtering
32	Brahim Al Farisi, Karel Bruneel, Harald Devos, Dirk Stroobandt	Automatic tool flow for shift-register-LUT reconfiguration: making run-time reconfiguration fast and easy (abstract only).	FPGA	2010	DBLP DOI BibTeX RDF	parameterizable configurations, tmap, fpga, reconfigurable computing, run-time reconfiguration, srl, icap