Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
1 | Jin Guo 0001, Antonis Papanikolaou, Pol Marchal, Francky Catthoor |
Energy/area/delay trade-offs in the physical design of on-chip segmented bus architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 75-81, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
segmented bus, floorplanning, trade-offs |
1 | Mandeep Bamal, Youssef Travaly, Wenqi Zhang, Michele Stucchi, Karen Maex |
Impact of interconnect resistance increase on system performance of low power and high performance designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 85-90, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
interconnect sizing, interconnect technology evaluation, power-delay trade-off, wire sizing |
1 | Young-Sin Cho, Eun-Ju Choi, Kyoung-Rok Cho |
Modeling and analysis of the system bus latency on the SoC platform. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 67-74, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
multi-layer bus, system bus, SoC, latency, platform |
1 | Wim Heirman, Joni Dambre, Jan M. Van Campenhout |
Congestion modeling for reconfigurable inter-processor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 59-66, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
interconnection network, prediction, reconfiguration, congestion |
1 | Valavan Manohararajah, Gordon R. Chiu, Deshanand P. Singh, Stephen Dean Brown |
Difficulty of predicting interconnect delay in a timing driven FPGA CAD flow. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 3-8, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Louis Scheffer |
An overview of on-chip interconnect variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 27-28, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
causes of variability, on-chip variation, design rules |
1 | Mike Hutton, Joni Dambre (eds.) |
The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![ACM, 1-59593-255-0 The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP BibTeX RDF |
|
1 | Manuel Saldaña, Lesley Shannon, Paul Chow |
The routability of multiprocessor network topologies in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 49-56, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA, multiprocessor, network-on-chip, topology, interconnect |
1 | Andrew B. Kahng, Bao Liu 0001, Xu Xu 0001 |
Statistical crosstalk aggressor alignment aware interconnect delay calculation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 91-97, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
1 | Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng 0001, Hannu Tenhunen |
Minimal-power, delay-balanced smart repeaters for interconnects in the nanometer regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 113-120, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
delay-balanced, minimal-power, interconnects, repeaters |
1 | Mary Yvonne Lanzerotti, Giovanni Fiorenza, Rick A. Rand |
Predicting interconnect requirements in ultra-large-scale integrated control logic circuitry. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 43-50, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
wire-length distribution model, routing, interconnect, rent |
1 | Igor L. Markov, Mike Hutton (eds.) |
The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![ACM, 1-59593-033-7 The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP BibTeX RDF |
|
1 | David J. Hathaway |
Dealing with the spatio-temporal interactions among transient power, supply noise and timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 61, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Takumi Uezono, Junpei Inoue, Takanori Kyogoku, Kenichi Okada, Kazuya Masu |
Prediction of delay time for future LSI using on-chip transmission line interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 7-12, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | N. S. Nagaraj |
Dealing with interconnect process variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 39, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
1 | Katherine Shu-Min Li, Chung-Len Lee 0001, Yao-Wen Chang, Chauchin Su, Jwu E. Chen |
Multilevel full-chip routing with testability and yield enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 29-36, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
multilevel routing, yield, testability |
1 | Young-Su Kwon, Payam Lajevardi, Anantha P. Chandrakasan, Frank Honoré, Donald E. Troxel |
A 3-D FPGA wire resource prediction model validated using a 3-D placement and routing tool. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 65-72, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
3-D FPGA, wire resource prediction |
1 | Wim Heirman, Joni Dambre, Christof Debaes, Hugo Thienpont, Dirk Stroobandt, Jan Van Campenhout |
Prediction model for evaluation of reconfigurable interconnects in distributed shared-memory systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 51-58, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
interconnection network, reconfiguration, distributed shared-memory, prediction model |
1 | Jurjen Westra, Patrick Groeneveld |
Is probabilistic congestion estimation worthwhile? ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 99-106, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
congestion estimation, degenerate global routing, probabilistic congestion estimation, congestion, routability |
1 | Jens Lienig |
Interconnect and current density stress: an introduction to electromigration-aware design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 81-88, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
interconnect, layout, physical design, electromigration, current density, interconnect reliability |
1 | Guoqing Chen, Hui Chen, Mikhail Haurylau, Nicholas Nelson 0001, Philippe M. Fauchet, Eby G. Friedman, David H. Albonesi |
Predictions of CMOS compatible on-chip optical interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 13-20, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
CMOS compatible, on-chip, optical interconnect, trends |
1 | Viet H. Nguyen, Phillip Christie |
The impact of interstratal interconnect density on the performance of three-dimensional integrated circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 73-78, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
interstratal interconnect, 3D-IC, system-level |
1 | Chiu-Wing Sham, Evangeline F. Y. Young |
Congestion prediction in early stages. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 91-98, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
placement, floorplanning, interconnect estimation |
1 | J. Balachandran, Steven Brebels, Geert Carchon, Tomas Webers, Walter De Raedt, Bart Nauwelaers, Eric Beyne |
Package level interconnect options. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 21-27, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
performance metrics, package, transmission lines, global interconnects |
1 | Ron Ho |
High-performance ULSI: the real limiter to interconnect scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Seventh International Workshop on System-Level Interconnect Prediction (SLIP 2005), San Francisco, CA, USA, April 2-3, 2005, Proceedings, pp. 3, 2005, ACM, 1-59593-033-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
VLSI, wireless, 3D, scaling, proximity, repeaters, wires |
1 | Louis Scheffer, Igor L. Markov (eds.) |
The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![ACM, 1-58113-818-0 The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP BibTeX RDF |
|
1 | Dmitri B. Chklovskii |
Evolution as the blind engineer: wiring minimization in the brain. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 63, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
1 | Mandeep Bamal, Evelyn Grossar, Michele Stucchi, Karen Maex |
Interconnect width selection for deep submicron designs using the table lookup method. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 41-44, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect sizing, power-delay trade-off, wire sizing |
1 | Beng Hwee Ong, Choon Beng Sia, Kiat Seng Yeo, Jianguo Ma, Manh Anh Do, Erping Li |
Investigating the frequency dependence elements of CMOS RFIC interconnects for physical modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 31-38, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
distributed effects, frequency dependence elements, physical model, skin effects |
1 | Reinaldo A. Bergamaschi |
Early and accurate analysis of SoCs: oxymoron or real? ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 3-6, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
performance, power, design space exploration, floorplanning, design analysis |
1 | Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Bendix |
Prediction of interconnect adjacency distribution: derivation, validation, and applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 99-106, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect adjacency, interconnect pattern density, prediction, stochastic model, probability density function |
1 | Ajay Joshi, Jeffrey A. Davis |
A 2-slot time-division multiplexing (TDM) interconnect network for gigascale integration (GSI). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 64-68, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect area, wire sharing, time-division multiplexing |
1 | Maurizio Martina, Guido Masera |
A statistical model for estimating the effect of process variations on crosstalk noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 115-120, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
statistical analysis, interconnects modeling |
1 | Bipin Rajendran, Pawan Kapur, Krishna Saraswat, R. Fabian W. Pease |
Self-consistent power/performance/reliability analysis for copper interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 17-22, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Joule heating, copper interconnects, rent's rule, electromigration, duty cycle, current density |
1 | Tao Wan, Malgorzata Chrzanowska-Jeske |
Prediction of interconnect net-degree distribution based on Rent's rule. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 107-114, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
net-degree distribution, Rent's rule, interconnect prediction |
1 | Ian O'Connor |
Optical solutions for system-level interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 79-88, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect technology, optical network on chip, optical interconnect |
1 | Arvind Kumar, Sandip Tiwari |
Defect tolerance for nanocomputer architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 89-96, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
wire length estimation, FPGA, reliability, reconfigurability, defect tolerance, nanoelectronics, Rent's rule, nanocomputing |
1 | Vikas Chandra, Anthony Xu, Herman Schmit |
A low power approach to system level pipelined interconnect design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 45-52, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
pipelined interconnect, low power, voltage scaling |
1 | Puneet Gupta 0001, Andrew B. Kahng, Youngmin Kim, Dennis Sylvester |
Investigation of performance metrics for interconnect stack architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 23-29, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
back-end metrics, interconnect stacks, via blockage, throughput, energy, bandwidth |
1 | Tapani Ahonen, David A. Sigüenza-Tortosa, Hong Bin, Jari Nurmi |
Topology optimization for application-specific networks-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 53-60, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
application-specific network, platform design, network-on-chip, topology optimization |
1 | Vishak Venkatraman, Andrew Laffely, Jinwook Jang, Hempraveen Kukkamalla, Zhi Zhu, Wayne P. Burleson |
NoCIC: a spice-based interconnect planning tool emphasizing aggressive on-chip interconnect circuit methods. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 69-75, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
on-chip, spice-based, network-on-chip, interconnects, signaling |
1 | Nir Magen, Avinoam Kolodny, Uri C. Weiser, Nachum Shamir |
Interconnect-power dissipation in a microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Sixth International Workshop on System-Level Interconnect Prediction (SLIP 2004), Paris, France, February 14-15, 2004, Proceedings, pp. 7-13, 2004, ACM, 1-58113-818-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
interconnect power, wire spacing, routing, low-power design |
1 | Andrew B. Kahng, Xu Xu 0001 |
Accurate pseudo-constructive wirelength and congestion estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 61-68, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Chao-Yang Yeh, Malgorzata Marek-Sadowska |
Sequential delay budgeting with interconnect prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 23-30, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
delay budgeting, sequential circuits, interconnect prediction |
1 | Ketan N. Patel, Igor L. Markov |
Error-correction and crosstalk avoidance in DSM busses. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 9-14, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
DSM busses, error-correction, crosstalk noise, bus encoding |
1 | Pranav Anbalagan, Jeffrey A. Davis |
Maximum multiplicity distributions (MMD). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 107-113, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
system-level prediction, wire-length distributions, simulated annealing |
1 | Joachim Pistorius, Mike Hutton |
Placement rent exponent calculation methods, temporal behaviour and FPGA architecture evaluation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 31-38, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPGA architecture, interconnect prediction, SLIP, rent |
1 | Jason Helge Anderson, Farid N. Najm |
Switching activity analysis and pre-layout activity prediction for FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 15-21, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
FPGAs, field-programmable gate arrays, low-power design, power, estimation |
1 | Eli Chiprout |
Early electrical wire projections and implications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 95, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Jian Liu, Meigen Shen, Li-Rong Zheng 0001, Hannu Tenhunen |
System level interconnect design for network-on-chip using interconnect IPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 117-124, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
interconnect IP, network on chip, interconnect, bandwidth optimization |
1 | Dennis Sylvester, Dirk Stroobandt, Louis Scheffer, Payman Zarkesh-Ha (eds.) |
The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![ACM, 1-58113-627-7 The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP BibTeX RDF |
|
1 | Qinghua Liu, Bo Hu 0006, Malgorzata Marek-Sadowska |
Wire length prediction in constraint driven placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 99-105, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
wire length prediction, clustering |
1 | Feng Zhou, Esther Y. Cheng, Bo Yao, Chung-Kuan Cheng, Ronald L. Graham |
A hierarchical three-way interconnect architecture for hexagonal processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 133-139, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Y architecture, Y tree, interconnect architecture |
1 | Hongyu Chen, Chung-Kuan Cheng, Andrew B. Kahng, Ion I. Mandoiu, Qinke Wang |
Estimation of wirelength reduction for lambda-geometry vs. manhattan placement and routing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 71-76, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
?-geometry routing, ?-geometry-driven placement, wirelength reduction estimation |
1 | Joni Dambre, Dirk Stroobandt, Jan Van Campenhout |
Fast estimation of the partitioning rent characteristic using a recursive partitioning model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 45-52, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
a priori wire length prediction, recursive circuit partitioning, graph bipartitioning |
1 | Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex |
Global interconnect trade-off for technology over memory modules to application level: case study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 125-132, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Pareto-optimal energy/delay interconnect exploration, interconnect wire processing, intra/inter-memory interconnect |
1 | Navaratnasothie Selvakkumaran, Phiroze N. Parakh, George Karypis |
Perimeter-degree: a priori metric for directly measuring and homogenizing interconnection complexity in multilevel placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 53-59, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
interconnection complexity, multilevel global placement, nonhomogeneity, perimeter-degree, congestion, routability |
1 | Martijn T. Bennebroek |
Validation of wire length distribution models on commercial designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 41, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
1 | Payman Zarkesh-Ha, Ken Doniger, William Loh, Peter Wright |
Prediction of interconnect pattern density distribution: derivation, validation, and applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 85-91, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
interconnect network prediction, interconnect pattern density, Stochastic model, probability density function |
1 | Victor N. Kravets, Prabhakar Kudva |
Understanding metrics in logic synthesis for routability enhancement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 3-5, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
optimization, VLSI, synthesis, decomposition, layout, congestion, structure, circuits |
1 | Shankar Balachandran, Dinesh Bhatia |
A-priori wirelength and interconnect estimation based on circuit characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 5th International Workshop on System-Level Interconnect Prediction (SLIP 2003), Monterey, CA, USA, April 5-6, 2003, Proceedings, pp. 77-84, 2003, ACM, 1-58113-627-7. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
routing demand, placement, wirelength, interconnect estimation |
1 | Muzammil Iqbal, Ahmed Sharkawy, Usman Hameed, Phillip Christie |
Stochastic wire length sampling for cycle time estimation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 91-96, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
cycle time estimates, wire sampling, performance modeling, physical design |
1 | Seongkyun Shin, Yungseon Eo, William R. Eisenstadt, Jongin Shim |
Analytical signal integrity verification models for inductance-dominant multi-coupled VLSI interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 61-68, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
TWA, signal integrity verification, delay, crosstalk, ringing, signal integrity, transmission line, glitch, VLSI interconnect, traveling-wave |
1 | Raymond A. Wildman, Joshua I. Kramer, Daniel S. Weile, Phillip Christie |
Wire layer geometry optimization using stochastic wire sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 97-102, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
genetic algorithms, optimization, interconnect, Rent's rule |
1 | Murat R. Becer, David T. Blaauw, Ibrahim N. Hajj, Rajendran Panda |
Early probabilistic noise estimation for capacitively coupled interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 77-83, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
early noise analysis, congestion, global routing |
1 | Andrey V. Mezhiba, Eby G. Friedman |
Scaling trends of on-chip Power distribution noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 47-53, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
technology scaling, power supply noise, power distribution |
1 | Antonis Papanikolaou, Miguel Miranda, Francky Catthoor, Henk Corporaal, Hugo De Man, David De Roest, Michele Stucchi, Karen Maex |
Interconnect exploration for future wire dominated technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 105-106, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
interconnect wire processing, intra/inter-memory interconnect, pareto-optimal energy/delay interconnect exploration |
1 | Stephen E. Krufka, Phillip Christie |
Terminal optimization analysis for functional block re-use. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 3-8, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
optimization, SoC, interconnect, Rent's rule |
1 | Ingrid Verbauwhede, M.-C. Frank Chang |
Reconfigurable interconnect for next generation systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 71-74, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
architectures, reconfiguration, interconnect, design methods, power efficiency |
1 | Sudhakar Muddu |
Estimation needs for future networking systems interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 41-44, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Hongyu Chen, Changge Qiao, Feng Zhou, Chung-Kuan Cheng |
Refined single trunk tree: a rectilinear steiner tree generator for interconnect prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 85-89, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
rectilinear steiner tree algorithm, refined single trunk tree, routing estimation, VLSI CAD |
1 | Sani R. Nassif, Onsi Fakhouri |
Technology trends in power-grid-induced noise. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 55-59, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
power grid noise |
1 | Amit Singh 0001, Malgorzata Marek-Sadowska |
FPGA interconnect planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 23-30, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Steven L. Teig |
The X architecture: not your father's diagonal wiring. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 33-37, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | |
The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![ACM The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP BibTeX RDF |
|
1 | Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout |
Getting more out of Donath's hierarchical model for interconnect prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 9-16, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Donath's wirelength estimation technique, a priori wirelength estimation, partitioning based placement |
1 | Tianpei Zhang, Sachin S. Sapatnekar |
Optimized pin assignment for lower routing congestion after floorplanning phase. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 17-21, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
1 | Dirk Stroobandt |
A priori system-level interconnect prediction: Rent's rule and wire length distribution models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 3-21, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
1 | Peter Verplaetse, Joni Dambre, Dirk Stroobandt, Jan Van Campenhout |
On partitioning vs. placement rent properties. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 33-40, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
wire length distribution, partitioning, placement, estimation, Rent's rule |
1 | Ralph H. J. M. Otten, Giuseppe S. Garcea |
Are wires plannable? ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 59-66, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
1 | Michael D. Hutton |
Interconnect prediction for programmable logic devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 125-131, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
interconnect prodiction, wireability, architecture, programmable logic device |
1 | André DeHon |
Rent's rule based switching requirements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 197-204, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
switching requirements, hierarchical networks, Rent's rule |
1 | |
The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![ACM The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP BibTeX RDF |
|
1 | Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni |
Hierarchical power supply noise evaluation for early power grid design prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 183-188, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
1 | Xiaojian Yang, Elaheh Bozorgzadeh, Majid Sarrafzadeh |
Wirelength estimation based on rent exponents of partitioning and placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 25-31, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
1 | Ganapathy Parthasarathy, Malgorzata Marek-Sadowska, Arindam Mukherjee 0001, Amit Singh 0001 |
Interconnect complexity-aware FPGA placement using Rent's rule. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 115-121, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
Rent's exponent, interconnect, placement |
1 | Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout |
On rent's rule for rectangular regions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 49-56, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
layout Rent parameters, rectangular layout region, wirelength distribution, Rent's rule |
1 | Kenneth D. Boese, Andrew B. Kahng, Stefanus Mantik |
On the relevance of wire load models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 91-98, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
1 | Phillip Christie, José Pineda de Gyvez |
Pre-layout prediction of interconnect manufacturability. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 167-173, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
design, reliability, interconnect, theory, yield, Rent's rule, critical areas |
1 | James D. Z. Ma, Lei He 0001 |
Simultaneous signal and power routing under K model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 175-182, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
net ordering, on-chip inductance, shield insertion, interconnect estimation, interconnect design |
1 | José Pineda de Gyvez |
Yield modeling and BEOL fundamentals. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 135-163, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
1 | Arifur Rahman, Shamik Das, Anantha P. Chandrakasan, Rafael Reif |
Wiring requirement and three-dimensional integration of field-programmable gate arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 107-113, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
3-D integrated circuits, FPGA, system-level modeling, wire-length |
1 | Shih-Hsu Huang |
An effective low power design methodology based on interconnect prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 189-194, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
1 | Dirk Stroobandt |
Multi-terminal nets do change conventional wire length distribution models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 41-48, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
multi-terminal nets, wire length estimation, Rent's rule |
1 | Chung-Kuan Cheng, Andrew B. Kahng, Bao Liu 0001 |
Interconnect implications of growth-based structural models for VLSI circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 99-106, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
1 | Kenneth Rose |
A comprehensive look at system level model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31 - April 1, 2001, DoubleTree Hotel, Rohnert Park, CA, USA, Proceedings, pp. 69-87, 2001, ACM. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
1 | Jeffrey A. Davis, Raguraman Venkatesan, Keith A. Bowman, James D. Meindl |
Gigascale integration (GSI) interconnect limits and n-tier multilevel interconnect architectural solutions (discussion session). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 147-148, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Phillip Christie |
Managing interconnect resources (tutorial). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 1-51, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
1 | Payman Zarkesh-Ha, Jeffrey A. Davis, William Loh, James D. Meindl |
Prediction of interconnect fan-out distribution using Rent's rule. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 107-112, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
fan-out distribution, interconnect network prediction, Rent's rule |
1 | Krishna Saraswat, Shukri J. Souri, Kaustav Banerjee, Pawan Kapur |
Performance analysis and technology of 3-D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 85-90, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
VLSI, interconnect, circuits, ICs, 3-D |