Search results for "adder"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
26	Guangping Li 0002, Dingkai Liang	Adder Wavelet for Better Image Classification under Adder Neural Network.	CSAI	2022	DBLP DOI BibTeX RDF
26	Hyoju Seo, Jungwon Lee, Hyelin Seok, Yongtae Kim	Design of an Accuracy Enhanced Imprecise Adder with Half Adder-based Approximation.	ISOCC	2021	DBLP DOI BibTeX RDF
26	Subodh Kumar Singhal, Basant K. Mohanty, Sujit Kumar Patel, Gaurav Saxena	Efficient Diminished-1 Modulo (2n+1) Adder Using Parallel Prefix Adder.	J. Circuits Syst. Comput.	2020	DBLP DOI BibTeX RDF
26	Ayad Dalloo, Ardalan Najafi, Alberto García Ortiz	Systematic Design of an Approximate Adder: The Optimized Lower Part Constant-OR Adder.	IEEE Trans. Very Large Scale Integr. Syst.	2018	DBLP DOI BibTeX RDF
26	P. Balasubramanian 0001	Asynchronous Ripple Carry Adder based on Area Optimized Early Output Dual-Bit Full Adder.	CoRR	2018	DBLP BibTeX RDF
26	Morgana Macedo, Leonardo Bandeira Soares, Bianca Silveira, Cláudio Machado Diniz, Eduardo A. C. da Costa	Exploring the use of parallel prefix adder topologies into approximate adder circuits.	ICECS	2017	DBLP DOI BibTeX RDF
26	P. Balasubramanian 0001, Nikos E. Mastorakis	An Asynchronous Early Output Full Adder and a Relative-Timed Ripple Carry Adder.	CoRR	2016	DBLP BibTeX RDF
26	P. Balasubramanian 0001, K. Prasad	Early Output Hybrid Input Encoded Asynchronous Full Adder and Relative-Timed Ripple Carry Adder.	CoRR	2016	DBLP BibTeX RDF
26	Manan Mewada, Mazad Zaveri	An input test pattern for characterization of a full-adder and n-bit ripple carry adder.	ICACCI	2016	DBLP DOI BibTeX RDF
26	Pao-Lung Chen	A low-cost carry look-ahead adder for flying-adder frequency synthesizer.	ICCE-TW	2016	DBLP DOI BibTeX RDF
26	Sunghyun Kim, Youngmin Kim	Energy-efficient hybrid adder design by using inexact lower bits adder.	APCCAS	2016	DBLP DOI BibTeX RDF
26	Praveena Murugesan, Thanushkodi Keppanagounder	Design of Optimal Carry Skip Adder and Carry Skip BCD Adder using Reversible Logic Gates.	J. Comput. Sci.	2014	DBLP DOI BibTeX RDF
26	Lalitha Mohana Kalyani-Garimella, Sri Raga Sudha Garimella, Kevin Duda, Eric S. Fetzer	New generation carry look twice-ahead adder CL2A and carry look thrice-ahead adder CL3A.	MWSCAS	2013	DBLP DOI BibTeX RDF
26	Yu-Shun Wang, Min-Han Hsieh, James Chien-Mo Li, Charlie Chung-Ping Chen	An At-Speed Test Technique for High-Speed High-order Adder by a 6.4-GHz 64-bit Domino Adder Example.	IEEE Trans. Circuits Syst. I Regul. Pap.	2012	DBLP DOI BibTeX RDF
26	Yiran Chen 0001, Hai Li 0001, Cheng-Kok Koh, Guangyu Sun 0003, Jing Li 0073, Yuan Xie 0001, Kaushik Roy 0001	Variable-Latency Adder (VL-Adder) Designs for Low Power and NBTI Tolerance.	IEEE Trans. Very Large Scale Integr. Syst.	2010	DBLP DOI BibTeX RDF
26	David Bol, Ilham Hassoune, David Levacq, Denis Flandre, Jean-Didier Legat	Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder.	J. Multiple Valued Log. Soft Comput.	2007	DBLP BibTeX RDF
26	Giacinto Paolo Saggese, Antonio G. M. Strollo, Nicola Mazzocca, Davide De Caro	Shuffled serial adder: an area-latency effective serial adder.	ICECS	2002	DBLP DOI BibTeX RDF
24	Xinmiao Zhang, Jiangli Zhu	Efficient interpolration architecture for soft-decision Reed-Solomon decoding by applying slow-down.	SiPS	2008	DBLP DOI BibTeX RDF
24	Jon Alfredsson, Snorre Aunet	Performance of CMOS and Floating-Gate Full-Adders Circuits at Subthreshold Power Supply.	PATMOS	2007	DBLP DOI BibTeX RDF
24	Naofumi Homma, Katsuhiko Degawa, Takafumi Aoki, Tatsuo Higuchi 0001	Algorithm-Level Optimization of Multiple-Valued Arithmetic Circuits Using Counter Tree Diagrams.	ISMVL	2007	DBLP DOI BibTeX RDF
24	Sheng Sun, Carl Sechen	Post-layout comparison of high performance 64b static adders in energy-delay space.	ICCD	2007	DBLP DOI BibTeX RDF
24	A. Neslin Ismailoglu, Murat Askar	Application of Bit-level Pipelining to Delay Insensitive Null Convention Adders.	ISCAS	2007	DBLP DOI BibTeX RDF
24	R. Mahesh 0001, A. Prasad Vinod 0001	An Architecture For Integrating Low Complexity and Reconfigurability for Channel filters in Software Defined Radio Receivers.	ISCAS	2007	DBLP DOI BibTeX RDF
24	Jaume Abella 0001, Xavier Vera, Osman S. Unsal, Oguz Ergin, Antonio González 0001	Fuse: A Technique to Anticipate Failures due to Degradation in ALUs.	IOLTS	2007	DBLP DOI BibTeX RDF
24	Ismo Hänninen, Jarmo Takala	Robust Adders Based on Quantum-Dot Cellular Automata.	ASAP	2007	DBLP DOI BibTeX RDF
24	Sybille Hellebrand, Christian G. Zoellin, Hans-Joachim Wunderlich, Stefan Ludwig, Torsten Coym, Bernd Straube	A Refined Electrical Model for Particle Strikes and its Impact on SEU Prediction.	DFT	2007	DBLP DOI BibTeX RDF
24	Guadalupe Miñana, José Ignacio Hidalgo, Oscar Garnica, Juan Lanchares, José Manuel Colmenar, Sonia López	A Technique to Reduce Static and Dynamic Power of Functional Units in High-Performance Processors.	PATMOS	2006	DBLP DOI BibTeX RDF
24	Haridimos T. Vergos, Costas Efstathiou	Novel Modulo 2n + 1 Multipliers.	DSD	2006	DBLP DOI BibTeX RDF
24	Fei Xu, Chip-Hong Chang, Ching-Chuen Jong	A new integrated approach to the design of low-complexity FIR filters.	ISCAS	2006	DBLP DOI BibTeX RDF
24	Johannes Grad, James E. Stine	Low power binary addition using carry increment adders.	ISCAS	2006	DBLP DOI BibTeX RDF
24	Massimo Alioto, Gaetano Palumbo	Delay uncertainty due to supply variations in static and dynamic full adders.	ISCAS	2006	DBLP DOI BibTeX RDF
24	Hayssam El-Razouk, Zine Abid	A New Transistor-Redundant Voter for Defect-Tolerant Digital Circuits.	CCECE	2006	DBLP DOI BibTeX RDF
24	Aggelos Kiayias, Michael Korman, David Walluck	An Internet Voting System Supporting User Privacy.	ACSAC	2006	DBLP DOI BibTeX RDF
24	Kavallur Gopi Smitha, Hossam A. H. Fahmy, A. Prasad Vinod 0001	Redundant Adders Consume Less Energy.	APCCAS	2006	DBLP DOI BibTeX RDF
24	A. Prasad Vinod 0001, Edmund Ming-Kit Lai	An efficient coefficient-partitioning algorithm for realizing low-complexity digital filters.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
24	Rumi Zhang, Wei Wang 0003, Konrad Walus, Graham A. Jullien	Performance comparison of quantum-dot cellular automata adders.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
24	Cor Meenderinck, Sorin Cotofana, Casper Lageweg	High Radix Addition Via Conditional Charge Transport in Single Electron Tunneling Technology.	ASAP	2005	DBLP DOI BibTeX RDF
24	Luigi Dadda, Marco Macchetti, Jeff Owen	The Design of a High Speed ASIC Unit for the Hash Function SHA-256 (384, 512).	DATE	2004	DBLP DOI BibTeX RDF
24	Y. Ibrahim, Graham A. Jullien, William C. Miller	Ultra Low Noise Signed Digit Arithmetic using Cellular Neural Networks.	IWSOC	2004	DBLP DOI BibTeX RDF
24	Michael Nicolaidis	Carry checking/parity prediction adders and ALUs.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
24	Haridimos T. Vergos, Dimitris Nikolos, Maciej Bellos, Costas Efstathiou	Deterministic BIST for RNS Adders.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	deterministic and pseudorandom tests, formal test sets, Built-In Self-Test, Residue Number System
24	Ronald D. Blanton, John P. Hayes	On the properties of the input pattern fault model.	ACM Trans. Design Autom. Electr. Syst.	2003	DBLP DOI BibTeX RDF	fault testing, testing digital circuits, ATPG, fault models, faults, defects
24	Ernest Jamro, Kazimierz Wiatr	Genetic Programming in FPGA Implementation of Addition as a Part of the Convolution.	DSD	2001	DBLP DOI BibTeX RDF
24	Ajay Naini, Atul Dhablania, Warren James, Debjit Das Sarma	1-GHz HAL SPARC64 Dual Floating Point Unit with RAS Features.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
24	Javier D. Bruguera, Tomás Lang	Using the Reverse-Carry Approach for Double Datapath Floating-Point Addition.	IEEE Symposium on Computer Arithmetic	2001	DBLP DOI BibTeX RDF
24	Ioannis M. Thoidis, Dimitrios Soudris, Jean-Marc Fernandez, Adonios Thanailakis	The circuit design of multiple-valued logic voltage-mode adders.	ISCAS (4)	2001	DBLP DOI BibTeX RDF
24	Christian Pacha, Uwe Auer, Christian Burwick, Peter Glösekötter, Andreas Brennemann, Werner Prost, Franz-Josef Tegude, Karl F. Goser	Threshold logic circuit design of parallel adders using resonant tunneling devices.	IEEE Trans. Very Large Scale Integr. Syst.	2000	DBLP DOI BibTeX RDF
24	Keshab K. Parhi	Low-energy CSMT carry generators and binary adders.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
24	Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.	Bit-level arithmetic optimization for carry-save additions.	ICCAD	1999	DBLP DOI BibTeX RDF
24	Chetana Nagendra, Robert Michael Owens, Mary Jane Irwin	Power-delay characteristics of CMOS adders.	IEEE Trans. Very Large Scale Integr. Syst.	1994	DBLP DOI BibTeX RDF
24	Miriam Leeser	Reasoning about the function and timing of integrated circuits with interval temporal logic.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
23	Sang-Hun Yoon, Jin-Doo Jeong, Jong-Wha Chong	An area reduction method for digital filter using redundancy of SD number system.	ICUIMC	2009	DBLP DOI BibTeX RDF	adder sharing, flattened coefficient, architecture, digital filter
23	Akihiro Hirosaki, Masatomo Miura, Atsushi Matsumoto, Takahiro Hanyu	Vth-Variation Compensation of Multiple-Valued Current-Mode Circuit Using TMR Devices.	ISMVL	2008	DBLP DOI BibTeX RDF	differential-pair circuit, radix-2 signed-digit adder, reliability
23	S. Dabas, Ning Dong 0002, Jaijeet S. Roychowdhury	Automated Extraction of Accurate Delay/Timing Macromodels of Digital Gates and Latches using Trajectory Piecewise Methods.	ASP-DAC	2007	DBLP DOI BibTeX RDF	gate delay modelling, accurate delay/timing macromodels, digital gates, trajectory-piecewise automated nonlinear macromodelling methods, mixed-signal/RF domain, SPICE-level netlists, transparent retargetability, NAND gates, NOR gates, sequential latch, latches, full adder, current-source models, XOR gates
23	Taeko Matsunaga, Yusuke Matsunaga	Area minimization algorithm for parallel prefix adders under bitwise delay constraints.	ACM Great Lakes Symposium on VLSI	2007	DBLP DOI BibTeX RDF	arithmetic synthesis, dynamic programming, parallel prefix adder
23	Bonseok Koo, Dongwook Lee, Gwonho Ryu, Taejoo Chang, Sangjin Lee 0002	High-Speed RSA Crypto-processor with Radix-4 Modular Multiplication and Chinese Remainder Theorem.	ICISC	2006	DBLP DOI BibTeX RDF	Booth’s algorithm, RSA, Chinese Remainder Theorem, Montgomery multiplication, Carry Save Adder
23	Amir Fijany, Farrokh Vatan, Mohammad M. Mojarradi, Nikzad Benny Toomarian, Benjamin J. Blalock, Kerem Akarvardar, Sorin Cristoloveanu, Pierre Gentil	The G4-FET: a universal and programmable logic gate.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	G4-FET, programmable gate, universal logic gate, full adder
23	Ki-seon Cho, Jong-on Park, Jin-seok Hong, Goang-Seog Choi	54x54-bit radix-4 multiplier based on modified booth algorithm.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	compressor, adder, multiplier, booth encoder, wallace tree
23	Hiromitsu Kimura, Takahiro Hanyu, Michitaka Kameyama	Multiple-Valued Logic-in-Memory VLSI Based on Ferroelectric Capacitor Storage and Charge Addition.	ISMVL	2002	DBLP DOI BibTeX RDF	Ferroelectric capacitor, multiple-valued current-mode logic circuit, arithmetic operation, full adder
23	Jongsun Park 0001, Woopyo Jeong, Hunsoo Choo, Hamid Mahmoodi-Meimand, Yongtao Wang, Kaushik Roy 0001	High performance and low power FIR filter design based on sharing multiplication.	ISLPED	2002	DBLP DOI BibTeX RDF	FIR filter design, computation sharing, conditional capture flip-flop, high performance and low power carry select adder
23	Junhyung Um, Taewhan Kim	Layout-aware synthesis of arithmetic circuits.	DAC	2002	DBLP DOI BibTeX RDF	layout, high performance, carry-save-adder
23	Shugang Wei, Kensuke Shimizu	Error Detection of Arithmetic Circuits Using a Residue Checker with Signed-Digit Number System.	DFT	2001	DBLP DOI BibTeX RDF	residue addition, residue multiplication, signed-digit(SD) number representation, SD adder, error detection, residue number system(RNS)
23	Takahiro Hanyu, Tsukasa Ike, Michitaka Kameyama	Low-Power Dual-Rail Multiple-Valued Current-Mode Logic Circuit Using Multiple Input-Signal Levels.	ISMVL	2000	DBLP DOI BibTeX RDF	dual-rail multiple-valued current-mode logic circuit, two supply voltages, differential-pair circuit, radix-2 signed-digit adder
23	Debatosh Debnath, Tsutomu Sasao	Multiple-Valued Minimization to Optimize PLAs with Output EXOR Gates.	ISMVL	1999	DBLP DOI BibTeX RDF	Three-level network, programmable logic array, adder, multiple-valued logic, logic minimization
23	Seiji Kajihara, Tsutomu Sasao	On the Adders with Minimum Tests.	Asian Test Symposium	1997	DBLP DOI BibTeX RDF	ripple carry adder, minimum test set, test generation, stuck-at fault, carry look-ahead adders
23	R. D. (Shawn) Blanton, John P. Hayes	Design of a fast, easily testable ALU.	VTS	1996	DBLP DOI BibTeX RDF	ALU, adder design, L-testable design, level-testable, carry-lookahead addition, fault diagnosis, logic testing, integrated circuit testing, automatic testing, digital arithmetic, integrated circuit design, adders, logic arrays, test patterns, area overhead, functional faults, carry logic, arithmetic-logic unit, 8 bit
23	Menghui Zheng, Alexander Albicki	Low power and high speed multiplication design through mixed number representations.	ICCD	1995	DBLP DOI BibTeX RDF	high speed multiplication, mixed number representations, low power multiplication, reduced switching, Sign-Magnitude, Redundant Binary adder, Booth decoder, Carry-Propagation-Free, digital arithmetic, VLSI architecture, redundant number systems, Partial Products
23	William C. Athas, Nestoras Tzartzanis	Energy recovery for low-power CMOS.	ARVLSI	1995	DBLP DOI BibTeX RDF	bootstrap circuits, low-power CMOS, energy-recovery techniques, voltage swing, transition time, MOS device parameters, adder designs, VLSI, mathematical model, bootstrapping, adders, CMOS logic circuits, CMOS logic circuits, power dissipation, integrated circuit modelling, SOI
21	Myungsu Choi, Minsu Choi	Scalability of Globally Asynchronous QCA (Quantum-Dot Cellular Automata) Adder Design.	J. Electron. Test.	2008	DBLP DOI BibTeX RDF	QCA (quantum-dot cellular automata), Asynchronous architecture, Layout timing problem, Scalability, Robustness
21	Swaroop Ghosh, Patrick Ndai, Kaushik Roy 0001	A Novel Low Overhead Fault Tolerant Kogge-Stone Adder Using Adaptive Clocking.	DATE	2008	DBLP DOI BibTeX RDF
21	Andre Guntoro, Manfred Glesner	High-performance fpga-based floating-point adder with three inputs.	FPL	2008	DBLP DOI BibTeX RDF
21	Gian Carlo Cardarilli, Luca Di Nunzio, Marco Re, Alberto Nannarelli	ADAPTO: full-adder based reconfigurable architecture for bit level operations.	ISCAS	2008	DBLP DOI BibTeX RDF
21	Sreehari Veeramachaneni, Kirthi M. Krishna, Prateek G. V., Subroto S., Bharat S., M. B. Srinivas	A Novel Carry-Look Ahead Approach to a Unified BCD and Binary Adder/Subtractor.	VLSI Design	2008	DBLP DOI BibTeX RDF
21	Kyosun Kim, Kaijie Wu 0001, Ramesh Karri	The Robust QCA Adder Designs Using Composable QCA Building Blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
21	Lasse Kiviluoto, Patric R. J. Östergård	New Uniquely Decodable Codes for the T-User Binary Adder Channel With 3<=T<=5.	IEEE Trans. Inf. Theory	2007	DBLP DOI BibTeX RDF
21	Oscar Gustafsson	A Difference Based Adder Graph Heuristic for Multiple Constant Multiplication Problems.	ISCAS	2007	DBLP DOI BibTeX RDF
21	Bálint Laczay	Coding for the Multiple-Access Adder Channel.	GTIT-C	2006	DBLP DOI BibTeX RDF
21	Ricardo C. Goncalves da Silva, Henri Boudinov, Luigi Carro	A low power high performance CMOS voltage-mode quaternary full adder.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
21	los Roberto Mingoto Jr.	A Quaternary Half-Adder Using Current-Mode Operation with Bipolar Transistors.	ISMVL	2006	DBLP DOI BibTeX RDF
21	Fatemeh Kashfi, Seid Mehdi Fakhraie	Implementation of a high-speed low-power 32-bit adder in 70nm technology.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Yu-Ting Kuo, Tay-Jyi Lin, Yi Cho, Chih-Wei Liu, Chein-Wei Jen	Programmable FIR filter with adder-based computing engine.	ISCAS	2006	DBLP DOI BibTeX RDF
21	Ali Bastani, Charles A. Zukowski	A Low-Leakage High-Speed Monotonic Static CMOS 64b Adder in a Dual Gate Oxide 65-nm CMOS Technology.	ISQED	2006	DBLP DOI BibTeX RDF
21	Yi Wang 0016, Douglas L. Maskell, Jussipekka Leiwo, Thambipillai Srikanthan	Unified Signed-Digit Number Adder for RSA and ECC Public-key Cryptosystems.	APCCAS	2006	DBLP DOI BibTeX RDF
21	Liming Xiu, Zhihong You	A "Flying-Adder" frequency synthesis architecture of reducing VCO stages.	IEEE Trans. Very Large Scale Integr. Syst.	2005	DBLP DOI BibTeX RDF
21	M. Mattas, Patric R. J. Östergård	A New Bound for the Zero-Error Capacity Region of the Two-User Binary Adder Channel.	IEEE Trans. Inf. Theory	2005	DBLP DOI BibTeX RDF
21	Rui Tang, Fengming Zhang, Yong-Bin Kim	QCA-based nano circuits design [adder design example].	ISCAS (3)	2005	DBLP DOI BibTeX RDF
21	Shahnam Khabiri, Maitham Shams	An MCML four-bit ripple-carry adder design in 1 GHz range.	ISCAS (2)	2005	DBLP DOI BibTeX RDF
21	Dilip P. Vasudevan, Parag K. Lala	A Technique for Modular Design of Self-Checking Carry-Select Adder.	DFT	2005	DBLP DOI BibTeX RDF
21	Yuanzhong Wan, Maitham Shams	Optimization of Mixed Logic Circuits with Application to a 64-Bit Static Adder.	VLSI Design	2005	DBLP DOI BibTeX RDF
21	Dave A. Berque, Ian Serlin, Atanas Vlahov	A brief water excursion: introducing computer organization students to a water driven 1-bit half-adder.	ACM SIGCSE Bull.	2004	DBLP DOI BibTeX RDF	computer organization pedagogy, water-based computing
21	Turgay Temel, Avni Morgül, Nizamettin Aydin	A Novel Signed Higher-Radix Full-Adder Algorithm and Implementation with Current-Mode Multi-Valued Logic Circuits.	DSD	2004	DBLP DOI BibTeX RDF
21	Valdemar Cardoso da Rocha Jr., Maria de Lourdes M. G. Alcoforado	Trellis Code Construction for the 2-User Binary Adder Channel.	ICT	2004	DBLP DOI BibTeX RDF
21	Hafiz Md. Hasan Babu, Md. Rafiqul Islam 0001, Syed Mostahed Ali Chowdhury, Ahsan Raja Chowdhury	Synthesis of Full-Adder Circuit Using Reversible Logic.	VLSI Design	2004	DBLP DOI BibTeX RDF
21	Stefania Perri, Pasquale Corsonello, Giuseppe Cocorullo	A high-speed energy-efficient 64-bit reconfigurable binary adder.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
21	Costas Efstathiou, Haridimos T. Vergos, Dimitris Nikolos	Modulo 2n±1 Adder Design Using Select-Prefix Blocks.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	modulo 2n± 1 adders, select-prefix adders, computer arithmetic, VLSI architectures
21	Kuan Zhou, Michael Chu, Chao You, Jong-Ru Guo, Channakeshav, John Mayega, John F. McDonald 0001, Russell P. Kraft, Bryan S. Goda	A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme.	FPGA	2003	DBLP DOI BibTeX RDF
21	Hwang-Cherng Chow, I-Chyn Wey	A 3.3 V 1 GHz low-latency pipelined Booth multiplier with new Manchester carry-pass adder.	ISCAS (5)	2003	DBLP DOI BibTeX RDF
21	Whitney J. Townsend, Jacob A. Abraham, Parag K. Lala	On-Line Error Detecting Constant Delay Adder.	IOLTS	2003	DBLP DOI BibTeX RDF
21	Bhushan A. Shinkre, James E. Stine	A pipelined clock-delayed domino carry-lookahead adder.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF
21	Haridimos T. Vergos, Costas Efstathiou, Dimitris Nikolos	Diminished-One Modulo 2n+1 Adder Design.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Modulo $big. 2^{rm n}+1bigr.$ addition, carry look-ahead addition, diminished-one number representation, VLSI adders, parallel-prefix adders