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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 455 occurrences of 299 keywords
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Results
Found 537 publication records. Showing 537 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
14 | Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane |
Fast exploration of bus-based communication architectures at the CCATB abstraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 7(2), pp. 22:1-22:32, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
performance exploration, System-on-chip, transaction-level modeling, communication architecture, on-chip bus |
14 | Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, Donald E. Thomas |
Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 1144-1149, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
13 | Shu-Hsuan Chou, Chi-Neng Wen, Yan-Ling Liu, Tien-Fu Chen |
VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 535-540, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
13 | George Hadjiyiannis, Srinivas Devadas |
Techniques for accurate performance evaluation in architecture exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 11(4), pp. 601-615, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
13 | Sumit Ahuja, Deepak Mathaikutty, Gaurav Singh 0006, Joe Stetzer, Sandeep K. Shukla, Ajit Dingankar |
Power estimation methodology for a high-level synthesis framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 10th International Symposium on Quality of Electronic Design (ISQED 2009), 16-18 March 2009, San Jose, CA, USA, pp. 541-546, 2009, IEEE Computer Society, 978-1-4244-2952-3. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Morteza Fayyazi, Laurent Kirsch |
Efficient simulation of oscillatory combinational loops. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 777-780, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
oscillatory combinational loops, emulation, functional verification |
11 | Colin J. Ihrig, Rami G. Melhem, Alex K. Jones |
Automated modeling and emulation of interconnect designs for many-core chip multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 431-436, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
simulation, interconnection network, emulation, multi-core, many-core |
11 | Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiroaki Honda, Koji Inoue, Kazuaki J. Murakami |
A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 564-569, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
11 | Trevor Meyerowitz, Alberto L. Sangiovanni-Vincentelli, Mirko Sauermann, Dominik Langen |
Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 276-279, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
11 | Jürgen Schnerr, Oliver Bringmann 0001, Alexander Viehl, Wolfgang Rosenstiel |
High-performance timing simulation of embedded software. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 290-295, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
software timing, virtual prototypes, simulation acceleration |
11 | Srinivasan Murali, Luca Benini, Giovanni De Micheli |
An Application-Specific Design Methodology for On-Chip Crossbar Generation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7), pp. 1283-1296, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
11 | Tejas Karkhanis, James E. Smith 0001 |
Automated design of application specific superscalar processors: an analytical approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 34th International Symposium on Computer Architecture (ISCA 2007), June 9-13, 2007, San Diego, California, USA, pp. 402-411, 2007, ACM, 978-1-59593-706-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
performance model, analytical model, design optimization, energy model, application specific processors |
11 | Pablo García Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli |
A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI-SoC ![In: IFIP VLSI-SoC 2006, IFIP WG 10.5 International Conference on Very Large Scale Integration of System-on-Chip, Nice, France, 16-18 October 2006, pp. 140-145, 2006, IEEE. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | Emmanuel Viaud, François Pêcheux, Alain Greiner |
An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Proceedings of the Conference on Design, Automation and Test in Europe, DATE 2006, Munich, Germany, March 6-10, 2006, pp. 94-99, 2006, European Design and Automation Association, Leuven, Belgium, 3-9810801-1-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
11 | David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias |
A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 43rd Design Automation Conference, DAC 2006, San Francisco, CA, USA, July 24-28, 2006, pp. 618-623, 2006, ACM, 1-59593-381-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
thermal studies, FPGA, emulation, MPSoC |
11 | Lucanus J. Simonson, Lei He 0001 |
Micro-architecture Performance Estimation by Formula. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAMOS ![In: Embedded Computer Systems: Architectures, Modeling, and Simulation 5th International Workshop, SAMOS 2005, Samos, Greece, July 18-20, 2005, Proceedings, pp. 192-201, 2005, Springer, 3-540-26969-X. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie |
Unbounded Transactional Memory. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 316-327, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
11 | Tao Li 0006, Lizy Kurian John |
Run-time modeling and estimation of operating system power consumption. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the International Conference on Measurements and Modeling of Computer Systems, SIGMETRICS 2003, June 9-14, 2003, San Diego, CA, USA, pp. 160-171, 2003, ACM, 1-58113-664-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
low power, operating system, power estimation |
11 | Spiridon Nikolaidis 0001, Nikolaos Kavvadias, Periklis Neofotistos, K. Kosmatopoulos, Theodore Laopoulos, Labros Bisdounis |
Instrumentation Set-up for Instruction Level Power Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit Design. Power and Timing Modeling, Optimization and Simulation, 12th International Workshop, PATMOS 2002, Seville, Spain, September 11-13, 2002, pp. 71-80, 2002, Springer, 3-540-44143-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
11 | Allan Snavely, Laura Carrington, Nicole Wolter, Jesús Labarta, Rosa M. Badia, Avi Purkayastha |
A framework for performance modeling and prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the 2002 ACM/IEEE conference on Supercomputing, Baltimore, Maryland, USA, November 16-22, 2002, CD-ROM, pp. 24:1-24:17, 2002, IEEE Computer Society, 0-7695-1524-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
10 | Eric Cheung, Harry Hsieh, Felice Balarin |
Fast and accurate performance simulation of embedded software for MPSoC. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 552-557, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
10 | Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar |
Multi-granularity sampling for simulating concurrent heterogeneous applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CASES ![In: Proceedings of the 2008 International Conference on Compilers, Architecture, and Synthesis for Embedded Systems, CASES 2008, Atlanta, GA, USA, October 19-24, 2008, pp. 217-226, 2008, ACM. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
simulation sampling, multiprocessor system-on-chip, simulation acceleration |
10 | Mariko Sakamoto, Larry Brisson, Akira Katsuno, Aiichiro Inoue, Yasunori Kimura |
Reverse Tracer: A Software Tool for Generating Realistic Performance Test Programs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: Proceedings of the Eighth International Symposium on High-Performance Computer Architecture (HPCA'02), Boston, Massachusettes, USA, February 2-6, 2002, pp. 81-91, 2002, IEEE Computer Society, 0-7695-1525-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Multi-user Interactive Workload, System Level Performance, Instruction Trace, Software Tool, Logic Simulator, Hardware Design, Performance Test |
9 | Xi E. Chen, Tor M. Aamodt |
A first-order fine-grained multithreaded throughput model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 15th International Conference on High-Performance Computer Architecture (HPCA-15 2009), 14-18 February 2009, Raleigh, North Carolina, USA, pp. 329-340, 2009, IEEE Computer Society, 978-1-4244-2932-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
9 | Yonghyun Hwang, Samar Abdi, Daniel Gajski |
Cycle-approximate Retargetable Performance Estimation at the Transaction Level. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: Design, Automation and Test in Europe, DATE 2008, Munich, Germany, March 10-14, 2008, pp. 3-8, 2008, ACM, 978-3-9810801-3-1. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
9 | Chung-Fu Kao, Ing-Jer Huang, Chi-Hung Lin |
An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 477-482, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
9 | Wonbok Lee, Kimish Patel, Massoud Pedram |
B2Sim: : a fast micro-architecture simulator based on basic block characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 199-204, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
basic block, micro-architecture simulation, program behavior |
9 | Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar |
Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 298-303, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
floorplanning, microarchitecture, transient analysis |
9 | Ben L. Titzer, Daniel K. Lee, Jens Palsberg |
Avrora: scalable sensor network simulation with precise timing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSN ![In: Proceedings of the Fourth International Symposium on Information Processing in Sensor Networks, IPSN 2005, April 25-27, 2005, UCLA, Los Angeles, California, USA, pp. 477-482, 2005, IEEE, 0-7803-9202-7. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor |
A Complete Network-On-Chip Emulation Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 246-251, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Hongkyu Kim, D. Scott Wills, Linda M. Wills |
Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), CD-ROM / Abstracts Proceedings, 4-8 April 2005, Denver, CO, USA, 2005, IEEE Computer Society, 0-7695-2312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Sibin Mohan, Frank Mueller 0001, David B. Whalley, Christopher A. Healy |
Timing Analysis for Sensor Network Nodes of the Atmega Processor Family. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Real-Time and Embedded Technology and Applications Symposium ![In: 11th IEEE Real-Time and Embedded Technology and Applications Symposium (RTAS 2005), 7-10 March 2005, San Francisco, CA, USA, pp. 405-414, 2005, IEEE Computer Society, 0-7695-2302-1. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor |
A novel approach for network on chip emulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (3) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 2365-2368, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Jia Yu 0008, Jun Yang 0002, Shaojie Chen, Yan Luo, Laxmi N. Bhuyan |
Enhancing Network Processor Simulation Speed with Statistical Input Sampling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HiPEAC ![In: High Performance Embedded Architectures and Compilers, First International Conference, HiPEAC 2005, Barcelona, Spain, November 17-18, 2005, Proceedings, pp. 68-83, 2005, Springer, 3-540-30317-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
9 | Uwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael Thies |
Feedback driven instruction-set extension. ![Search on Bibsonomy](Pics/bibsonomy.png) |
LCTES ![In: Proceedings of the 2004 ACM SIGPLAN/SIGBED Conference on Languages, Compilers, and Tools for Embedded Systems (LCTES'04), Washington, DC, USA, June 11-13, 2004, pp. 126-135, 2004, ACM, 1-58113-806-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
simulator generation, encryption, network processor, codesign, instruction-set extensions, compiler generation |
9 | Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye, David Duarte |
Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 52(1), pp. 59-76, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
simulation, optimizations, energy models, Energy estimation |
9 | Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar |
Accurate Power Macro-modeling Techniques for Complex RTL Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 14th International Conference on VLSI Design (VLSI Design 2001), 3-7 January 2001, Bangalore, India, pp. 235-241, 2001, IEEE Computer Society, 0-7695-0831-6. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
8 | Georgios Keramidas, Vasileios Spiliopoulos, Stefanos Kaxiras |
Interval-based models for run-time DVFS orchestration in superscalar processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 7th Conference on Computing Frontiers, 2010, Bertinoro, Italy, May 17-19, 2010, pp. 287-296, 2010, ACM, 978-1-4503-0044-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance and power modeling, superscalar out-of-order processors, dynamic voltage and frequency scaling |
8 | Zhong-Yi Jin, Rajesh K. Gupta 0001 |
Improving the speed and scalability of distributed simulations of sensor networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSN ![In: Proceedings of the 8th International Conference on Information Processing in Sensor Networks, IPSN 2009, April 13-16, 2009, San Francisco, California, USA, pp. 169-180, 2009, IEEE Computer Society, 978-1-4244-5108-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
8 | Hyunwoo Joe, Jonghyuk Lee, Duk-Kyun Woo, Pyeong-Soo Mah, Hyungshin Kim |
Demo abstract: A high-fidelity sensor network simulator using accurate CC2420 model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPSN ![In: Proceedings of the 8th International Conference on Information Processing in Sensor Networks, IPSN 2009, April 13-16, 2009, San Francisco, California, USA, pp. 429-430, 2009, IEEE Computer Society, 978-1-4244-5108-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
8 | Zhong-Yi Jin, Rajesh Gupta 0001 |
LazySync: A New Synchronization Scheme for Distributed Simulation of Sensor Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DCOSS ![In: Distributed Computing in Sensor Systems, 5th IEEE International Conference, DCOSS 2009, Marina del Rey, CA, USA, June 8-10, 2009. Proceedings, pp. 103-116, 2009, Springer, 978-3-642-02084-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
8 | Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel |
A Flexible Framework for Communication Evaluation in SoC Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 36(5), pp. 457-477, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Interconnect simulator, Network on chip, Trace based simulation, Multiprocessor simulator |
8 | Tarek M. Taha, D. Scott Wills |
An Instruction Throughput Model of Superscalar Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(3), pp. 389-403, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
Modeling techniques, Pipeline processors, Modeling of computer architecture |
8 | Hun Jung, Miao Ju, Hao Che, Zhijun Wang 0001 |
A Fast Performance Analysis Tool for Multicore, Multithreaded Communication Processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HASE ![In: 11th IEEE High Assurance Systems Engineering Symposium, HASE 2008, Nanjing, China, December 3 - 5, 2008, pp. 135-144, 2008, IEEE Computer Society, 978-0-7695-3482-4. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Abbas Eslami Kiasari, Dara Rahmati, Hamid Sarbazi-Azad, Shaahin Hessabi |
A Markovian Performance Model for Networks-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PDP ![In: 16th Euromicro International Conference on Parallel, Distributed and Network-Based Processing (PDP 2008), 13-15 February 2008, Toulouse, France, pp. 157-164, 2008, IEEE Computer Society, 978-0-7695-3089-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Bin Li 0008, Lu Peng 0001, Balachandran Ramadass |
Efficient mart-aided modeling for microarchitecture design space exploration and performance prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2008, Annapolis, MD, USA, June 2-6, 2008, pp. 439-440, 2008, ACM, 978-1-60558-005-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
MART-aided models, performance prediction, design space exploration |
8 | Youngjin Cho, Younghyun Kim 0001, Sangyoung Park, Naehyuck Chang |
System-level power estimation using an on-chip bus performance monitoring unit. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 149-154, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
8 | Zhonglei Wang, Antonio Sánchez, Andreas Herkersdorf |
SciSim: a software performance estimation framework using source code instrumentation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WOSP ![In: Proceedings of the 7th International Workshop on Software and Performance, WOSP 2008, Princeton, NJ, USA, June 23-26, 2008, pp. 33-42, 2008, ACM, 978-1-59593-873-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
debugging information, software performance estimation, source code instrumentation, microarchitecture |
8 | Ioana Burcea, Stephen Somogyi, Andreas Moshovos, Babak Falsafi |
Predictor virtualization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASPLOS ![In: Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, ASPLOS 2008, Seattle, WA, USA, March 1-5, 2008, pp. 157-167, 2008, ACM, 978-1-59593-958-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
predictor virtualization, caches, metadata, memory hierarchy |
8 | Lerong Cheng, Fei Li 0003, Yan Lin 0001, Phoebe Wong, Lei He 0001 |
Device and Architecture Cooptimization for FPGA Power Reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7), pp. 1211-1221, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Antoine Fraboulet, Tanguy Risset |
Master Interface for On-chip Hardware Accelerator Burst Communications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. VLSI Signal Process. ![In: J. VLSI Signal Process. 49(1), pp. 73-85, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
SoC simulation, system on chip, high level synthesis, interface generation |
8 | Zoltán Herczeg, Ákos Kiss 0001, Daniel Schmidt 0001, Norbert Wehn, Tibor Gyimóthy |
XEEMU: An Improved XScale Power Simulator. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 17th International Workshop, PATMOS 2007, Gothenburg, Sweden, September 3-5, 2007, Proceedings, pp. 300-309, 2007, Springer, 978-3-540-74441-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
8 | Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser |
Massively parallel processing on a chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Conf. Computing Frontiers ![In: Proceedings of the 4th Conference on Computing Frontiers, 2007, Ischia, Italy, May 7-9, 2007, pp. 277-286, 2007, ACM, 978-1-59593-683-7. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
MasPar, mppSoC, SoC, SIMD, system-on-a-chip, massively parallelism |
8 | Chan-Hao Chang, Diana Marculescu |
Design and Analysis of a Low Power VLIW DSP Core. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISVLSI ![In: 2006 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2006), 2-3 March 2006, Karlsruhe, Germany, pp. 167-172, 2006, IEEE Computer Society, 0-7695-2533-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser |
Estimating Energy Consumption for an MPSoC Architectural Exploration. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2006, 19th International Conference, Frankfurt/Main, Germany, March 13-16, 2006, Proceedings, pp. 298-310, 2006, Springer, 3-540-32765-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Gi-Ho Park, Sung Woo Chung, Han-Jong Kim, Jung-Bin Im, Jung-Wook Park, Shin-Dug Kim, Sung-Bae Park |
Practice and Experience of an Embedded Processor Core Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCC ![In: High Performance Computing and Communications, Second International Conference, HPCC 2006, Munich, Germany, September 13-15, 2006, Proceedings, pp. 621-630, 2006, Springer, 3-540-39368-4. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Ram Srinivasan, Jeanine E. Cook, Olaf M. Lubeck |
Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 18th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2006), 17-20 October 2006, Ouro Preto, Minas Gerais, Brazil, pp. 107-116, 2006, IEEE Computer Society, 0-7695-2704-3. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
8 | Saurabh Sharma, Jesse G. Beu, Thomas M. Conte |
Spectral prefetcher: An effective mechanism for L2 cache prefetching. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Archit. Code Optim. ![In: ACM Trans. Archit. Code Optim. 2(4), pp. 423-450, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
absolute and differential domain, adaptive, memory, Prefetch, autocorrelation, frequency, L2 cache |
8 | Joshua L. Kihm, Daniel A. Connors |
Statistical Simulation of Multithreaded Architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 13th International Symposium on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2005), 27-29 September 2005, Atlanta, GA, USA, pp. 67-74, 2005, IEEE Computer Society, 0-7695-2458-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihin |
Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPCA ![In: 11th International Conference on High-Performance Computer Architecture (HPCA-11 2005), 12-16 February 2005, San Francisco, CA, USA, pp. 340-351, 2005, IEEE Computer Society, 0-7695-2275-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Eric Mercer, Michael D. Jones |
Model Checking Machine Code with the GNU Debugger. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPIN ![In: Model Checking Software, 12th International SPIN Workshop, San Francisco, CA, USA, August 22-24, 2005, Proceedings, pp. 251-265, 2005, Springer, 3-540-28195-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
8 | Mirko Loghi, Martin Letis, Luca Benini, Massimo Poncino |
Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, Chicago, Illinois, USA, April 17-19, 2005, pp. 276-281, 2005, ACM, 1-59593-057-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
low power, multiprocessor, system-on-chip, cache coherence |
8 | Lerong Cheng, Phoebe Wong, Fei Li 0003, Yan Lin 0001, Lei He 0001 |
Device and architecture co-optimization for FPGA power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 915-920, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Psim, Ptrace, powergating, FPGA, low power |
8 | Andrea Bona, Vittorio Zaccaria, Roberto Zafalon |
Low Effort, High Accuracy Network-on-Chip Power Macro Modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design, Power and Timing Modeling, Optimization and Simulation; 14th International Workshop, PATMOS 2004, Santorini, Greece, September 15-17, 2004, Proceedings, pp. 541-552, 2004, Springer, 3-540-23095-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Network-on-Chip power analysis, communication based low power design, system-level energy optimization |
8 | Lesley Shannon, Paul Chow |
Using reconfigurability to achieve real-time profiling for hardware/software codesign. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, FPGA 2004, Monterey, California, USA, February 22-24, 2004, pp. 190-199, 2004, ACM, 1-58113-829-6. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
FPGA, profiling, performance measurement, embedded processor, hardware/software codesign, soft processor |
8 | Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon |
Analyzing On-Chip Communication in a MPSoC Environment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 752-757, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger |
Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 300-305, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Jiangjiang Liu 0002, Krishnan Sundaresan, Nihar R. Mahapatra |
Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 11-13 October 2004, San Jose, CA, USA, Proceedings, pp. 458-463, 2004, IEEE Computer Society, 0-7695-2231-9. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Antoine Fraboulet, Tanguy Risset |
Efficient On-Chip Communications for Data-Flow IPs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASAP ![In: 15th IEEE International Conference on Application-Specific Systems, Architectures, and Processors (ASAP 2004), 27-29 September 2004, Galveston, TX, USA, pp. 293-303, 2004, IEEE Computer Society, 0-7695-2226-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
SoC simulation, system on chip, High level synthesis, interface generation |
8 | Yue Luo, Lizy Kurian John, Lieven Eeckhout |
Self-Monitored Adaptive Cache Warm-Up for Microprocessor Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBAC-PAD ![In: 16th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2004), 27-29 October 2004, Foz do Iguacu, Brazil, pp. 10-17, 2004, IEEE Computer Society, 0-7695-2240-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
8 | Hojun Shim, Yongsoo Joo, Yongseok Choi, Hyung Gyu Lee, Naehyuck Chang |
Low-energy off-chip SDRAM memory systems for embedded applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Embed. Comput. Syst. ![In: ACM Trans. Embed. Comput. Syst. 2(1), pp. 98-130, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Low power, memory system, SDRAM |
8 | Laura Carrington, Allan Snavely, Xiaofeng Gao 0003, Nicole Wolter |
A Performance Prediction Framework for Scientific Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
International Conference on Computational Science ![In: Computational Science - ICCS 2003, International Conference, Melbourne, Australia and St. Petersburg, Russia, June 2-4, 2003. Proceedings, Part III, pp. 926-935, 2003, Springer, 3-540-40196-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
8 | Matteo Dall'Osso, Gianluca Biccari, Luca Giovannini, Davide Bertozzi, Luca Benini |
xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 21st International Conference on Computer Design (ICCD 2003),VLSI in Computers and Processors, 13-15 October 2003, San Jose, CA, USA, Proceedings, pp. 536-, 2003, IEEE Computer Society, 0-7695-2025-1. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
8 | Tajana Simunic, Luca Benini, Giovanni De Micheli |
Energy-efficient design of battery-powered embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(1), pp. 15-28, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
8 | An-Chow Lai, Cem Fide, Babak Falsafi |
Dead-block prediction & dead-block correlating prefetchers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: Proceedings of the 28th Annual International Symposium on Computer Architecture, ISCA 2001, Göteborg, Sweden, June 30-July 4, 2001, pp. 144-154, 2001, ACM, 0-7695-1162-7. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
8 | David M. Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose |
Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PACS ![In: Power-Aware Computer Systems, First International Workshop, PACS 2000, Cambridge, MA, USA, November 12, 2000, Revised Papers, pp. 126-136, 2000, Springer, 3-540-42329-X. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
8 | Jonathan Combs, Candice Bechem Combs, John Paul Shen |
Mispredicted Path Cache Effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par '99 Parallel Processing, 5th International Euro-Par Conference, Toulouse, France, August 31 - September 3, 1999, Proceedings, pp. 1322-1331, 1999, Springer, 3-540-66443-2. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
6 | Kyle Rupnow, Jacob Adriaens, Wenyin Fu, Katherine Compton |
Accurately evaluating application performance in simulated hybrid multi-tasking systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 135-144, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
performance evaluation, hybrid systems, heterogeneous systems, full system simulation, multi-tasking systems |
6 | Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003 |
Intel nehalem processor core made FPGA synthesizable. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 3-12, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
intel nehalem, synthesizable core, fpga, emulator |
6 | Aparna Mandke Dani, Keshavan Varadarajan, Bharadwaj Amrutur, Y. N. Srikant |
Accelerating multi-core simulators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2010 ACM Symposium on Applied Computing (SAC), Sierre, Switzerland, March 22-26, 2010, pp. 2377-2382, 2010, ACM, 978-1-60558-639-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
chip multi-core, multi-core platform, timed petri-nets, instruction set simulator, cache simulator |
6 | Dave Christie, Jae-Woong Chung, Stephan Diestelhorst, Michael Hohmuth, Martin Pohlack, Christof Fetzer, Martin Nowack, Torvald Riegel, Pascal Felber, Patrick Marlier, Etienne Rivière |
Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EuroSys ![In: European Conference on Computer Systems, Proceedings of the 5th European conference on Computer systems, EuroSys 2010, Paris, France, April 13-16, 2010, pp. 27-40, 2010, ACM, 978-1-60558-577-2. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
transactional memory |
6 | Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John |
The virtual write queue: coordinating DRAM and last-level cache policies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France, pp. 72-82, 2010, ACM, 978-1-4503-0053-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache |
6 | Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson 0001, Krste Asanovic |
RAMP gold: an FPGA-based architecture simulator for multiprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 463-468, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
simulation, FPGA, multiprocessors |
6 | Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser |
Multiple clock and voltage domains for chip multi processors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), December 12-16, 2009, New York, New York, USA, pp. 459-468, 2009, ACM, 978-1-60558-798-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
clock domains, voltage domain, power management, DVFS, chip multi processor |
6 | Joseph Gebis, Leonid Oliker, John Shalf, Samuel Williams 0001, Katherine A. Yelick |
Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ARCS ![In: Architecture of Computing Systems - ARCS 2009, 22nd International Conference, Delft, The Netherlands, March 10-13, 2009. Proceedings, pp. 146-158, 2009, Springer, 978-3-642-00453-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
6 | Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, Yonghyun Hwang, Lochi Yu, Daniel Gajski |
Hardware-dependent software synthesis for many-core embedded systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 14th Asia South Pacific Design Automation Conference, ASP-DAC 2009, Yokohama, Japan, January 19-22, 2009, pp. 304-310, 2009, IEEE, 978-1-4244-2748-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
6 | Karthik Ganesan 0006, Deepak Panwar, Lizy K. John |
Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch, Memory and TLB Characteristics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SPEC Benchmark Workshop ![In: Computer Performance Evaluation and Benchmarking, SPEC Benchmark Workshop 2009, Austin, TX, USA, January 25, 2009. Proceedings, pp. 121-137, 2009, Springer, 978-3-540-93798-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
6 | Pierre Michaud |
Online compression of cache-filtered address traces. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2009, April 26-28, 2009, Boston, Massachusetts, USA, Proceedings, pp. 185-194, 2009, IEEE Computer Society, 978-1-4244-4184-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
6 | Dam Sunwoo, Joonsoo Kim, Derek Chiou |
QUICK: A flexible full-system functional model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPASS ![In: IEEE International Symposium on Performance Analysis of Systems and Software, ISPASS 2009, April 26-28, 2009, Boston, Massachusetts, USA, Proceedings, pp. 249-258, 2009, IEEE Computer Society, 978-1-4244-4184-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
6 | Nan Yuan, Yongbin Zhou, Guangming Tan, Junchao Zhang, Dongrui Fan |
High Performance Matrix Multiplication on Many Cores. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Euro-Par ![In: Euro-Par 2009 Parallel Processing, 15th International Euro-Par Conference, Delft, The Netherlands, August 25-28, 2009. Proceedings, pp. 948-959, 2009, Springer, 978-3-642-03868-6. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
6 | Muhammad Aqeel Wahlah, Kees Goossens |
Modeling reconfiguration in a FPGA with a hardwired network on chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-8, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
6 | Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam |
A DP-network for optimal dynamic routing in network-on-chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 119-128, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
optimal and sub-optimal routing, dynamic programming, network-on-chip, adaptive routing |
6 | Anders Sejer Tranberg-Hansen, Jan Madsen |
A compositional modelling framework for exploring MPSoC systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 1-10, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
MPSoC, system level design, performance estimation |
6 | Yanqin Yang, Meng Wang 0005, Zili Shao, Minyi Guo |
Dynamic Scratch-Pad Memory Management with Data Pipelining for Embedded Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CSE (2) ![In: Proceedings of the 12th IEEE International Conference on Computational Science and Engineering, CSE 2009, Vancouver, BC, Canada, August 29-31, 2009, pp. 358-365, 2009, IEEE Computer Society, 978-1-4244-5334-4. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
6 | James R. Green, Hanan Mahmoud, Michel Dumontier |
Modeling tryptic digestion on the Cell BE processor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCECE ![In: Proceedings of the 22nd Canadian Conference on Electrical and Computer Engineering, CCECE 2009, 3-6 May 2009, Delta St. John's Hotel and Conference Centre, St. John's, Newfoundland, Canada, pp. 701-705, 2009, IEEE, 978-1-4244-3508-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
6 | Edgar A. León, Rolf Riesen, Arthur B. Maccabe, Patrick G. Bridges |
Instruction-level simulation of a cluster at scale. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SC ![In: Proceedings of the ACM/IEEE Conference on High Performance Computing, SC 2009, November 14-20, 2009, Portland, Oregon, USA, 2009, ACM, 978-1-60558-744-8. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
6 | Susmit Biswas, Diana Franklin, Alan Savage, Ryan Dixon, Timothy Sherwood, Frederic T. Chong |
Multi-execution: multicore caching for data-similar executions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 164-173, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
data similar execution, multicore cache design, cmp |
6 | Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi |
Spatio-temporal memory streaming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCA ![In: 36th International Symposium on Computer Architecture (ISCA 2009), June 20-24, 2009, Austin, TX, USA, pp. 69-80, 2009, ACM, 978-1-60558-526-0. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
prefetching, spatial correlation, temporal correlation |
6 | Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Michela Milano, Luca Benini |
A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Int. J. Parallel Program. ![In: Int. J. Parallel Program. 36(1), pp. 3-36, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
scheduling, Integer Programming, Constraint Programming, MPSoCs, allocation |
6 | Jongsun Kim, Bo-Cheng Lai, Mau-Chung Frank Chang, Ingrid Verbauwhede |
A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 57(12), pp. 1714-1719, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
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