Search results for "cycle-accurate"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
14	Sudeep Pasricha, Nikil D. Dutt, Mohamed Ben-Romdhane	Fast exploration of bus-based communication architectures at the CCATB abstraction.	ACM Trans. Embed. Comput. Syst.	2008	DBLP DOI BibTeX RDF	performance exploration, System-on-chip, transaction-level modeling, communication architecture, on-chip bus
14	Alex Bobrek, Joshua J. Pieper, Jeffrey E. Nelson, JoAnn M. Paul, Donald E. Thomas	Modeling Shared Resource Contention Using a Hybrid Simulation/Analytical Approach.	DATE	2004	DBLP DOI BibTeX RDF
13	Shu-Hsuan Chou, Chi-Neng Wen, Yan-Ling Liu, Tien-Fu Chen	VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models.	ISQED	2009	DBLP DOI BibTeX RDF
13	George Hadjiyiannis, Srinivas Devadas	Techniques for accurate performance evaluation in architecture exploration.	IEEE Trans. Very Large Scale Integr. Syst.	2003	DBLP DOI BibTeX RDF
13	Sumit Ahuja, Deepak Mathaikutty, Gaurav Singh 0006, Joe Stetzer, Sandeep K. Shukla, Ajit Dingankar	Power estimation methodology for a high-level synthesis framework.	ISQED	2009	DBLP DOI BibTeX RDF
11	Morteza Fayyazi, Laurent Kirsch	Efficient simulation of oscillatory combinational loops.	DAC	2010	DBLP DOI BibTeX RDF	oscillatory combinational loops, emulation, functional verification
11	Colin J. Ihrig, Rami G. Melhem, Alex K. Jones	Automated modeling and emulation of interconnect designs for many-core chip multiprocessors.	DAC	2010	DBLP DOI BibTeX RDF	simulation, interconnection network, emulation, multi-core, many-core
11	Farhad Mehdipour, Hamid Noori, Bahman Javadi, Hiroaki Honda, Koji Inoue, Kazuaki J. Murakami	A combined analytical and simulation-based model for performance evaluation of a reconfigurable instruction set processor.	ASP-DAC	2009	DBLP DOI BibTeX RDF
11	Trevor Meyerowitz, Alberto L. Sangiovanni-Vincentelli, Mirko Sauermann, Dominik Langen	Source-Level Timing Annotation and Simulation for a Heterogeneous Multiprocessor.	DATE	2008	DBLP DOI BibTeX RDF
11	Jürgen Schnerr, Oliver Bringmann 0001, Alexander Viehl, Wolfgang Rosenstiel	High-performance timing simulation of embedded software.	DAC	2008	DBLP DOI BibTeX RDF	software timing, virtual prototypes, simulation acceleration
11	Srinivasan Murali, Luca Benini, Giovanni De Micheli	An Application-Specific Design Methodology for On-Chip Crossbar Generation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
11	Tejas Karkhanis, James E. Smith 0001	Automated design of application specific superscalar processors: an analytical approach.	ISCA	2007	DBLP DOI BibTeX RDF	performance model, analytical model, design optimization, energy model, application specific processors
11	Pablo García Del Valle, David Atienza, Ivan Magan, Javier Garcia Flores, Esther Andres Perez, Jose Manuel Mendias, Luca Benini, Giovanni De Micheli	A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework.	VLSI-SoC	2006	DBLP DOI BibTeX RDF
11	Emmanuel Viaud, François Pêcheux, Alain Greiner	An efficient TLM/T modeling and simulation environment based on conservative parallel discrete event principles.	DATE	2006	DBLP DOI BibTeX RDF
11	David Atienza, Pablo García Del Valle, Giacomo Paci, Francesco Poletti, Luca Benini, Giovanni De Micheli, Jose Manuel Mendias	A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip.	DAC	2006	DBLP DOI BibTeX RDF	thermal studies, FPGA, emulation, MPSoC
11	Lucanus J. Simonson, Lei He 0001	Micro-architecture Performance Estimation by Formula.	SAMOS	2005	DBLP DOI BibTeX RDF
11	C. Scott Ananian, Krste Asanovic, Bradley C. Kuszmaul, Charles E. Leiserson, Sean Lie	Unbounded Transactional Memory.	HPCA	2005	DBLP DOI BibTeX RDF
11	Tao Li 0006, Lizy Kurian John	Run-time modeling and estimation of operating system power consumption.	SIGMETRICS	2003	DBLP DOI BibTeX RDF	low power, operating system, power estimation
11	Spiridon Nikolaidis 0001, Nikolaos Kavvadias, Periklis Neofotistos, K. Kosmatopoulos, Theodore Laopoulos, Labros Bisdounis	Instrumentation Set-up for Instruction Level Power Modeling.	PATMOS	2002	DBLP DOI BibTeX RDF
11	Allan Snavely, Laura Carrington, Nicole Wolter, Jesús Labarta, Rosa M. Badia, Avi Purkayastha	A framework for performance modeling and prediction.	SC	2002	DBLP DOI BibTeX RDF
10	Eric Cheung, Harry Hsieh, Felice Balarin	Fast and accurate performance simulation of embedded software for MPSoC.	ASP-DAC	2009	DBLP DOI BibTeX RDF
10	Melhem Tawk, Khaled Z. Ibrahim, Smaïl Niar	Multi-granularity sampling for simulating concurrent heterogeneous applications.	CASES	2008	DBLP DOI BibTeX RDF	simulation sampling, multiprocessor system-on-chip, simulation acceleration
10	Mariko Sakamoto, Larry Brisson, Akira Katsuno, Aiichiro Inoue, Yasunori Kimura	Reverse Tracer: A Software Tool for Generating Realistic Performance Test Programs.	HPCA	2002	DBLP DOI BibTeX RDF	Multi-user Interactive Workload, System Level Performance, Instruction Trace, Software Tool, Logic Simulator, Hardware Design, Performance Test
9	Xi E. Chen, Tor M. Aamodt	A first-order fine-grained multithreaded throughput model.	HPCA	2009	DBLP DOI BibTeX RDF
9	Yonghyun Hwang, Samar Abdi, Daniel Gajski	Cycle-approximate Retargetable Performance Estimation at the Transaction Level.	DATE	2008	DBLP DOI BibTeX RDF
9	Chung-Fu Kao, Ing-Jer Huang, Chi-Hung Lin	An Embedded Multi-resolution AMBA Trace Analyzer for Microprocessor-based SoC Integration.	DAC	2007	DBLP DOI BibTeX RDF
9	Wonbok Lee, Kimish Patel, Massoud Pedram	B2Sim: : a fast micro-architecture simulator based on basic block characterization.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	basic block, micro-architecture simulation, program behavior
9	Vidyasagar Nookala, David J. Lilja, Sachin S. Sapatnekar	Temperature-aware floorplanning of microarchitecture blocks with IPC-power dependence modeling and transient analysis.	ISLPED	2006	DBLP DOI BibTeX RDF	floorplanning, microarchitecture, transient analysis
9	Ben L. Titzer, Daniel K. Lee, Jens Palsberg	Avrora: scalable sensor network simulation with precise timing.	IPSN	2005	DBLP DOI BibTeX RDF
9	Nicolas Genko, David Atienza, Giovanni De Micheli, Jose Manuel Mendias, Román Hermida, Francky Catthoor	A Complete Network-On-Chip Emulation Framework.	DATE	2005	DBLP DOI BibTeX RDF
9	Hongkyu Kim, D. Scott Wills, Linda M. Wills	Technology-based Architectural Analysis of Operand Bypass Networks for Efficient Operand Transport.	IPDPS	2005	DBLP DOI BibTeX RDF
9	Sibin Mohan, Frank Mueller 0001, David B. Whalley, Christopher A. Healy	Timing Analysis for Sensor Network Nodes of the Atmega Processor Family.	IEEE Real-Time and Embedded Technology and Applications Symposium	2005	DBLP DOI BibTeX RDF
9	Nicolas Genko, David Atienza, Giovanni De Micheli, Luca Benini, Jose Manuel Mendias, Román Hermida, Francky Catthoor	A novel approach for network on chip emulation.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
9	Jia Yu 0008, Jun Yang 0002, Shaojie Chen, Yan Luo, Laxmi N. Bhuyan	Enhancing Network Processor Simulation Speed with Statistical Input Sampling.	HiPEAC	2005	DBLP DOI BibTeX RDF
9	Uwe Kastens, Dinh Khoi Le, Adrian Slowik, Michael Thies	Feedback driven instruction-set extension.	LCTES	2004	DBLP DOI BibTeX RDF	simulator generation, encryption, network processor, codesign, instruction-set extensions, compiler generation
9	Narayanan Vijaykrishnan, Mahmut T. Kandemir, Mary Jane Irwin, Hyun Suk Kim, Wu Ye, David Duarte	Evaluating Integrated Hardware-Software Optimizations Using a Unified Energy Estimation Framework.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	simulation, optimizations, energy models, Energy estimation
9	Nachiketh R. Potlapally, Michael S. Hsiao, Anand Raghunathan, Ganesh Lakshminarayana, Srimat T. Chakradhar	Accurate Power Macro-modeling Techniques for Complex RTL Circuits.	VLSI Design	2001	DBLP DOI BibTeX RDF
8	Georgios Keramidas, Vasileios Spiliopoulos, Stefanos Kaxiras	Interval-based models for run-time DVFS orchestration in superscalar processors.	Conf. Computing Frontiers	2010	DBLP DOI BibTeX RDF	performance and power modeling, superscalar out-of-order processors, dynamic voltage and frequency scaling
8	Zhong-Yi Jin, Rajesh K. Gupta 0001	Improving the speed and scalability of distributed simulations of sensor networks.	IPSN	2009	DBLP DOI BibTeX RDF
8	Hyunwoo Joe, Jonghyuk Lee, Duk-Kyun Woo, Pyeong-Soo Mah, Hyungshin Kim	Demo abstract: A high-fidelity sensor network simulator using accurate CC2420 model.	IPSN	2009	DBLP DOI BibTeX RDF
8	Zhong-Yi Jin, Rajesh Gupta 0001	LazySync: A New Synchronization Scheme for Distributed Simulation of Sensor Networks.	DCOSS	2009	DBLP DOI BibTeX RDF
8	Praveen Kalla, Xiaobo Sharon Hu, Jörg Henkel	A Flexible Framework for Communication Evaluation in SoC Design.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	Interconnect simulator, Network on chip, Trace based simulation, Multiprocessor simulator
8	Tarek M. Taha, D. Scott Wills	An Instruction Throughput Model of Superscalar Processors.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF	Modeling techniques, Pipeline processors, Modeling of computer architecture
8	Hun Jung, Miao Ju, Hao Che, Zhijun Wang 0001	A Fast Performance Analysis Tool for Multicore, Multithreaded Communication Processors.	HASE	2008	DBLP DOI BibTeX RDF
8	Abbas Eslami Kiasari, Dara Rahmati, Hamid Sarbazi-Azad, Shaahin Hessabi	A Markovian Performance Model for Networks-on-Chip.	PDP	2008	DBLP DOI BibTeX RDF
8	Bin Li 0008, Lu Peng 0001, Balachandran Ramadass	Efficient mart-aided modeling for microarchitecture design space exploration and performance prediction.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	MART-aided models, performance prediction, design space exploration
8	Youngjin Cho, Younghyun Kim 0001, Sangyoung Park, Naehyuck Chang	System-level power estimation using an on-chip bus performance monitoring unit.	ICCAD	2008	DBLP DOI BibTeX RDF
8	Zhonglei Wang, Antonio Sánchez, Andreas Herkersdorf	SciSim: a software performance estimation framework using source code instrumentation.	WOSP	2008	DBLP DOI BibTeX RDF	debugging information, software performance estimation, source code instrumentation, microarchitecture
8	Ioana Burcea, Stephen Somogyi, Andreas Moshovos, Babak Falsafi	Predictor virtualization.	ASPLOS	2008	DBLP DOI BibTeX RDF	predictor virtualization, caches, metadata, memory hierarchy
8	Lerong Cheng, Fei Li 0003, Yan Lin 0001, Phoebe Wong, Lei He 0001	Device and Architecture Cooptimization for FPGA Power Reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
8	Antoine Fraboulet, Tanguy Risset	Master Interface for On-chip Hardware Accelerator Burst Communications.	J. VLSI Signal Process.	2007	DBLP DOI BibTeX RDF	SoC simulation, system on chip, high level synthesis, interface generation
8	Zoltán Herczeg, Ákos Kiss 0001, Daniel Schmidt 0001, Norbert Wehn, Tibor Gyimóthy	XEEMU: An Improved XScale Power Simulator.	PATMOS	2007	DBLP DOI BibTeX RDF
8	Philippe Marquet, Simon Duquennoy, Sébastien Le Beux, Samy Meftali, Jean-Luc Dekeyser	Massively parallel processing on a chip.	Conf. Computing Frontiers	2007	DBLP DOI BibTeX RDF	MasPar, mppSoC, SoC, SIMD, system-on-a-chip, massively parallelism
8	Chan-Hao Chang, Diana Marculescu	Design and Analysis of a Low Power VLIW DSP Core.	ISVLSI	2006	DBLP DOI BibTeX RDF
8	Rabie Ben Atitallah, Smaïl Niar, Alain Greiner, Samy Meftali, Jean-Luc Dekeyser	Estimating Energy Consumption for an MPSoC Architectural Exploration.	ARCS	2006	DBLP DOI BibTeX RDF
8	Gi-Ho Park, Sung Woo Chung, Han-Jong Kim, Jung-Bin Im, Jung-Wook Park, Shin-Dug Kim, Sung-Bae Park	Practice and Experience of an Embedded Processor Core Modeling.	HPCC	2006	DBLP DOI BibTeX RDF
8	Ram Srinivasan, Jeanine E. Cook, Olaf M. Lubeck	Ultra-Fast CPU Performance Prediction: Extending the Monte Carlo Approach.	SBAC-PAD	2006	DBLP DOI BibTeX RDF
8	Saurabh Sharma, Jesse G. Beu, Thomas M. Conte	Spectral prefetcher: An effective mechanism for L2 cache prefetching.	ACM Trans. Archit. Code Optim.	2005	DBLP DOI BibTeX RDF	absolute and differential domain, adaptive, memory, Prefetch, autocorrelation, frequency, L2 cache
8	Joshua L. Kihm, Daniel A. Connors	Statistical Simulation of Multithreaded Architectures.	MASCOTS	2005	DBLP DOI BibTeX RDF
8	Dhruba Chandra, Fei Guo, Seongbeom Kim, Yan Solihin	Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture.	HPCA	2005	DBLP DOI BibTeX RDF
8	Eric Mercer, Michael D. Jones	Model Checking Machine Code with the GNU Debugger.	SPIN	2005	DBLP DOI BibTeX RDF
8	Mirko Loghi, Martin Letis, Luca Benini, Massimo Poncino	Exploring the energy efficiency of cache coherence protocols in single-chip multi-processors.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	low power, multiprocessor, system-on-chip, cache coherence
8	Lerong Cheng, Phoebe Wong, Fei Li 0003, Yan Lin 0001, Lei He 0001	Device and architecture co-optimization for FPGA power reduction.	DAC	2005	DBLP DOI BibTeX RDF	Psim, Ptrace, powergating, FPGA, low power
8	Andrea Bona, Vittorio Zaccaria, Roberto Zafalon	Low Effort, High Accuracy Network-on-Chip Power Macro Modeling.	PATMOS	2004	DBLP DOI BibTeX RDF	Network-on-Chip power analysis, communication based low power design, system-level energy optimization
8	Lesley Shannon, Paul Chow	Using reconfigurability to achieve real-time profiling for hardware/software codesign.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, profiling, performance measurement, embedded processor, hardware/software codesign, soft processor
8	Mirko Loghi, Federico Angiolini, Davide Bertozzi, Luca Benini, Roberto Zafalon	Analyzing On-Chip Communication in a MPSoC Environment.	DATE	2004	DBLP DOI BibTeX RDF
8	Ulrich Neffe, Klaus Rothbart, Christian Steger, Reinhold Weiss, Edgar Rieger, Andreas Mühlberger	Energy Estimation Based on Hierarchical Bus Models for Power-Aware Smart Cards.	DATE	2004	DBLP DOI BibTeX RDF
8	Jiangjiang Liu 0002, Krishnan Sundaresan, Nihar R. Mahapatra	Dynamic Address Compression Schemes: A Performance, Energy, and Cost Study.	ICCD	2004	DBLP DOI BibTeX RDF
8	Antoine Fraboulet, Tanguy Risset	Efficient On-Chip Communications for Data-Flow IPs.	ASAP	2004	DBLP DOI BibTeX RDF	SoC simulation, system on chip, High level synthesis, interface generation
8	Yue Luo, Lizy Kurian John, Lieven Eeckhout	Self-Monitored Adaptive Cache Warm-Up for Microprocessor Simulation.	SBAC-PAD	2004	DBLP DOI BibTeX RDF
8	Hojun Shim, Yongsoo Joo, Yongseok Choi, Hyung Gyu Lee, Naehyuck Chang	Low-energy off-chip SDRAM memory systems for embedded applications.	ACM Trans. Embed. Comput. Syst.	2003	DBLP DOI BibTeX RDF	Low power, memory system, SDRAM
8	Laura Carrington, Allan Snavely, Xiaofeng Gao 0003, Nicole Wolter	A Performance Prediction Framework for Scientific Applications.	International Conference on Computational Science	2003	DBLP DOI BibTeX RDF
8	Matteo Dall'Osso, Gianluca Biccari, Luca Giovannini, Davide Bertozzi, Luca Benini	xpipes: a Latency Insensitive Parameterized Network-on-chip Architecture For Multi-Processor SoCs.	ICCD	2003	DBLP DOI BibTeX RDF
8	Tajana Simunic, Luca Benini, Giovanni De Micheli	Energy-efficient design of battery-powered embedded systems.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
8	An-Chow Lai, Cem Fide, Babak Falsafi	Dead-block prediction & dead-block correlating prefetchers.	ISCA	2001	DBLP DOI BibTeX RDF
8	David M. Brooks, Margaret Martonosi, John-David Wellman, Pradip Bose	Power-Performance Modeling and Tradeoff Analysis for a High End Microprocessor.	PACS	2000	DBLP DOI BibTeX RDF
8	Jonathan Combs, Candice Bechem Combs, John Paul Shen	Mispredicted Path Cache Effects.	Euro-Par	1999	DBLP DOI BibTeX RDF
6	Kyle Rupnow, Jacob Adriaens, Wenyin Fu, Katherine Compton	Accurately evaluating application performance in simulated hybrid multi-tasking systems.	FPGA	2010	DBLP DOI BibTeX RDF	performance evaluation, hybrid systems, heterogeneous systems, full system simulation, multi-tasking systems
6	Graham Schelle, Jamison D. Collins, Ethan Schuchman, Perry H. Wang, Xiang Zou, Gautham N. Chinya, Ralf Plate, Thorsten Mattner, Franz Olbrich, Per Hammarlund, Ronak Singhal, Jim Brayton, Sebastian Steibl, Hong Wang 0003	Intel nehalem processor core made FPGA synthesizable.	FPGA	2010	DBLP DOI BibTeX RDF	intel nehalem, synthesizable core, fpga, emulator
6	Aparna Mandke Dani, Keshavan Varadarajan, Bharadwaj Amrutur, Y. N. Srikant	Accelerating multi-core simulators.	SAC	2010	DBLP DOI BibTeX RDF	chip multi-core, multi-core platform, timed petri-nets, instruction set simulator, cache simulator
6	Dave Christie, Jae-Woong Chung, Stephan Diestelhorst, Michael Hohmuth, Martin Pohlack, Christof Fetzer, Martin Nowack, Torvald Riegel, Pascal Felber, Patrick Marlier, Etienne Rivière	Evaluation of AMD's advanced synchronization facility within a complete transactional memory stack.	EuroSys	2010	DBLP DOI BibTeX RDF	transactional memory
6	Jeffrey Stuecheli, Dimitris Kaseridis, David Daly, Hillery C. Hunter, Lizy K. John	The virtual write queue: coordinating DRAM and last-level cache policies.	ISCA	2010	DBLP DOI BibTeX RDF	cmp many-core, ddr ddr2 ddr3, dram-parameters, memory-scheduling writeback, page-mode, write-queue, write-scheduling, dram, cache-replacement, last-level-cache
6	Zhangxi Tan, Andrew Waterman, Rimas Avizienis, Yunsup Lee, Henry Cook, David A. Patterson 0001, Krste Asanovic	RAMP gold: an FPGA-based architecture simulator for multiprocessors.	DAC	2010	DBLP DOI BibTeX RDF	simulation, FPGA, multiprocessors
6	Efraim Rotem, Avi Mendelson, Ran Ginosar, Uri C. Weiser	Multiple clock and voltage domains for chip multi processors.	MICRO	2009	DBLP DOI BibTeX RDF	clock domains, voltage domain, power management, DVFS, chip multi processor
6	Joseph Gebis, Leonid Oliker, John Shalf, Samuel Williams 0001, Katherine A. Yelick	Improving Memory Subsystem Performance Using ViVA: Virtual Vector Architecture.	ARCS	2009	DBLP DOI BibTeX RDF
6	Samar Abdi, Gunar Schirner, Ines Viskic, Hansu Cho, Yonghyun Hwang, Lochi Yu, Daniel Gajski	Hardware-dependent software synthesis for many-core embedded systems.	ASP-DAC	2009	DBLP DOI BibTeX RDF
6	Karthik Ganesan 0006, Deepak Panwar, Lizy K. John	Generation, Validation and Analysis of SPEC CPU2006 Simulation Points Based on Branch, Memory and TLB Characteristics.	SPEC Benchmark Workshop	2009	DBLP DOI BibTeX RDF
6	Pierre Michaud	Online compression of cache-filtered address traces.	ISPASS	2009	DBLP DOI BibTeX RDF
6	Dam Sunwoo, Joonsoo Kim, Derek Chiou	QUICK: A flexible full-system functional model.	ISPASS	2009	DBLP DOI BibTeX RDF
6	Nan Yuan, Yongbin Zhou, Guangming Tan, Junchao Zhang, Dongrui Fan	High Performance Matrix Multiplication on Many Cores.	Euro-Par	2009	DBLP DOI BibTeX RDF
6	Muhammad Aqeel Wahlah, Kees Goossens	Modeling reconfiguration in a FPGA with a hardwired network on chip.	IPDPS	2009	DBLP DOI BibTeX RDF
6	Terrence S. T. Mak, Peter Y. K. Cheung, Wayne Luk, Kai-Pui Lam	A DP-network for optimal dynamic routing in network-on-chip.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	optimal and sub-optimal routing, dynamic programming, network-on-chip, adaptive routing
6	Anders Sejer Tranberg-Hansen, Jan Madsen	A compositional modelling framework for exploring MPSoC systems.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	MPSoC, system level design, performance estimation
6	Yanqin Yang, Meng Wang 0005, Zili Shao, Minyi Guo	Dynamic Scratch-Pad Memory Management with Data Pipelining for Embedded Systems.	CSE (2)	2009	DBLP DOI BibTeX RDF
6	James R. Green, Hanan Mahmoud, Michel Dumontier	Modeling tryptic digestion on the Cell BE processor.	CCECE	2009	DBLP DOI BibTeX RDF
6	Edgar A. León, Rolf Riesen, Arthur B. Maccabe, Patrick G. Bridges	Instruction-level simulation of a cluster at scale.	SC	2009	DBLP DOI BibTeX RDF
6	Susmit Biswas, Diana Franklin, Alan Savage, Ryan Dixon, Timothy Sherwood, Frederic T. Chong	Multi-execution: multicore caching for data-similar executions.	ISCA	2009	DBLP DOI BibTeX RDF	data similar execution, multicore cache design, cmp
6	Stephen Somogyi, Thomas F. Wenisch, Anastasia Ailamaki, Babak Falsafi	Spatio-temporal memory streaming.	ISCA	2009	DBLP DOI BibTeX RDF	prefetching, spatial correlation, temporal correlation
6	Martino Ruggiero, Alessio Guerri, Davide Bertozzi, Michela Milano, Luca Benini	A Fast and Accurate Technique for Mapping Parallel Applications on Stream-Oriented MPSoC Platforms with Communication Awareness.	Int. J. Parallel Program.	2008	DBLP DOI BibTeX RDF	scheduling, Integer Programming, Constraint Programming, MPSoCs, allocation
6	Jongsun Kim, Bo-Cheng Lai, Mau-Chung Frank Chang, Ingrid Verbauwhede	A Cost-Effective Latency-Aware Memory Bus for Symmetric Multiprocessor Systems.	IEEE Trans. Computers	2008	DBLP DOI BibTeX RDF