Search results for "designs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
17	Nagaraj Ns, John Byler, Koorosh Nazifi, Venugopal Puvvada, Toshiyuki Saito, Alan Gibbons, S. Balajee	What's cool for the future of ultra low power designs?	DAC	2010	DBLP DOI BibTeX RDF	system level power, low power, system design
17	Gopu V. R. Muni Kumar, B. Sundar Rajan	Low PAPR square STBCs from complex partial-orthogonal designs (CPODs).	IEEE Trans. Wirel. Commun.	2009	DBLP DOI BibTeX RDF
17	M. R. Darafsheh, A. Iranmanesh, R. Kahkeshani	Some designs and codes invariant under the groups S 9 and A 8.	Des. Codes Cryptogr.	2009	DBLP DOI BibTeX RDF	Mathematics Subject Classifications (2000) 05E15, 05B05, 05E20
17	P. Balasubramanian 0001, David A. Edwards, Charlie Brej	Self-timed full adder designs based on hybrid input encoding.	DDECS	2009	DBLP DOI BibTeX RDF
17	Bing-Chuan Bai, Augusli Kifli, Chien-Mo James Li, Kun-Cheng Wu	Fault modeling and testing of retention flip-flops in low power designs.	ASP-DAC	2009	DBLP DOI BibTeX RDF
17	Pradyumn Kumar Shukla	Genetically Optimized Architectural Designs for Control of Pedestrian Crowds.	ACAL	2009	DBLP DOI BibTeX RDF	crowd stampedes, genetic algorithms, design optimization
17	Hyunmin Kim, Yong-Hyuk Kim	Optimal designs of ambiguous mobile keypad with alphabetical constraints.	GECCO	2009	DBLP DOI BibTeX RDF	keypad design, genetic algorithm, mobile device, dynamic programming, multitap
17	Hariharan Sankaran, Srinivas Katkoori	On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs.	ISQED	2009	DBLP DOI BibTeX RDF
17	Mike Sablatash	Designs and architectures of filter bank trees for spectrally efficient multi-user communications: review, modifications and extensions of wavelet packet filter bank trees.	Signal Image Video Process.	2008	DBLP DOI BibTeX RDF	Filter bank trees, Multi-user OFDM-type communication systems
17	Bryan Horling, Victor R. Lesser	Using quantitative models to search for appropriate organizational designs.	Auton. Agents Multi Agent Syst.	2008	DBLP DOI BibTeX RDF
17	Zhifei Fan, Louis L. Scharf, John A. Gubner	Analog Precoder and Equalizer Designs and their Geometry for Multichannel Communication.	IEEE Trans. Wirel. Commun.	2008	DBLP DOI BibTeX RDF
17	Jon-Lark Kim, Patrick Solé	Skew Hadamard designs and their codes.	Des. Codes Cryptogr.	2008	DBLP DOI BibTeX RDF	94B25, AMS Classifications 05B20
17	Yinghui Li, Hlaing Minn	Robust and consistent pilot designs for frequency offset estimation in MIMO OFDM systems.	IEEE Trans. Commun.	2008	DBLP DOI BibTeX RDF
17	Kerstin Hesse, Paul C. Leopardi	The Coulomb energy of spherical designs on S 2.	Adv. Comput. Math.	2008	DBLP DOI BibTeX RDF	Mathematics Subject Classifications (2000) Primary: 31C20, Secondary: 41A55, 42C20, 65B10, 65D32, 42C10
17	Jeng-Ji Huang, Zong-Jhe Wu, Wei-Ting Wang	Designs of microcell for an integrated HAPS-terrestrial CDMA system.	PIMRC	2008	DBLP DOI BibTeX RDF
17	Michael Todd Gamble, Rose F. Gamble	Reasoning about Hybrid System of Systems Designs.	ICCBSS	2008	DBLP DOI BibTeX RDF	interoperability, hybrid systems, isolation, system of systems
17	Michael Huber	Steiner t-Designs for Large t.	MMICS	2008	DBLP DOI BibTeX RDF
17	James Alfred Walker, James A. Hilder, Andy M. Tyrrell	Evolving Variability-Tolerant CMOS Designs.	ICES	2008	DBLP DOI BibTeX RDF
17	Gregory Hornby, William F. Kraus, Jason D. Lohn	Evolving MEMS Resonator Designs for Fabrication.	ICES	2008	DBLP DOI BibTeX RDF
17	Paula Herber, Joachim Fellmuth, Sabine Glesner	Model checking SystemC designs using timed automata.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	model checking, timed automata, SystemC
17	Joachim Schenk, Stefan Schwärzler, Günther Ruske, Gerhard Rigoll	Novel VQ Designs for Discrete HMM On-Line Handwritten Whiteboard Note Recognition.	DAGM-Symposium	2008	DBLP DOI BibTeX RDF
17	Hossein Asadi 0001, Mehdi Baradaran Tahoori	Analytical Techniques for Soft Error Rate Modeling and Mitigation of FPGA-Based Designs.	IEEE Trans. Very Large Scale Integr. Syst.	2007	DBLP DOI BibTeX RDF
17	Gary L. Ebert, Keith E. Mellinger	Mixed partitions and related designs.	Des. Codes Cryptogr.	2007	DBLP DOI BibTeX RDF	51A35, AMS Classification 51E20
17	Carl Bracken, Gary McGuire	Duals of quasi-3 designs are not necessarily quasi-3.	Des. Codes Cryptogr.	2007	DBLP DOI BibTeX RDF	AMS Classifications 05B05, 94B65, 05B20
17	Niranjan Balachandran, Dijen K. Ray-Chaudhuri	Simple 3-designs and PSL(2, q) with q == 1 (mod 4).	Des. Codes Cryptogr.	2007	DBLP DOI BibTeX RDF	AMS Classification 05B30, 05E15
17	Sanghyeon Baeg	Delay Fault Coverage Enhancement by Partial Clocking for Low-Power Designs With Heavily Gated Clocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
17	Gaurav Singh 0006, Sandeep K. Shukla	Model Checking Bluespec Specified Hardware Designs.	MTV	2007	DBLP DOI BibTeX RDF
17	Noureddine Chabini	A Heuristic for Reducing Dynamic Power Dissipation in Clocked Sequential Designs.	PATMOS	2007	DBLP DOI BibTeX RDF
17	A. Nardi, Emre Tuncer, Srinath R. Naidu, A. Antonau, S. Gradinaru, Tao Lin, J. Song	Use of statistical timing analysis on real designs.	DATE	2007	DBLP DOI BibTeX RDF
17	Rene Krenz-Baath, Andreas Glowatz, Jürgen Schlöffel	Computation and Application of Absolute Dominators in Industrial Designs.	ETS	2007	DBLP DOI BibTeX RDF
17	Bill Pontikakis, Hung Tien Bui, François R. Boyer, Yvon Savaria	A Low-Complexity High-Speed Clock Generator for Dynamic Frequency Scaling of FPGA and Standard-Cell Based Designs.	ISCAS	2007	DBLP DOI BibTeX RDF
17	Carl Bracken, Gary McGuire, Harold N. Ward	New quasi-symmetric designs constructed using mutually orthogonal Latin squares and Hadamard matrices.	Des. Codes Cryptogr.	2006	DBLP DOI BibTeX RDF	AMS Classifications 05B05, 94B65, 05B20
17	Maciej J. Ciesielski, Priyank Kalla, Serkan Askar	Taylor Expansion Diagrams: A Canonical Representation for Verification of Data Flow Designs.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Register transfer level—design aids, arithmetic and logic structures—verification, symbolic and algebraic manipulation, verification
17	Christian Genz, Rolf Drechsler	System Exploration of SystemC Designs.	ISVLSI	2006	DBLP DOI BibTeX RDF
17	José Arnaldo Barra Montevechi, Renaldo Gonzaga de Almeida Filho, André Luiz Medeiros	Application of factorial designs for reducing factors in optimization via discrete-event simulation.	WSC	2006	DBLP DOI BibTeX RDF
17	Monika Záková, Filip Zelezný, Javier A. García-Sedano, Cyril Masia Tissot, Nada Lavrac, Petr Kremen, Javier Molina	Relational Data Mining Applied to Virtual Engineering of Product Designs.	ILP	2006	DBLP DOI BibTeX RDF
17	Nir Piterman, Amir Pnueli, Yaniv Sa'ar	Synthesis of Reactive(1) Designs.	VMCAI	2006	DBLP DOI BibTeX RDF
17	Xue-Bin Liang, Xiang-Gen Xia 0001	Fast differential unitary space-time demodulation via square orthogonal designs.	IEEE Trans. Wirel. Commun.	2005	DBLP DOI BibTeX RDF
17	Eric Anderson 0003, Susan Spence, Ram Swaminathan, Mahesh Kallahalla, Qian Wang	Quickly finding near-optimal storage designs.	ACM Trans. Comput. Syst.	2005	DBLP DOI BibTeX RDF
17	Harri Haanpää, Petteri Kaski	The Near Resolvable 2-(13, 4, 3) Designs and Thirteen-Player Whist Tournaments.	Des. Codes Cryptogr.	2005	DBLP DOI BibTeX RDF	near resolvable design, whist tournament, orderly algorithm
17	Carl Bracken, Gary McGuire	Characterization of SDP Designs That Yield Certain Spin Models.	Des. Codes Cryptogr.	2005	DBLP DOI BibTeX RDF	symmetric difference property, spin model, design, symplectic
17	Yuan-Pei Lin, See-May Phoong	Window designs for DFT-based multicarrier systems.	IEEE Trans. Signal Process.	2005	DBLP DOI BibTeX RDF
17	Marc Herbstritt, Bernd Becker 0001	On SAT-based Bounded Invariant Checking of Blackbox Designs.	MTV	2005	DBLP DOI BibTeX RDF
17	Yu-Shen Yang, Andreas G. Veneris, Paul J. Thadikaran, Srikanth Venkataraman	Extraction Error Modeling and Automated Model Debugging in High-Performance Low Power Custom Designs.	DATE	2005	DBLP DOI BibTeX RDF
17	Natarajan Viswanathan, Min Pan, Chris C. N. Chu	FastPlace: an analytical placer for mixed-mode designs.	ISPD	2005	DBLP DOI BibTeX RDF	mixed-mode placement, floorplanning, analytical placement
17	Paul Baker, Tim Todman, Henry Styles, Wayne Luk	Reconfigurable Designs for Radiosity.	FCCM	2005	DBLP DOI BibTeX RDF
17	Amit Agarwal 0001, Kunhyuk Kang, Swarup Bhunia, James D. Gallagher, Kaushik Roy 0001	Effectiveness of low power dual-Vt designs in nano-scale technologies under process parameter variations.	ISLPED	2005	DBLP DOI BibTeX RDF	process variation, yield, leakage, dual-Vt, metal gate
17	Christianto C. Liu, Jeng-Huei Chen, Rajit Manohar, Sandip Tiwari	Mapping system-on-chip designs from 2-D to 3-D ICs.	ISCAS (3)	2005	DBLP DOI BibTeX RDF
17	Alex Samorodnitsky	On Linear Programming Bounds for Spherical Codes and Designs.	Discret. Comput. Geom.	2004	DBLP DOI BibTeX RDF
17	Peter D. Neuhaus, Michael O'Sullivan, David Eaton, John Carff, Jerry E. Pratt	Concept Designs for Underwater Swimming Exoskeletons.	ICRA	2004	DBLP DOI BibTeX RDF
17	José Miguel Valiente, Francisco Albert, Carmen Carretero, José María Gomis	Structural Description of Textile and Tile Pattern Designs Using Image Processing.	ICPR (1)	2004	DBLP DOI BibTeX RDF
17	Xiao Yang, Keying Ye	On Efficiency of Experimental Designs for Single Factor cDNA Microarray Experiments.	CASDMKM	2004	DBLP DOI BibTeX RDF
17	Rolf Drechsler	Synthesizing checkers for on-line verification of System-on-Chip designs.	ISCAS (4)	2003	DBLP DOI BibTeX RDF
17	Noureddine Chabini, Ismaïl Chabini, El Mostapha Aboulhamid, Yvon Savaria	Unification of basic retiming and supply voltage scaling to minimize dynamic power consumption for synchronous digital designs.	ACM Great Lakes Symposium on VLSI	2003	DBLP DOI BibTeX RDF	supply voltage scaling, performance, power consumption, CMOS, retiming, digital design
17	Fei Xie, James C. Browne	Integrated State Space Reduction for Model Checking Executable Object-Oriented Software System Designs.	FASE	2002	DBLP DOI BibTeX RDF
17	HyungWon Kim 0001, John P. Hayes	Delay fault testing of IP-based designs via symbolic path modeling.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
17	HyungWon Kim 0001, John P. Hayes	Realization-independent ATPG for designs with unimplemented blocks.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2001	DBLP DOI BibTeX RDF
17	Lionel C. Briand, Christian Bunse, John W. Daly	A Controlled Experiment for Evaluating Quality Guidelines on the Maintainability of Object-Oriented Designs.	IEEE Trans. Software Eng.	2001	DBLP DOI BibTeX RDF	object-oriented, replication, experiment, maintainability, Design documents
17	Sitaram Yadavalli, Sandip Kundu	On Fault-Simulation Through Embedded Memories On Large Industrial Designs.	VLSI Design	2001	DBLP DOI BibTeX RDF
17	Arran Derbyshire, Wayne Luk	Combining Serialisation and Reconfiguration for FPGA Designs.	FPL	2000	DBLP DOI BibTeX RDF
17	Linda Trocine, Linda C. Malone	Statistical tools for simulation design and analysis I: finding important independent variables through screening designs: a comparison of methods.	WSC	2000	DBLP DOI BibTeX RDF
17	Vesselin K. Vassilev, Julian F. Miller	Scalability Problems of Digital Circuit Evolution: Evolvability and Efficient Designs.	Evolvable Hardware	2000	DBLP DOI BibTeX RDF
17	Jitendra Khare, Hans T. Heineken, Manuel d'Abreu	Cost Trade-Offs in System On Chip Designs.	VLSI Design	2000	DBLP DOI BibTeX RDF	Manufacturing Cost, Test Cost, Technology Migration, Cost Trade-Offs, System On Chip
17	Elizabeth A. Kendall	Role Model Designs and Implementations with Aspect-oriented Programming.	OOPSLA	1999	DBLP DOI BibTeX RDF	aspect-oriented programming, role modelling
17	Lun Ye, Foong-Charn Chang, Peter Feldmann, Rakesh Chadha, Nagaraj Ns, Frank Cano	Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs.	DATE	1999	DBLP DOI BibTeX RDF
17	Wen-Jong Fang, Peng-Cheng Kao, Allen C.-H. Wu	A Multi-Level FPGA Synthesis Method Supporting HDL Debugging for Emulation-Based Designs.	ASP-DAC	1999	DBLP DOI BibTeX RDF
17	K. K. P. Chanduka, Mahesh C. Bhandari, Arbind K. Lal	Lower Bounds for Group Covering Designs.	AAECC	1999	DBLP DOI BibTeX RDF
17	John S. Fernando, Milos D. Ercegovac	Conventional and on-line arithmetic designs for high-speed recursive digital filters.	J. VLSI Signal Process.	1994	DBLP DOI BibTeX RDF
17	Rajiv Jain, Alice C. Parker, Nohbyung Park	Predicting system-level area and delay for pipelined and nonpipelined designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1992	DBLP DOI BibTeX RDF
17	Loe M. G. Feijs	Transformations of Designs.	Algebraic Methods	1989	DBLP DOI BibTeX RDF
17	Daniel Le Ly, Paul Chow	A high-performance FPGA architecture for restricted boltzmann machines.	FPGA	2009	DBLP DOI BibTeX RDF	neural network hardware, restricted boltzmann machines, scalable hardware designs, fpga, high-performance computing, complexity reduction
17	Annalisa De Bonis	New combinatorial structures with applications to efficient group testing with inhibitors.	J. Comb. Optim.	2008	DBLP DOI BibTeX RDF	Group testing algorithms, Superimposed codes, Pooling designs, Selectors, Computational molecular biology
17	Grzegorz Mrugalski, Janusz Rajski, Chen Wang 0014, Artur Pogiel, Jerzy Tyszer	Isolation of Failing Scan Cells through Convolutional Test Response Compaction.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	convolutional compactors, fault diagnosis, test response compaction, scan-based designs
17	Kwang-Ting (Tim) Cheng	Moore's law meets the life sciences.	IEEE Des. Test Comput.	2007	DBLP DOI BibTeX RDF	labs on chips, CAD, biochips, multimedia designs
17	Natarajan Viswanathan, Min Pan, Chris C. N. Chu	FastPlace 3.0: A Fast Multilevel Quadratic Placement Algorithm with Placement Congestion Control.	ASP-DAC	2007	DBLP DOI BibTeX RDF	legalization technique, FastPlace 3.0, multilevel quadratic placement algorithm, placement congestion control, large-scale mixed-size designs, multilevel global placement framework, two-level clustering scheme, iterative local refinement, placement blockages, placement congestion constraints
17	Aseem Gupta, Nikil D. Dutt, Fadi J. Kurdahi, Kamal S. Khouri, Magdy S. Abadir	LEAF: A System Level Leakage-Aware Floorplanner for SoCs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	LEAF, leakage-aware floorplanning, temperature-aware leakage power, dynamic power profile, system on chip, SoC designs
17	Sudarshan Bahukudumbi, Sule Ozev, Krishnendu Chakrabarty, Vikram Iyengar	AWafer-Level Defect Screening Technique to Reduce Test and Packaging Costs for "Big-D/Small-A" Mixed-Signal SoCs.	ASP-DAC	2007	DBLP DOI BibTeX RDF	mixed-signal cores, wafer-level defect screening, packaging cost reduction, big-D/small-A mixed-signal system-on-chip designs, mixed-signal SoC, consumer electronics market, wafer-level testing, correlation-based signature analysis, low-cost digital testers, generic cost model, mixed-signal test, digital logic, test cost reduction
17	Marc Herbstritt, Bernd Becker 0001	On Combining 01X-Logic and QBF.	EUROCAST	2007	DBLP DOI BibTeX RDF	01X, Blackbox Designs, Bounded Model Checking, QBF
17	Mahmoud O. Elish, David C. Rine	Design Structural Stability Metrics and Post-Release Defect Density: An Empirical Study.	COMPSAC (2)	2006	DBLP DOI BibTeX RDF	software metrics, object-oriented designs, Structural stability
17	Evangelos Vergetis, Roch Guérin, Saswati Sarkar	Realizing the benefits of user-level channel diversity.	Comput. Commun. Rev.	2005	DBLP DOI BibTeX RDF	channel diversity, open-loop control, robustness, cross-layer designs
17	Robert D. Kenney, Michael J. Schulte	High-Speed Multioperand Decimal Adders.	IEEE Trans. Computers	2005	DBLP DOI BibTeX RDF	multioperand adders, Computer arithmetic, hardware designs, decimal arithmetic
17	Mahmoud O. Elish, David C. Rine	Investigation of Metrics for Object-Oriented Design Logical Stability.	CSMR	2003	DBLP DOI BibTeX RDF	Design stability, metrics, object-oriented designs, maintainability
17	Sylvia B. Encheva, Gérard D. Cohen	Partially Identifying Codes for Copyright Protection.	AAECC	2001	DBLP DOI BibTeX RDF	Secure frameproof codes, designs, copyright protection
17	Adam L. Young, Moti Yung	Bandwidth-Optimal Kleptographic Attacks.	CHES	2001	DBLP DOI BibTeX RDF	Leakage attacks, the Newton channel, design methodologies for asymmetric ciphers, kleptographic attacks, attack bandwidth, discrete logarithm based systems, tamper-proof hardware designs, public scrutiny, hardware technologies: EEPROM, ferroelectric, trust, DSA, ElGamal, subliminal channels, non-volatile memory
17	Michael J. Schulte, Earl E. Swartzlander Jr.	A Family of Variable-Precision Interval Arithmetic Processors.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	variable-precision arithmetic, computer arithmetic, accuracy, Processors, interval arithmetic, hardware designs, roundoff error
17	Amnart Pohthong, David Budgen	Accessing software component documentation during design: an observational study.	APSEC	2000	DBLP DOI BibTeX RDF	software component documentation access, software delivery, laboratory-based studies, system design, systems analysis, software reusability, subroutines, component-based designs, system documentation, reusable software components
17	Yu-Kwong Kwok, Vincent K. N. Lau	A Performance Study of Multiple Access Control Protocols for Wireless Multimedia Services.	ICNP	2000	DBLP DOI BibTeX RDF	integrated voice/data communication, packet reservation multiple access, multiple access control protocols, wireless multimedia services, broadband wireless multimedia network, user traffic requirements, channel bandwidth allocation, TDMA-based MAC protocols, integrated wireless data/voice services, SCAMA, DTDMA/VR, DTDMA/PR, D4RUMA, DPRMA, DSA++, PRMA/DA, orthogonal design, quality of service, quality of service, performance, asynchronous transfer mode, multimedia communication, time division multiple access, MAC protocol, telecommunication traffic, access protocols, protocol designs, CBR, VBR, broadband networks, packet radio networks, ABR, wireless ATM network
17	Yi-Min Jiang, Angela Krstic, Kwang-Ting Cheng	Dynamic Timing Analysis Considering Power Supply Noise Effects.	ISQED	2000	DBLP DOI BibTeX RDF	dynamic timing analysis, input pattern dependent, power supply noise, deep submicron designs
17	Lothar Baum, Martin Becker 0002	Generic Components to Foster Reuse.	TOOLS (37)	2000	DBLP DOI BibTeX RDF	software development efficiency, project-specific aspects, reusable component contribution, inefficient general solutions, niche requirements, specifically optimized designs, requirements space, adaptable generic components, automatic component instantiation, embedded systems, software tools, software tools, abstraction, software reuse, software components, software reusability, computer aided software engineering, operating systems (computers), subroutines, embedded operating systems
17	Douglas R. Stinson, Ruizhong Wei	Key Preassigned Traceability Schemes for Broadcast Encryption.	Selected Areas in Cryptography	1998	DBLP DOI BibTeX RDF	key preassigned scheme, traceability, broadcast encryption, secret sharing schemes, combinatorial designs
17	S. Sandeep Pradhan, Kannan Ramchandran	Efficient layered video delivery over multicarrier systems using optimized embedded modulation.	ICIP (3)	1997	DBLP DOI BibTeX RDF	efficient layered video delivery, multicarrier systems, optimized embedded modulation, multi-carrier modulation systems, layered framework, multiresolution framework, importance layers, BER requirements, embedded multi-carrier modulation, EMCM, table-lookup based power allocation algorithm, multicarrier constellation design, deliverable throughput bitrates, resolution layers, TDM-based MCM designs, embedded wavelet image coder, 3 dB, visual communication, noise immunity, MCM, image transmission
17	Raghava V. Cherabuddi, Magdy A. Bayoumi, H. Krishnamurthy	A low power based system partitioning and binding technique for multi-chip module architectures.	Great Lakes Symposium on VLSI	1997	DBLP DOI BibTeX RDF	binding technique, multi-chip module architectures, high-level synthesis framework, inter-chip buses, stochastic evolution based technique, multichip modules, switching activity, MCM, functional units, system partitioning, benchmark designs
17	Matthew B. Dwyer	Modular Flow Analysis for Concurrent Software.	ASE	1997	DBLP DOI BibTeX RDF	modular flow analysis, FLAVERS, early validation, individual module designs, system-level validation, whole-program automated static analysis technique, concurrent software systems, program flow analysis, explicitly stated correctness properties, modular analysis approach, realistic concurrent multi-component system, parallel programming
17	Peter Wohl, John A. Waicukauski	Using ATPG for clock rules checking in complex scan design.	VTS	1997	DBLP DOI BibTeX RDF	clock rules checking, complex scan designs, structured DFT, automated design-rules-checking, robust set of rules, clock-rule-violation detection, fast clock verification, large microprocessor design, topological circuit analysis, zero delay, user controlled verification, capture ability, port contention, cone tracing, equivalent sources, ATPG, race conditions, computer testing, timing verification
17	Karin Erni, Claus Lewerentz	Applying design-metrics to object-oriented frameworks.	IEEE METRICS	1996	DBLP DOI BibTeX RDF	factor-criteria-metrics model, multi-metrics, structural measurements, measurement reports, framework reorganization reviews, stable system designs, object-oriented programming, software developers, software quality, software metrics, feedback, object-oriented methods, classes, object-oriented frameworks, quality model, design principles, incremental development, abstraction levels, design rules, subsystems, program evaluation, graphical applications, object-oriented design metrics
17	James O. Bondi, Ashwini K. Nanda, Simonjit Dutta	Integrating a Misprediction Recovery Cache (MRC) into a Superscalar Pipeline.	MICRO	1996	DBLP DOI BibTeX RDF	branch target buffer technology, deep pipelines, misprediction recovery cache integration, performance loss, residual misprediction penalty, superscalar pipeline, microprocessor chips, microprocessor designs, CISC, multiple instructions
17	Anand Raghunathan, Sujit Dey, Niraj K. Jha	Register-transfer level estimation techniques for switching activity and power consumption.	ICCAD	1996	DBLP DOI BibTeX RDF	gate-level implementation, register-transfer level estimation, logic design, power consumption, switching activity, glitching, RTL designs
17	Steven Bradley, William Henderson, David Kendall, Adrian Robson, Stephen Hawkes	A Formal Design and Implementation Method for Real-Time Embedded Systems.	EUROMICRO	1996	DBLP DOI BibTeX RDF	real-time system development, AORTA, development life cycle, real-time systems, real-time systems, verification, real-time embedded systems, formal designs
17	Rajesh K. Gupta 0001, Daniel Gajski, Randy Allen, Yatin Trivedi	Opportunities and pitfalls in HDL-based system design.	ICCD	1996	DBLP DOI BibTeX RDF	textual Hardware Description Languages, system designs, VHDL, modeling language, hardware description languages, Verilog, HDLs, hardware systems
17	S. K. Gupta, M. M. Hasan	KANSYS: a CAD tool for analog circuit synthesis.	VLSI Design	1996	DBLP DOI BibTeX RDF	KANSYS, analog circuit synthesis, knowledge intensive hierarchical design, transistor circuit designs, functional circuits, knowledge based systems, hierarchy, integrated circuit design, circuit CAD, CAD tool, analogue integrated circuits, design knowledge, process specifications