Search results for "FPGAs"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
21	Florent Berthelot, Fabienne Nouvel	Partial and Dynamic Reconfiguration of FPGAs: a top down design methodology for an automatic implementation.	ISVLSI	2006	DBLP DOI BibTeX RDF
21	Tatsuhiro Tachibana, Yoshihiro Murata, Naoki Shibata, Keiichi Yasumoto, Minoru Ito	Flexible implementation of genetic algorithms on FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
21	Mohammed Y. Niamat, Dinesh Nemade, Mohsin M. Jamali	Testing embedded RAM modules in SRAM-based FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF
21	Michael J. Beauchamp, Scott Hauck, Keith D. Underwood, K. Scott Hemmert	Embedded floating-point units in FPGAs.	FPGA	2006	DBLP DOI BibTeX RDF	FPU, FPGA, floating-point, FPGA architecture
21	Akhilesh Kumar, Mohab Anis	An analytical state dependent leakage power model for FPGAs.	DATE	2006	DBLP DOI BibTeX RDF
21	Balasubramanian Sethuraman, Ranga Vemuri	optiMap: a tool for automated generation of noc architectures using multi-port routers for FPGAs.	DATE	2006	DBLP DOI BibTeX RDF
21	Lee W. Howes, Paul Price, Oskar Mencer, Olav Beckmann, Oliver Pell	Comparing FPGAs to Graphics Accelerators and the Playstation 2 Using a Unified Source Description.	FPL	2006	DBLP DOI BibTeX RDF
21	Allen Michalski, Duncan A. Buell	A Scalable Architecture for RSA Cryptography on Large FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
21	Manuel Saldaña, Paul Chow	TMD-MPI: An MPI Implementation for Multiple Processors Across Multiple FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
21	Jason D. Bakos, Charles L. Cathey, Allen Michalski	Predictive Load Balancing for Interconnected FPGAs.	FPL	2006	DBLP DOI BibTeX RDF
21	Michael Hübner 0001, Christian Schuck, Jürgen Becker 0001	Elementary block based 2-dimensional dynamic and partial reconfiguration for Virtex-II FPGAs.	IPDPS	2006	DBLP DOI BibTeX RDF
21	Florent Berthelot, Fabienne Nouvel, Dominique Houzet	Partial and dynamic reconfiguration of FPGAs: a top down design methodology for an automatic implementation.	IPDPS	2006	DBLP DOI BibTeX RDF
21	Allen Michalski, Duncan A. Buell	A Scalable Architecture for RSA Cryptography on Large FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
21	Aman Gayasen, Narayanan Vijaykrishnan, Mahmut T. Kandemir, Arif Rahman	Switch Box Architectures for Three-Dimensional FPGAs.	FCCM	2006	DBLP DOI BibTeX RDF
21	Robert Strzodka, Dominik Göddeke	Pipelined Mixed Precision Algorithms on FPGAs for Fast and Accurate PDE Solvers from Low Precision Components.	FCCM	2006	DBLP DOI BibTeX RDF
21	Marvin Tom, David Leong, Guy G. Lemieux	Un/DoPack: re-clustering of large system-on-chip designs with interconnect variation for low-cost FPGAs.	ICCAD	2006	DBLP DOI BibTeX RDF	channel width constraints, clustering, field-programmable gate arrays (FPGA), packing
21	Gordon R. Chiu, Deshanand P. Singh, Valavan Manohararajah, Stephen Dean Brown	Mapping arbitrary logic functions into synchronous embedded memories for area reduction on FPGAs.	ICCAD	2006	DBLP DOI BibTeX RDF
21	Carsten Bieser, Klaus D. Müller-Glaser	Rapid Prototyping Design Acceleration Using a Novel Merging Methodology for Partial Configuration Streams of Xilinx Virtex-II FPGAs.	IEEE International Workshop on Rapid System Prototyping	2006	DBLP DOI BibTeX RDF
21	Taraneh Taghavi, Soheil Ghiasi, Majid Sarrafzadeh	Routing algorithms: architecture driven rerouting enhancement for FPGAs.	ISCAS	2006	DBLP DOI BibTeX RDF
21	S. Habermann, René Kothe, Heinrich Theodor Vierhaus	Built-in Self Repair by Reconfiguration of FPGAs.	IOLTS	2006	DBLP DOI BibTeX RDF
21	Javier Vega-Pineda, Mario Ignacio Chacon Murguia, Roberto Camarillo-Cisneros	Synthesis of Pulsed-Coupled Neural Networks in FPGAs for Real-Time Image Segmentation.	IJCNN	2006	DBLP DOI BibTeX RDF
21	Vishal Suthar, Shantanu Dutt	Mixed PLB and Interconnect BIST for FPGAs Without Fault-Free Assumptions.	VTS	2006	DBLP DOI BibTeX RDF
21	Manuel G. Gericota, Luís F. Lemos, Gustavo R. Alves, Mario M. Barbosa, José M. Ferreira 0001	A Framework for Fault Tolerant Real Time Systems Based on Reconfigurable FPGAs.	ETFA	2006	DBLP DOI BibTeX RDF
21	Robin J. Bruce, Richard Chamberlain, Malachy Devlin, Stephen Marshall	Poster reception - Implementing algorithms on FPGAs using high-level languages and low-level libraries.	SC	2006	DBLP DOI BibTeX RDF
21	Balaji Vaidyanathan, Suresh Srinivasan, Yuan Xie 0001, Narayanan Vijaykrishnan, Rong Luo	Leakage Optimized DECAP Design for FPGAs.	APCCAS	2006	DBLP DOI BibTeX RDF
21	Graham Schelle, Dirk Grunwald	CUSP: a modular framework for high speed network applications on FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	networking, parallelism, reconfigurable hardware, speculation
21	Ling Zhuo, Viktor K. Prasanna	Sparse Matrix-Vector multiplication on FPGAs.	FPGA	2005	DBLP DOI BibTeX RDF	FPGA, reconfigurable architecture, high performance, floating-point, sparse matrix
21	Khaled Benkrid, Samir Belkacemi	An integrated framework for the high level design of high performance signal processing circuits on FPGAs (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
21	Deepak Rautela, Rajendra S. Katti	Efficient utilization of heterogeneous routing resources for FPGAs (abstract only).	FPGA	2005	DBLP DOI BibTeX RDF
21	Zhi Guo, Betul Buyukkurt, Walid A. Najjar, Kees A. Vissers	Optimized Generation of Data-Path from C Codes for FPGAs.	DATE	2005	DBLP DOI BibTeX RDF
21	Chang Woo Kang, Massoud Pedram	Clustering techniques for coarse-grained, antifuse FPGAs.	ASP-DAC	2005	DBLP DOI BibTeX RDF
21	E. Syam Sundar Reddy, Vikram Chandrasekhar, Milagros Sashikánth, V. Kamakoti 0001, Narayanan Vijaykrishnan	Online Detection and Diagnosis of Multiple Configuration Upsets in LUTs of SRAM-Based FPGAs.	IPDPS	2005	DBLP DOI BibTeX RDF
21	Mohammed Y. Niamat, Surya S. Hejeebu, Mansoor Alam	A BIST Approach for Testing FPGAs Using JBITS.	FCCM	2005	DBLP DOI BibTeX RDF
21	Hassan Hassan 0001, Mohab Anis, Mohamed I. Elmasry	LAP: a logic activity packing methodology for leakage power-tolerant FPGAs.	ISLPED	2005	DBLP DOI BibTeX RDF	activity profile, basic logic elements (BLEs), configurable logic blocks (CLBs), sleep transistor (ST), sub-threshold leakage power, FPGA, packing
21	Somsubhra Mondal, Seda Ogrenci Memik	Fine-grain leakage optimization in SRAM based FPGAs.	ACM Great Lakes Symposium on VLSI	2005	DBLP DOI BibTeX RDF	hierarchical LUT, FPGA, low power, leakage power
21	Ghazanfar Asadi, Mehdi Baradaran Tahoori	Soft Error Mitigation for SRAM-Based FPGAs.	VTS	2005	DBLP DOI BibTeX RDF
21	Simon Johnston, Girijesh Prasad, Liam P. Maguire, T. Martin McGinnity	Comparative Investigation into Classical and Spiking Neuron Implementations on FPGAs.	ICANN (1)	2005	DBLP DOI BibTeX RDF
21	Fernanda Lima Kastensmidt, Gustavo Neuberger, Renato Fernandes Hentschke, Luigi Carro, Ricardo Reis 0001	Designing Fault-Tolerant Techniques for SRAM-Based FPGAs.	IEEE Des. Test Comput.	2004	DBLP DOI BibTeX RDF
21	Hao Li, Wai-Kei Mak, Srinivas Katkoori	Force-Directed Performance-Driven Placement Algorithm for FPGAs.	ISVLSI	2004	DBLP DOI BibTeX RDF
21	Zhi Guo, Walid A. Najjar, Frank Vahid, Kees A. Vissers	A quantitative analysis of the speedup factors of FPGAs over processors.	FPGA	2004	DBLP DOI BibTeX RDF	performance, FPGA, analysis, VHDL, reconfigurable computing
21	Vinay Verma, Shantanu Dutt	Roving testing using new built-in-self-tester designs for FPGAs.	FPGA	2004	DBLP DOI BibTeX RDF
21	Helena Krupnova	Mapping Multi-Million Gate SoCs on FPGAs: Industrial Methodology and Experience.	DATE	2004	DBLP DOI BibTeX RDF
21	Norbert Pramstaller, Stefan Mangard, Sandra Dominikus, Johannes Wolkerstorfer	Efficient AES Implementations on ASICs and FPGAs.	AES Conference	2004	DBLP DOI BibTeX RDF	FPGA, Advanced Encryption Standard (AES), ASIC
21	Edson L. Horta, John W. Lockwood	Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
21	Abilio Parreira, João Paulo Teixeira 0001, Marcelino B. Santos	FPGAs BIST Evaluation.	FPL	2004	DBLP DOI BibTeX RDF
21	David B. Thomas, Wayne Luk	Implementing Graphics Shaders Using FPGAs.	FPL	2004	DBLP DOI BibTeX RDF
21	Gokul Govindu, Ling Zhuo, Seonil Choi, Viktor K. Prasanna	Analysis of High-Performance Floating-Point Arithmetic on FPGAs.	IPDPS	2004	DBLP DOI BibTeX RDF
21	Gokul Govindu, Seonil Choi, Viktor K. Prasanna, Vikash Daga, Sridhar Gangadharpalli, V. Sridhar	A High-Performance and Energy-Efficient Architecture for Floating-Point Based LU Decomposition on FPGAs.	IPDPS	2004	DBLP DOI BibTeX RDF
21	Ling Zhuo, Viktor K. Prasanna	Scalable and Modular Algorithms for Floating-Point Matrix Multiplication on FPGAs.	IPDPS	2004	DBLP DOI BibTeX RDF
21	David Zaretsky, Gaurav Mittal, Xiaoyong Tang, Prithviraj Banerjee	Overview of the FREEDOM Compiler for Mapping DSP Software to FPGAs.	FCCM	2004	DBLP DOI BibTeX RDF
21	Lei He, Tulika Mitra, Weng-Fai Wong	Configuration bitstream compression for dynamically reconfigurable FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
21	Erik Chmelar	Minimizing the number of test configurations for FPGAs.	ICCAD	2004	DBLP DOI BibTeX RDF
21	Maitrali Marik, Ajit Pal	Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs.	VLSI Design	2004	DBLP DOI BibTeX RDF
21	Rohini Krishnan, José Pineda de Gyvez	Low Energy Switch Block For FPGAs.	VLSI Design	2004	DBLP DOI BibTeX RDF
21	Gaurav Mittal, David Zaretsky, Xiaoyong Tang, Prithviraj Banerjee	Automatic translation of software binaries onto FPGAs.	DAC	2004	DBLP DOI BibTeX RDF	compiler, reconfigurable computing, binary translation, hardware-software co-design, decompilation
21	Seokjin Lee, Martin D. F. Wong	Timing-driven routing for FPGAs based on Lagrangian relaxation.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
21	Miron Abramovici, Charles E. Stroud	BIST-Based Delay-Fault Testing in FPGAs.	J. Electron. Test.	2003	DBLP DOI BibTeX RDF	Field Programmable Gate Arrays, Built-In Self-Test, delay faults
21	Bruce A. Draper, J. Ross Beveridge, A. P. Wim Böhm, Charles Ross, Monica Chawathe	Accelerated image processing on FPGAs.	IEEE Trans. Image Process.	2003	DBLP DOI BibTeX RDF
21	Pedro C. Diniz, Joonseok Park	Using FPGAs for data and reorganization engines: preliminary results for spatial pointer-based data structures.	FPGA	2003	DBLP DOI BibTeX RDF
21	Kuan Zhou, Michael Chu, Chao You, Jong-Ru Guo, Channakeshav, John Mayega, John F. McDonald 0001, Russell P. Kraft, Bryan S. Goda	A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme.	FPGA	2003	DBLP DOI BibTeX RDF
21	François-Xavier Standaert, Loïc van Oldeneel tot Oldenzeel, David Samyde, Jean-Jacques Quisquater	Power Analysis of FPGAs: How Practical is the Attack?	FPL	2003	DBLP DOI BibTeX RDF
21	Abdsamad Benkrid, Khaled Benkrid, Danny Crookes	Design and Implementation of a Novel FIR Filter Architecture with Boundary Handling on Xilinx VIRTEX FPGAs.	FPL	2003	DBLP DOI BibTeX RDF
21	Daniel Mesquita, Fernando Gehm Moraes, José Palma 0002, Leandro Möller, Ney Laert Vilar Calazans	Remote and Partial Reconfiguration of FPGAs: Tools and Trends.	IPDPS	2003	DBLP DOI BibTeX RDF
21	Jian Liang, Russell Tessier, Oskar Mencer	Floating Point Unit Generation and Evaluation for FPGAs.	FCCM	2003	DBLP DOI BibTeX RDF
21	Abdsamad Benkrid, Khaled Benkrid, Danny Crookes	A Novel FIR Filter Architecture for Efficient Signal Boundary Handling on Xilinx VIRTEX FPGAs.	FCCM	2003	DBLP DOI BibTeX RDF
21	Patrick Girard 0001, Olivier Héron, Serge Pravossoudovitch, Michel Renovell	Defect Analysis for Delay-Fault BIST in FPGAs.	IOLTS	2003	DBLP DOI BibTeX RDF
21	Dereck A. Fernandes, Ian G. Harris	Application of Built in Self-Test for Interconnect Testing of FPGAs.	ITC	2003	DBLP DOI BibTeX RDF
21	Radhika S. Grover, Weijia Shang, Qiang Li	A faster distributed arithmetic architecture for FPGAs.	FPGA	2002	DBLP DOI BibTeX RDF	DALUT, XC4000, carry propagation, cost-performance analysis, distributed arithmetic
21	Ernest Jamro, Kazimierz Wiatr	Constant Coefficient Convolution Implemented in FPGAs.	DSD	2002	DBLP DOI BibTeX RDF
21	Bruce A. Draper, J. Ross Beveridge, A. P. Wim Böhm, Charles Ross, Monica Chawathe	Implementing Image Applications on FPGAs.	ICPR (3)	2002	DBLP DOI BibTeX RDF
21	Naoto Kaneko, Hideharu Amano	A General Hardware Design Model for Multicontext FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
21	Kara K. W. Poon, Andy Yan, Steven J. E. Wilton	A Flexible Power Model for FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
21	Justin L. Tripp, Preston A. Jackson, Brad L. Hutchings	Sea Cucumber: A Synthesizing Compiler for FPGAs.	FPL	2002	DBLP DOI BibTeX RDF
21	Seokjin Lee, D. F. Wong 0001	Timing-driven routing for FPGAs based on Lagrangian relaxation.	ISPD	2002	DBLP DOI BibTeX RDF	timing-driven routing, FPGA, Lagrangian relaxation
21	Li Shang, Niraj K. Jha	Hardware-Software Co-Synthesis of Low Power Real-Time Distributed Embedded Systems with Dynamically Reconfigurable FPGAs.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
21	Prithviraj Banerjee, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi	A Behavioral Synthesis Tool for Exploiting Fine Grain Parallelism in FPGAs.	IWDC	2002	DBLP DOI BibTeX RDF
21	Steven J. E. Wilton	A crosstalk-aware timing-driven router for FPGAs.	FPGA	2001	DBLP DOI BibTeX RDF	field-programmable gate arrays, routing algorithms, crosstalk
21	Srihari Cadambi, Seth Copen Goldstein	Static Profile-Driven Compilation for FPGAs.	FPL	2001	DBLP DOI BibTeX RDF
21	PariVallal Kannan, Dinesh Bhatia	Tightly Integrated Placement and Routing for FPGAs.	FPL	2001	DBLP DOI BibTeX RDF
21	Tong Liu 0007, Wei-Kang Huang, Fred J. Meyer, Fabrizio Lombardi	Testing and testable designs for one-time programmable FPGAs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
21	John Marty Emmert, Dinesh K. Bhatia	A Fault Tolerant Technique for FPGAs.	J. Electron. Test.	2000	DBLP DOI BibTeX RDF	incremental reconfiguration, incremental routing, incremental placement, fault tolerance, FPGA
21	Yao-Wen Chang, Kai Zhu 0001, D. F. Wong 0001	Timing-driven routing for symmetrical array-based FPGAs.	ACM Trans. Design Autom. Electr. Syst.	2000	DBLP DOI BibTeX RDF	field-programmable gate array, synthesis, layout, computer-aided design of VLSI
21	Steven J. E. Wilton	Heterogeneous technology mapping for FPGAs with dual-port embedded memory arrays.	FPGA	2000	DBLP DOI BibTeX RDF
21	Rolf Enzler, Tobias Jeger, Didier Cottet, Gerhard Tröster	High-Level Area and Performance Estimation of Hardware Building Blocks on FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
21	Joerg Abke, Erich Barke	CoMGen: Direct Mapping of Arbitrary Components into LUT-Based FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
21	Holger Kropp, Carsten Reuter	A Mapping Methodology for Code Trees onto LUT-Based FPGAs.	FPL	2000	DBLP DOI BibTeX RDF
21	John Marty Emmert, Charles E. Stroud, Brandon Skaggs, Miron Abramovici	Dynamic Fault Tolerance in FPGAs via Partial Reconfiguration.	FCCM	2000	DBLP DOI BibTeX RDF
21	Steven J. E. Wilton, Jonathan Rose, Zvonko G. Vranesic	The memory/logic interface in FPGAs with large embedded memory arrays.	IEEE Trans. Very Large Scale Integr. Syst.	1999	DBLP DOI BibTeX RDF
21	Joerg Abke, Erich Barke, Jörn Stohmann	A Universal Module Generator for LUT-Based FPGAs.	IEEE International Workshop on Rapid System Prototyping	1999	DBLP DOI BibTeX RDF	Multiplexor, Multiplexor Structure, FPGA, Technology Mapping, Module Generator
21	Parag K. Lala, Alfred L. Burress	A technique for designing self-checking logic for FPGAs.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
21	Vicente Baena Lecuyer, M. A. Aguirre, Antonio Jesús Torralba Silgado, Leopoldo García Franquelo, Julio Faura	Decoder-driven switching matrices in multicontext FPGAs: area reduction and their effect on routability.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
21	Bupesh Pandita, Subir K. Roy	Design and Implementation of Viterbi Decoder Using FPGAs.	VLSI Design	1999	DBLP DOI BibTeX RDF
21	Michel Renovell, Jean-Michel Portal, Joan Figueras, Yervant Zorian	Testing the Interconnect of RAM-Based FPGAs.	IEEE Des. Test Comput.	1998	DBLP DOI BibTeX RDF
21	Jason Cong, Songjie Xu	Technology Mapping for FPGAs with Embedded Memory Blocks.	FPGA	1998	DBLP DOI BibTeX RDF
21	Atsushi Takahara, Toshiaki Miyazaki, Takahiro Murooka, Masaru Katayama, Kazuhiro Hayashi, Akihiro Tsutsui, Takaki Ichimori, Ken-nosuke Fukami	More Wires and Fewer LUTs: A Design Methodology for FPGAs.	FPGA	1998	DBLP DOI BibTeX RDF
21	Jason Cong, Yean-Yow Hwang	Boolean Matching for Complex PLBs in LUT-based FPGAs with Application to Architecture Evaluation.	FPGA	1998	DBLP DOI BibTeX RDF
21	Helena Krupnova, Vu DucAnh Dinh, Gabriele Saucier	A Knowledge-Based System for Prototyping on FPFAs.	FPL	1998	DBLP DOI BibTeX RDF
21	Michael Eisenring, Jürgen Teich	Interfacing Hardware and Software.	FPL	1998	DBLP DOI BibTeX RDF	automatic interface synthesis, low power design, rapid prototyping, hardware/software codesign
21	Tero Rissa, Tommi Mäkeläinen, Jarkko Niittylahti, Jouni Siirtola	Fast Prototyping Using System Emulators.	FPL	1998	DBLP DOI BibTeX RDF
21	Yamin Li, Wanming Chu	Implementation of single precision floating point square root on FPGAs.	FCCM	1997	DBLP DOI BibTeX RDF