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Venues (Conferences, Journals, ...)
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GrowBag graphs for keyword ? (Num. hits/coverage)
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The graphs summarize 3674 occurrences of 1433 keywords
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Results
Found 5812 publication records. Showing 5812 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti |
Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence. |
MICRO |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta |
Optimal Positions of Twists in Global On-Chip Differential Interconnects. |
IEEE Trans. Very Large Scale Integr. Syst. |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud |
Frequency Selective Model Order Reduction via Spectral Zero Projection. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Min Pan, Chris C. N. Chu |
IPR: An Integrated Placement and Routing Algorithm. |
DAC |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Ajay Joshi, Jeffrey A. Davis |
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI). |
IEEE Trans. Very Large Scale Integr. Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Valeriy Sukharev |
Physically based simulation of electromigration-induced degradation mechanisms in dual-inlaid copper interconnects. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Guoqing Chen, Eby G. Friedman |
Low power repeaters driving RLC interconnects with delay and bandwidth constraints. |
ISCAS (1) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Syed M. Alam, Frank L. Wei, Chee Lip Gan, Carl V. Thompson, Donald E. Troxel |
Electromigration Reliability Comparison of Cu and Al Interconnects. |
ISQED |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Yan Lin 0001, Lei He 0001 |
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
programmable-Vdd, time slack, FPGA, low power |
26 | Andrew Labun |
Rapid method to account for process variation in full-chip capacitance extraction. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail |
Efficient model order reduction including skin effect. |
DAC |
2003 |
DBLP DOI BibTeX RDF |
simulation, VLSI, model order reduction, skin effect, RLC |
26 | Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh |
Pattern routing: use and theory for increasing predictability andavoiding coupling. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Ivo Bolsens |
Challenges and Opportunities for FPGA Platforms. |
FPL |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Joachim Worringen, Andreas Gäer, Frank Reker |
Exploiting Transparent Remote Memory Access for Non-Contiguous- and One-Sided-Communication. |
IPDPS |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Krishna Sekar, Sujit Dey |
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. |
VTS |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian |
Switching activity generation with automated BIST synthesis forperformance testing of interconnects. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Martin Bächtold, Mirko Spasojevic, Christian Lage, Per B. Ljung |
A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Debendra Das Sharma |
System on a Package Innovations With Universal Chiplet Interconnect Express (UCIe) Interconnect. |
IEEE Micro |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Julien Emmanuel |
A full stack simulator for HPC: Multi-level modelling of the BXI interconnect to predict the performance of MPI applications. (Un simulateur pour le calcul haute performance : modélisation multi-niveau de l'interconnect BXI pour prédire les performances d'applications MPI). |
|
2023 |
RDF |
|
23 | Xiuyan Zhang, Shantanu Dutt |
Limiting Interconnect Heating in Power-Driven Physical Synthesis. |
SLIP |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Ning Wang, Shiyou Yang, Zhuoxiang Ren, Huifang Wang |
An Improved Structure-Preserving Reduced-Order Interconnect Macromodeling for Large-Scale Equation Sets of Transient Interconnect Circuit Problems. |
IEEE Access |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Minmin Jiang, Vasilis F. Pavlidis |
Performance-Aware Interconnect Delay Insertion Against EM Side-Channel Attacks. |
SLIP |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Patrick Groeneveld |
Wafer scale interconnect and pathfinding for machine learning hardware (invited). |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Saptadeep Pal, Puneet Gupta 0001 |
Pathfinding for 2.5D interconnect technologies. |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Tuck-Boon Chan, Andrew B. Kahng, Mingyu Woo |
Revisiting inherent noise floors for interconnect prediction. |
SLIP |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Boris Vaisband, Subramanian S. Iyer |
Communication Considerations for Silicon Interconnect Fabric. |
SLIP |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Kwangsoo Han, Andrew B. Kahng, Christopher Moyes, Alex Zelikovsky |
A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions. |
SLIP@DAC |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Siti Sarah Md Sallah, Sawal Hamid Md. Ali, P. Susthitha Menon, Nurjuliana Juhari, Md. Shabiul Islam |
Comparative Performances of SOI-Based Optical Interconnect vs. Electrical Interconnect in Analog Electronic Applications. |
IEICE Trans. Electron. |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Gabriele Miorandi, Mahdi Tala, Marco Balboni, Luca Ramini, Davide Bertozzi |
Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems. |
AISTECS@HiPEAC |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Hai-Bao Chen, Sheldon X.-D. Tan, Valeriy Sukharev, Xin Huang 0003, Taeyoung Kim 0001 |
Interconnect reliability modeling and analysis for multi-branch interconnect trees. |
DAC |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Sai Manoj P. D., Kanwen Wang, Hantao Huang, Hao Yu 0001 |
Smart I/Os: a data-pattern aware 2.5D interconnect with space-time multiplexing. |
SLIP |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Andrew B. Kahng, Mulong Luo, Siddhartha Nath |
SI for free: machine learning of interconnect coupling delay and transition effects. |
SLIP |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Yuichiro Ajima, Tomohiro Inoue, Shinya Hiramoto, Shunji Uno, Shinji Sumimoto, Kenichi Miura, Naoyuki Shida, Takahiro Kawashima, Takayuki Okamoto, Osamu Moriyama, Yoshiro Ikeda, Takekazu Tabata, Takahide Yoshikawa, Ken Seki, Toshiyuki Shimizu |
Tofu Interconnect 2: System-on-Chip Integration of High-Performance Interconnect. |
ISC |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Rasit Onur Topaloglu |
Chip-scale physical interconnect models (Tutorial). |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li 0002 |
Toward quantifying the IC design value of interconnect technology improvements. |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Andrew B. Kahng, Seokhyeong Kang, Hyein Lee 0001, Siddhartha Nath, Jyoti Wadhwani |
Learning-based approximation of interconnect delay and slew in signoff timing tools. |
SLIP |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Hongbo Zhang 0001, Yunfei Deng, Jongwook Kye, Martin D. F. Wong |
Impact of lithography retargeting process on low level interconnect in 20nm technology. |
SLIP |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Xiangyu Chen, Jiale Liang, H.-S. Philip Wong |
Interconnect scaling into the sub-10nm regime. |
SLIP |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Ganapati Srinivasa |
Heterogeneity and interconnect. |
SLIP |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Ahmad Atghiaee, Nasser Masoumi |
A Predictive and Accurate Interconnect Density Function: The Core of a Novel Interconnect-Centric Prediction Engine. |
IEEE Trans. Very Large Scale Integr. Syst. |
2011 |
DBLP DOI BibTeX RDF |
|
23 | Tom English, Emanuel M. Popovici |
Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for Cryptographic accelerators. |
NOCS |
2011 |
DBLP DOI BibTeX RDF |
|
23 | T. Alam, Rohit Dhiman, Rajeevan Chandel |
Resistive analysis of mixed carbon nanotube bundle interconnect and its comparison with copper interconnect. |
ICWET |
2011 |
DBLP DOI BibTeX RDF |
|
23 | Chen-Ling Chou, Radu Marculescu, Ümit Y. Ogras, Satrajit Chatterjee, Michael Kishinevsky, Dmitrii Loukianov |
System interconnect design exploration for embedded MPSoCs. |
SLIP |
2011 |
DBLP DOI BibTeX RDF |
|
23 | Di-An Li, Malgorzata Marek-Sadowska, Bill Lee |
On-chip em-sensitive interconnect structures. |
SLIP |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Shekhar Y. Borkar |
Future of interconnect fabric: a contrarian view. |
SLIP |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy 0001 |
Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation. |
IEEE Trans. Circuits Syst. I Regul. Pap. |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Kaustav Banerjee |
Graphene based nanomaterials for VLSI interconnect and energy-storage applications. |
SLIP |
2009 |
DBLP DOI BibTeX RDF |
carbon nanomaterials, graphene nano-ribbons, interconnects, carbon nanotubes, passives |
23 | Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic |
Floorplan-based FPGA interconnect power estimation in DSP circuits. |
SLIP |
2009 |
DBLP DOI BibTeX RDF |
fpga, low power, interconnects, power estimation |
23 | Payman Zarkesh-Ha, Ken Doniger |
Stochastic interconnect layout sensitivity model. |
SLIP |
2007 |
DBLP DOI BibTeX RDF |
critical area analysis, layout sensitivity, reliability, stochastic model, yield, design for manufacturability, defect density |
23 | Chandu Visweswariah |
Statistical analysis and optimization in the presence of gate and interconnect delay variations. |
SLIP |
2006 |
DBLP DOI BibTeX RDF |
variability, robust optimization, statistical timing |
23 | Louis Scheffer |
An overview of on-chip interconnect variation. |
SLIP |
2006 |
DBLP DOI BibTeX RDF |
causes of variability, on-chip variation, design rules |
23 | Sudhakar Muddu |
Estimation needs for future networking systems interconnect. |
SLIP |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout |
Getting more out of Donath's hierarchical model for interconnect prediction. |
SLIP |
2002 |
DBLP DOI BibTeX RDF |
Donath's wirelength estimation technique, a priori wirelength estimation, partitioning based placement |
23 | Phillip Christie |
Managing interconnect resources (tutorial). |
SLIP |
2000 |
DBLP DOI BibTeX RDF |
|
23 | James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl |
Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. |
SLIP |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Keh-Jeng Chang, Soo-Young Oh, Ken Lee |
HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs. |
ICCAD |
1991 |
DBLP DOI BibTeX RDF |
|
23 | Zhen Wang, Ding Xie, Jinmei Lai |
FPGA Interconnect Architecture Exploration Based on a Statistical Model. |
FPL |
2011 |
DBLP DOI BibTeX RDF |
hops, model, FPGA, interconnect |
23 | Yuichiro Ajima, Yuzo Takagi, Tomohiro Inoue, Shinya Hiramoto, Toshiyuki Shimizu |
The Tofu Interconnect. |
Hot Interconnects |
2011 |
DBLP DOI BibTeX RDF |
high-performance computing, topology, interconnect |
23 | Heiner Litz, Maximilian Thürmer, Ulrich Brüning 0001 |
TCCluster: A Cluster Architecture Utilizing the Processor Host Interface as a Network Interconnect. |
CLUSTER |
2010 |
DBLP DOI BibTeX RDF |
HyperTransport, AMD, Opteron, interconnect, HPC, Low latency, high bandwidth |
23 | Kee Beom Kim, Seong Min Jo, Jin Woo Song, Ki-Seok Chung, Yong Ho Song |
Performance evaluation of on-chip interconnect IP using CBR traffic generator model. |
ICHIT |
2009 |
DBLP DOI BibTeX RDF |
on-chip interconnect IP, simulation, traffic generator |
23 | Valerij Matrose, Carsten Gremzow |
Improved placement for hierarchical FPGAs exploiting local interconnect resources. |
SBCCI |
2009 |
DBLP DOI BibTeX RDF |
FPGA, interconnect, placement |
23 | Krishna Saraswat |
Performance comparison of cu/low-k, carbon nanotube, and optics for on-chip and off-chip interconnects. |
SLIP |
2009 |
DBLP DOI BibTeX RDF |
copper, energy per bit, power, latency, bandwidth, optical interconnect, carbon nanotube |
23 | Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez |
Efficient tree topology for FPGA interconnect network. |
ACM Great Lakes Symposium on VLSI |
2008 |
DBLP DOI BibTeX RDF |
fpga, routing, interconnect, hierarchy, rent's rule |
23 | Simon W. Moore, Daniel Greenfield |
The next resource war: computation vs. communication. |
SLIP |
2008 |
DBLP DOI BibTeX RDF |
fractal structure, temporal interconnect, tera-scale, networks-on-chip, CMP, communication complexity, Rent's rule |
23 | Katherine Shu-Min Li, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen |
IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. |
J. Electron. Test. |
2007 |
DBLP DOI BibTeX RDF |
oscillation ring (OR) test scheme, open faults, crosstalk glitches, IEEE P1500, wrapper cell design, stuck-at faults, delay faults, SOC testing, interconnect test |
23 | Haikun Zhu, Rui Shi 0003, Chung-Kuan Cheng, Hongyu Chen |
Approaching Speed-of-light Distortionless Communication for On-chip Interconnect. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
0.10 micron, speed-of-light distortionless communication, surfliner on-chip distortionless transmission line scheme, shunt resistors, shunt conductance, single-ended microstrip line, 10 Gbit/s, on-chip interconnect |
23 | Haikun Zhu, Yi Zhu 0002, Chung-Kuan Cheng, David M. Harris |
An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization. |
ASP-DAC |
2007 |
DBLP DOI BibTeX RDF |
64 bit, interconnect-centric approach, fanout splitting, cell order optimization, logarithmic cyclic shifter design, demultiplexers, shifting path, nonshifting paths, accumulated wire load, switching probabilities, integer linear programming |
23 | Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou |
Reliable crosstalk-driven interconnect optimization. |
ACM Trans. Design Autom. Electr. Syst. |
2006 |
DBLP DOI BibTeX RDF |
post-layout optimization, VLSI, interconnect, lagrangian relaxation |
23 | Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh |
BIST for Network-on-Chip Interconnect Infrastructures. |
VTS |
2006 |
DBLP DOI BibTeX RDF |
interconnect infrastructure, unicast test, multicast test, built-in self-test, network-on-chip |
23 | Manuel Saldaña, Lesley Shannon, Paul Chow |
The routability of multiprocessor network topologies in FPGAs. |
SLIP |
2006 |
DBLP DOI BibTeX RDF |
FPGA, multiprocessor, network-on-chip, topology, interconnect |
23 | Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei |
A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices. |
J. Electron. Test. |
2005 |
DBLP DOI BibTeX RDF |
timing specifications testing, test environment, tester OTA and yield, high-speed interconnect testing, yield analysis |
23 | André DeHon |
Design of programmable interconnect for sublithographic programmable logic arrays. |
FPGA |
2005 |
DBLP DOI BibTeX RDF |
Manhattan mesh, sublithographic architecture, programmable logic arrays, nanowires, programmable interconnect |
23 | Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell |
Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. |
VTS |
2005 |
DBLP DOI BibTeX RDF |
FPAA testing, Mixed-signal test, interconnect testing, oscillation-based test |
23 | Quming Zhou, Kartik Mohanram, Athanasios C. Antoulas |
Structure preserving reduction of frequency-dependent interconnect. |
DAC |
2005 |
DBLP DOI BibTeX RDF |
interconnect, model-order reduction, skin effect |
23 | Lakshmi Kalpana Vakati, Janet Meiling Wang |
A new multi-ramp driver model with RLC interconnect load. |
ISPD |
2004 |
DBLP DOI BibTeX RDF |
inductance criteria, multi-ramp driver model, transmission line effects, interconnect modeling, effective capacitance |
23 | Raphael Rubin, André DeHon |
Design of FPGA interconnect for multilevel metalization. |
FPGA |
2003 |
DBLP DOI BibTeX RDF |
multi-level metalization, FPGA, interconnect, hierarchical, mesh-of-trees |
23 | Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov |
Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing. |
Asian Test Symposium |
2003 |
DBLP DOI BibTeX RDF |
Timing specifications testing, Test Environment, Tester OTA and yield, High-speed interconnect testing, Yield analysis |
23 | John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan Zhou, John F. McDonald 0001, Russell P. Kraft |
3D direct vertical interconnect microprocessors test vehicle. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
SiGe HBT, direct vertical integration, finite state machine, interconnect, microprocessor, adder, register file, 3D integration, current mode logic |
23 | Magdy A. El-Moursy, Eby G. Friedman |
Optimum wire sizing of RLC interconnect with repeaters. |
ACM Great Lakes Symposium on VLSI |
2003 |
DBLP DOI BibTeX RDF |
power delay product, transient power dissipation, propagation delay, repeater insertion, wire sizing, RLC interconnect |
23 | Partha Pratim Pande, Cristian Grecu, André Ivanov |
High-Throughput Switch-Based Interconnect for Future SoCs. |
IWSOC |
2003 |
DBLP DOI BibTeX RDF |
SoC, Wormhole Routing, Virtual Channels, Interconnect Architecture |
23 | Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev |
Interconnect enhancements for a high-speed PLD architecture. |
FPGA |
2002 |
DBLP DOI BibTeX RDF |
FPGA, architecture, interconnect, programmable logic |
23 | Stephen E. Krufka, Phillip Christie |
Terminal optimization analysis for functional block re-use. |
SLIP |
2002 |
DBLP DOI BibTeX RDF |
optimization, SoC, interconnect, Rent's rule |
23 | Bin Liu, Fabrizio Lombardi, Wei-Kang Huang |
Testing programmable interconnect systems: an algorithmic approach. |
Asian Test Symposium |
2000 |
DBLP DOI BibTeX RDF |
programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits |
23 | Krishna Saraswat, Shukri J. Souri, Kaustav Banerjee, Pawan Kapur |
Performance analysis and technology of 3-D ICs. |
SLIP |
2000 |
DBLP DOI BibTeX RDF |
VLSI, interconnect, circuits, ICs, 3-D |
23 | Dirk Stroobandt, Herwig Van Marck |
Efficient representation of interconnection length distributions using generating polynomials. |
SLIP |
2000 |
DBLP DOI BibTeX RDF |
interconnect length distributions, enumeration, VLSI CAD, generating polynomials |
23 | W. J. Bainbridge, Stephen B. Furber |
Asynchronous Macrocell Interconnect using MARBLE. |
ASYNC |
1998 |
DBLP DOI BibTeX RDF |
Macrocell Bus, VLSI, Interconnect, Asynchronous |
23 | Takumi Okamoto, Jason Cong |
Buffered Steiner tree construction with wire sizing for interconnect layout optimization. |
ICCAD |
1996 |
DBLP DOI BibTeX RDF |
Steiner Tree, Buffer Insertion, Interconnect Optimization, Wire Sizing |
23 | Prasasth Palnati, Mario Gerla, Emilio Leonardi |
Deadlock-free routing in an optical interconnect for high-speed wormhole routing networks. |
ICPADS |
1996 |
DBLP DOI BibTeX RDF |
high-speed wormhole routing networks, Supercomputer SuperNet, two-level hierarchical high-speed network, electronic mesh fabric, WDM optical backbone network, metropolitan area, campus area, backpressure hop-by-hop flow control mechanism, shufflenet multihop virtual topology, physical channels, up/down deadlock free routing scheme, bidirectional shufflenet, optical backbone, multiprocessor interconnection networks, network routing, virtual channels, wavelength division multiplexing, optical interconnections, optical interconnect, deadlock-free routing, deadlock prevention |
23 | Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai |
Transformation of min-max optimization to least-square estimation and application to interconnect design optimization. |
ICCD |
1995 |
DBLP DOI BibTeX RDF |
min-max optimization transformation, interconnect design optimization, tighter bound, circuit layout CAD, minimisation, least squares approximations, multichip modules, multichip modules, least-square estimation, minimax techniques |
23 | Tülin Erdim Mangir, Algirdas Avizienis |
Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs. |
IEEE Trans. Computers |
1982 |
DBLP DOI BibTeX RDF |
VLSI fault tolerance, Interconnect area estimates, redundancy partitioning, redundancy placement, regular designs, VLSI yield improvement |
23 | Chris C. N. Chu, D. F. Wong 0001 |
A new approach to simultaneous buffer insertion and wire sizing. |
ICCAD |
1997 |
DBLP DOI BibTeX RDF |
interconnect delay minimization, interconnect area minimization, convex quadratic programming, buffer insertion, wire sizing |
22 | Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton |
The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). |
FPGA |
2010 |
DBLP DOI BibTeX RDF |
structured asics, via programmable fabric |
22 | Zhuo Li 0001, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou |
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. |
ISPD |
2010 |
DBLP DOI BibTeX RDF |
gate duplication, physical synthesis, timing-driven placement |
22 | Bruce Mathewson |
The evolution of SOC interconnect and how NOC fits within it. |
DAC |
2010 |
DBLP DOI BibTeX RDF |
AMBA AXI, network on chip |
22 | Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria |
An interconnect-aware delay model for dynamic voltage scaling in NM technologies. |
ACM Great Lakes Symposium on VLSI |
2009 |
DBLP DOI BibTeX RDF |
dynamic voltage scaling (dvs), interconnects, delay model |
22 | Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin |
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras |
Experimental Characterization of CMOS Interconnect Open Defects. |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross, Isaac L. Chuang, Frederic T. Chong |
High-level interconnect model for the quantum logic array architecture. |
ACM J. Emerg. Technol. Comput. Syst. |
2008 |
DBLP DOI BibTeX RDF |
QLA, Quantum computer architecture design, teleportation, fault tolerance, large scale, quantum |
22 | Yu Hu 0002, Yan Lin 0001, Lei He 0001, Tim Tuan |
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. |
ACM Trans. Design Autom. Electr. Syst. |
2008 |
DBLP DOI BibTeX RDF |
FPGA, Low power, retiming |
22 | Md. Sajjad Rahaman, Masud H. Chowdhury |
BER performance comparison between CDMA and UWB for RF/wireless interconnect application. |
EIT |
2008 |
DBLP DOI BibTeX RDF |
|
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