|
|
Venues (Conferences, Journals, ...)
|
|
GrowBag graphs for keyword ? (Num. hits/coverage)
Group by:
The graphs summarize 3674 occurrences of 1433 keywords
|
|
|
Results
Found 5812 publication records. Showing 5812 according to the selection in the facets
Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
26 | Natalie D. Enright Jerger, Li-Shiuan Peh, Mikko H. Lipasti |
Virtual tree coherence: Leveraging regions and in-network multicast trees for scalable cache coherence. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MICRO ![In: 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), November 8-12, 2008, Lake Como, Italy, pp. 35-46, 2008, IEEE Computer Society, 978-1-4244-2836-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
26 | Eisse Mensink, Daniël Schinkel, Eric A. M. Klumperink, Ed van Tuijl, Bram Nauta |
Optimal Positions of Twists in Global On-Chip Differential Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 15(4), pp. 438-446, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Mehboob Alam, Arthur Nieuwoudt, Yehia Massoud |
Frequency Selective Model Order Reduction via Spectral Zero Projection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 379-383, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Min Pan, Chris C. N. Chu |
IPR: An Integrated Placement and Routing Algorithm. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 59-62, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
26 | Ajay Joshi, Jeffrey A. Davis |
Wave-pipelined multiplexed (WPM) routing for gigascale integration (GSI). ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 13(8), pp. 899-910, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Valeriy Sukharev |
Physically based simulation of electromigration-induced degradation mechanisms in dual-inlaid copper interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(9), pp. 1326-1335, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Guoqing Chen, Eby G. Friedman |
Low power repeaters driving RLC interconnects with delay and bandwidth constraints. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 596-599, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Syed M. Alam, Frank L. Wei, Chee Lip Gan, Carl V. Thompson, Donald E. Troxel |
Electromigration Reliability Comparison of Cu and Al Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 303-308, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
26 | Yan Lin 0001, Lei He 0001 |
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 720-725, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
programmable-Vdd, time slack, FPGA, low power |
26 | Andrew Labun |
Rapid method to account for process variation in full-chip capacitance extraction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(6), pp. 941-951, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
26 | Shizhong Mei, Chirayu S. Amin, Yehea I. Ismail |
Efficient model order reduction including skin effect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 40th Design Automation Conference, DAC 2003, Anaheim, CA, USA, June 2-6, 2003, pp. 232-237, 2003, ACM, 1-58113-688-9. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
simulation, VLSI, model order reduction, skin effect, RLC |
26 | Ryan Kastner, Elaheh Bozorgzadeh, Majid Sarrafzadeh |
Pattern routing: use and theory for increasing predictability andavoiding coupling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 21(7), pp. 777-790, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Ivo Bolsens |
Challenges and Opportunities for FPGA Platforms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings, pp. 391-392, 2002, Springer, 3-540-44108-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Joachim Worringen, Andreas Gäer, Frank Reker |
Exploiting Transparent Remote Memory Access for Non-Contiguous- and One-Sided-Communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 16th International Parallel and Distributed Processing Symposium (IPDPS 2002), 15-19 April 2002, Fort Lauderdale, FL, USA, CD-ROM/Abstracts Proceedings, 2002, IEEE Computer Society, 0-7695-1573-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Krishna Sekar, Sujit Dey |
LI-BIST: A Low-Cost Self-Test Scheme for SoC Logic Cores and Interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 20th IEEE VLSI Test Symposium (VTS 2002), Without Testing It's a Gamble, 28 April - 2 May 2002, Monterey, CA, USA, pp. 417-422, 2002, IEEE Computer Society, 0-7695-1570-3. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
26 | Rajesh Pendurkar, Abhijit Chatterjee, Yervant Zorian |
Switching activity generation with automated BIST synthesis forperformance testing of interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 20(9), pp. 1143-1158, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
26 | Martin Bächtold, Mirko Spasojevic, Christian Lage, Per B. Ljung |
A system for full-chip and critical net parasitic extraction for ULSI interconnects using a fast 3-D field solver. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(3), pp. 325-338, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Debendra Das Sharma |
System on a Package Innovations With Universal Chiplet Interconnect Express (UCIe) Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Micro ![In: IEEE Micro 43(2), pp. 76-85, March - April 2023. The full citation details ...](Pics/full.jpeg) |
2023 |
DBLP DOI BibTeX RDF |
|
23 | Julien Emmanuel |
A full stack simulator for HPC: Multi-level modelling of the BXI interconnect to predict the performance of MPI applications. (Un simulateur pour le calcul haute performance : modélisation multi-niveau de l'interconnect BXI pour prédire les performances d'applications MPI). ![Search on Bibsonomy](Pics/bibsonomy.png) |
|
2023 |
RDF |
|
23 | Xiuyan Zhang, Shantanu Dutt |
Limiting Interconnect Heating in Power-Driven Physical Synthesis. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: Proceedings of the 24th ACM/IEEE Workshop on System Level Interconnect Pathfinding, SLIP 2022, San Diego, California, 3 November 2022, pp. 2:1-2:7, 2022, ACM, 978-1-4503-9536-6. The full citation details ...](Pics/full.jpeg) |
2022 |
DBLP DOI BibTeX RDF |
|
23 | Ning Wang, Shiyou Yang, Zhuoxiang Ren, Huifang Wang |
An Improved Structure-Preserving Reduced-Order Interconnect Macromodeling for Large-Scale Equation Sets of Transient Interconnect Circuit Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Access ![In: IEEE Access 9, pp. 132150-132157, 2021. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Minmin Jiang, Vasilis F. Pavlidis |
Performance-Aware Interconnect Delay Insertion Against EM Side-Channel Attacks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2021, Munich, Germany, November 4, 2021, pp. 25-32, 2021, IEEE, 978-1-6654-0083-1. The full citation details ...](Pics/full.jpeg) |
2021 |
DBLP DOI BibTeX RDF |
|
23 | Patrick Groeneveld |
Wafer scale interconnect and pathfinding for machine learning hardware (invited). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: SLIP '20: System-Level Interconnect - Problems and Pathfinding Workshop, San Diego, California, November 5, 2020, pp. 7, 2020, ACM, 978-1-4503-8106-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Saptadeep Pal, Puneet Gupta 0001 |
Pathfinding for 2.5D interconnect technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: SLIP '20: System-Level Interconnect - Problems and Pathfinding Workshop, San Diego, California, November 5, 2020, pp. 3, 2020, ACM, 978-1-4503-8106-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Tuck-Boon Chan, Andrew B. Kahng, Mingyu Woo |
Revisiting inherent noise floors for interconnect prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: SLIP '20: System-Level Interconnect - Problems and Pathfinding Workshop, San Diego, California, November 5, 2020, pp. 10, 2020, ACM, 978-1-4503-8106-2. The full citation details ...](Pics/full.jpeg) |
2020 |
DBLP DOI BibTeX RDF |
|
23 | Boris Vaisband, Subramanian S. Iyer |
Communication Considerations for Silicon Interconnect Fabric. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 21st ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2019, Las Vegas, NV, USA, June 1-2, 2019, pp. 1-6, 2019, IEEE, 978-1-7281-2818-4. The full citation details ...](Pics/full.jpeg) |
2019 |
DBLP DOI BibTeX RDF |
|
23 | Kwangsoo Han, Andrew B. Kahng, Christopher Moyes, Alex Zelikovsky |
A study of optimal cost-skew tradeoff and remaining suboptimality in interconnect tree constructions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP@DAC ![In: Proceedings of the 20th System Level Interconnect Prediction Workshop, SLIP@DAC 2018, San Francisco, CA, USA, June 23, 2018, pp. 2:1-2:8, 2018, ACM. The full citation details ...](Pics/full.jpeg) |
2018 |
DBLP DOI BibTeX RDF |
|
23 | Siti Sarah Md Sallah, Sawal Hamid Md. Ali, P. Susthitha Menon, Nurjuliana Juhari, Md. Shabiul Islam |
Comparative Performances of SOI-Based Optical Interconnect vs. Electrical Interconnect in Analog Electronic Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEICE Trans. Electron. ![In: IEICE Trans. Electron. 100-C(7), pp. 655-661, 2017. The full citation details ...](Pics/full.jpeg) |
2017 |
DBLP DOI BibTeX RDF |
|
23 | Gabriele Miorandi, Mahdi Tala, Marco Balboni, Luca Ramini, Davide Bertozzi |
Evolutionary vs. Revolutionary Interconnect Technologies for Future Low-Power Multi-Core Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AISTECS@HiPEAC ![In: Proceedings of the 1st International Workshop on Advanced Interconnect Solutions and Technologies for Emerging Computing Systems, AISTECS@HiPEAC 2016, Prague, Czech Republic, January 18, 2016, pp. 3:1-3:6, 2016, ACM, 978-1-4503-4084-7. The full citation details ...](Pics/full.jpeg) |
2016 |
DBLP DOI BibTeX RDF |
|
23 | Hai-Bao Chen, Sheldon X.-D. Tan, Valeriy Sukharev, Xin Huang 0003, Taeyoung Kim 0001 |
Interconnect reliability modeling and analysis for multi-branch interconnect trees. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 52nd Annual Design Automation Conference, San Francisco, CA, USA, June 7-11, 2015, pp. 90:1-90:6, 2015, ACM, 978-1-4503-3520-1. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Sai Manoj P. D., Kanwen Wang, Hantao Huang, Hao Yu 0001 |
Smart I/Os: a data-pattern aware 2.5D interconnect with space-time multiplexing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2015, San Francisco, CA, USA, June 6, 2015, pp. 1-6, 2015, IEEE Computer Society, 978-1-4673-8189-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Andrew B. Kahng, Mulong Luo, Siddhartha Nath |
SI for free: machine learning of interconnect coupling delay and transition effects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2015 ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2015, San Francisco, CA, USA, June 6, 2015, pp. 1-8, 2015, IEEE Computer Society, 978-1-4673-8189-5. The full citation details ...](Pics/full.jpeg) |
2015 |
DBLP DOI BibTeX RDF |
|
23 | Yuichiro Ajima, Tomohiro Inoue, Shinya Hiramoto, Shunji Uno, Shinji Sumimoto, Kenichi Miura, Naoyuki Shida, Takahiro Kawashima, Takayuki Okamoto, Osamu Moriyama, Yoshiro Ikeda, Takekazu Tabata, Takahide Yoshikawa, Ken Seki, Toshiyuki Shimizu |
Tofu Interconnect 2: System-on-Chip Integration of High-Performance Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISC ![In: Supercomputing - 29th International Conference, ISC 2014, Leipzig, Germany, June 22-26, 2014. Proceedings, pp. 498-507, 2014, Springer, 978-3-319-07517-4. The full citation details ...](Pics/full.jpeg) |
2014 |
DBLP DOI BibTeX RDF |
|
23 | Rasit Onur Topaloglu |
Chip-scale physical interconnect models (Tutorial). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013, Austin, TX, USA, June 2, 2013, pp. 1-3, 2013, IEEE Computer Society, 978-1-4673-6173-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Tuck-Boon Chan, Andrew B. Kahng, Jiajia Li 0002 |
Toward quantifying the IC design value of interconnect technology improvements. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013, Austin, TX, USA, June 2, 2013, pp. 1-6, 2013, IEEE Computer Society, 978-1-4673-6173-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Andrew B. Kahng, Seokhyeong Kang, Hyein Lee 0001, Siddhartha Nath, Jyoti Wadhwani |
Learning-based approximation of interconnect delay and slew in signoff timing tools. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: ACM/IEEE International Workshop on System Level Interconnect Prediction, SLIP 2013, Austin, TX, USA, June 2, 2013, pp. 1-8, 2013, IEEE Computer Society, 978-1-4673-6173-6. The full citation details ...](Pics/full.jpeg) |
2013 |
DBLP DOI BibTeX RDF |
|
23 | Hongbo Zhang 0001, Yunfei Deng, Jongwook Kye, Martin D. F. Wong |
Impact of lithography retargeting process on low level interconnect in 20nm technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 3-10, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Xiangyu Chen, Jiale Liang, H.-S. Philip Wong |
Interconnect scaling into the sub-10nm regime. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 2, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Ganapati Srinivasa |
Heterogeneity and interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction, SLIP '12, San Francisco, CA, USA, June 3, 2012, pp. 1, 2012, ACM, 978-1-4503-1437-4. The full citation details ...](Pics/full.jpeg) |
2012 |
DBLP DOI BibTeX RDF |
|
23 | Ahmad Atghiaee, Nasser Masoumi |
A Predictive and Accurate Interconnect Density Function: The Core of a Novel Interconnect-Centric Prediction Engine. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 19(9), pp. 1704-1717, 2011. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
23 | Tom English, Emanuel M. Popovici |
Interconnect Physical Analyser (IPAA) applied to the design of scalable Network-on-Chip interconnect for Cryptographic accelerators. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NOCS ![In: NOCS 2011, Fifth ACM/IEEE International Symposium on Networks-on-Chip, Pittsburgh, Pennsylvania, USA, May 1-4, 2011, pp. 225-232, 2011, ACM/IEEE Computer Society, 978-1-4503-0720-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
23 | T. Alam, Rohit Dhiman, Rajeevan Chandel |
Resistive analysis of mixed carbon nanotube bundle interconnect and its comparison with copper interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICWET ![In: Proceedings of the ICWET '11 International Conference & Workshop on Emerging Trends in Technology, Mumbai, Maharashtra, India, February 25 - 26, 2011, pp. 1157-1160, 2011, ACM, 978-1-4503-0449-8. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
23 | Chen-Ling Chou, Radu Marculescu, Ümit Y. Ogras, Satrajit Chatterjee, Michael Kishinevsky, Dmitrii Loukianov |
System interconnect design exploration for embedded MPSoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: 2011 International Workshop on System Level Interconnect Prediction, SLIP 2011, San Diego, CA, USA, June 5, 2011, pp. 1-8, 2011, IEEE Computer Society, 978-1-4577-1240-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
|
23 | Di-An Li, Malgorzata Marek-Sadowska, Bill Lee |
On-chip em-sensitive interconnect structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 43-50, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Shekhar Y. Borkar |
Future of interconnect fabric: a contrarian view. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010, pp. 1-2, 2010, ACM, 978-1-4503-0037-7. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
|
23 | Myeong-Eun Hwang, Seong-Ook Jung, Kaushik Roy 0001 |
Slope Interconnect Effort: Gate-Interconnect Interdependent Delay Modeling for Early CMOS Circuit Simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Circuits Syst. I Regul. Pap. ![In: IEEE Trans. Circuits Syst. I Regul. Pap. 56-I(7), pp. 1428-1441, 2009. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
23 | Kaustav Banerjee |
Graphene based nanomaterials for VLSI interconnect and energy-storage applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 105-106, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
carbon nanomaterials, graphene nano-ribbons, interconnects, carbon nanotubes, passives |
23 | Ruzica Jevtic, Carlos Carreras, Vukasin Pejovic |
Floorplan-based FPGA interconnect power estimation in DSP circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 53-60, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fpga, low power, interconnects, power estimation |
23 | Payman Zarkesh-Ha, Ken Doniger |
Stochastic interconnect layout sensitivity model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), Austin, Texas, USA, March 17-18, 2007, Proceedings, pp. 9-14, 2007, ACM, 978-1-59593-622-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
critical area analysis, layout sensitivity, reliability, stochastic model, yield, design for manufacturability, defect density |
23 | Chandu Visweswariah |
Statistical analysis and optimization in the presence of gate and interconnect delay variations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 37, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
variability, robust optimization, statistical timing |
23 | Louis Scheffer |
An overview of on-chip interconnect variation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 27-28, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
causes of variability, on-chip variation, design rules |
23 | Sudhakar Muddu |
Estimation needs for future networking systems interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 41-44, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
23 | Joni Dambre, Peter Verplaetse, Dirk Stroobandt, Jan Van Campenhout |
Getting more out of Donath's hierarchical model for interconnect prediction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 9-16, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Donath's wirelength estimation technique, a priori wirelength estimation, partitioning based placement |
23 | Phillip Christie |
Managing interconnect resources (tutorial). ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 1-51, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | James W. Joyner, Payman Zarkesh-Ha, Jeffrey A. Davis, James D. Meindl |
Vertical pitch limitations on performance enhancement in bonded three-dimensional interconnect architectures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 123-127, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
23 | Keh-Jeng Chang, Soo-Young Oh, Ken Lee |
HIVE: An Efficient Interconnect Capacitance Extractor to Support Submicron Multilevel Interconnect Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 1991 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1993, Santa Clara, CA, USA, November 11-14, 1991. Digest of Technical Papers, pp. 294-297, 1991, IEEE Computer Society, 0-8186-2157-5. The full citation details ...](Pics/full.jpeg) |
1991 |
DBLP DOI BibTeX RDF |
|
23 | Zhen Wang, Ding Xie, Jinmei Lai |
FPGA Interconnect Architecture Exploration Based on a Statistical Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: International Conference on Field Programmable Logic and Applications, FPL 2011, September 5-7, Chania, Crete, Greece, pp. 447-452, 2011, IEEE Computer Society, 978-1-4577-1484-9. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
hops, model, FPGA, interconnect |
23 | Yuichiro Ajima, Yuzo Takagi, Tomohiro Inoue, Shinya Hiramoto, Toshiyuki Shimizu |
The Tofu Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hot Interconnects ![In: IEEE 19th Annual Symposium on High Performance Interconnects, HOTI 2011, Santa Clara, CA, USA, August 24-26, 2011, pp. 87-94, 2011, IEEE Computer Society, 978-1-4577-1563-1. The full citation details ...](Pics/full.jpeg) |
2011 |
DBLP DOI BibTeX RDF |
high-performance computing, topology, interconnect |
23 | Heiner Litz, Maximilian Thürmer, Ulrich Brüning 0001 |
TCCluster: A Cluster Architecture Utilizing the Processor Host Interface as a Network Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CLUSTER ![In: Proceedings of the 2010 IEEE International Conference on Cluster Computing, Heraklion, Crete, Greece, 20-24 September, 2010, pp. 9-18, 2010, IEEE Computer Society, 978-1-4244-8373-0. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
HyperTransport, AMD, Opteron, interconnect, HPC, Low latency, high bandwidth |
23 | Kee Beom Kim, Seong Min Jo, Jin Woo Song, Ki-Seok Chung, Yong Ho Song |
Performance evaluation of on-chip interconnect IP using CBR traffic generator model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICHIT ![In: Proceedings of the 2009 International Conference on Hybrid Information Technology, ICHIT 2009, Daejeon, Korea, August 27-29, 2009, pp. 637-642, 2009, ACM, 978-1-60558-662-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
on-chip interconnect IP, simulation, traffic generator |
23 | Valerij Matrose, Carsten Gremzow |
Improved placement for hierarchical FPGAs exploiting local interconnect resources. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SBCCI ![In: Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, SBCCI 2009, Natal, Brazil, August 31 - September 3, 2009, 2009, ACM, 978-1-60558-705-9. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
FPGA, interconnect, placement |
23 | Krishna Saraswat |
Performance comparison of cu/low-k, carbon nanotube, and optics for on-chip and off-chip interconnects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings, pp. 111-112, 2009, ACM, 978-1-60558-576-5. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
copper, energy per bit, power, latency, bandwidth, optical interconnect, carbon nanotube |
23 | Zied Marrakchi, Hayder Mrabet, Emna Amouri, Habib Mehrez |
Efficient tree topology for FPGA interconnect network. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 18th ACM Great Lakes Symposium on VLSI 2008, Orlando, Florida, USA, May 4-6, 2008, pp. 321-326, 2008, ACM, 978-1-59593-999-9. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
fpga, routing, interconnect, hierarchy, rent's rule |
23 | Simon W. Moore, Daniel Greenfield |
The next resource war: computation vs. communication. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 81-86, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
fractal structure, temporal interconnect, tera-scale, networks-on-chip, CMP, communication complexity, Rent's rule |
23 | Katherine Shu-Min Li, Chung-Len Lee 0001, Chauchin Su, Jwu E. Chen |
IEEE Standard 1500 Compatible Oscillation Ring Test Methodology for Interconnect Delay and Crosstalk Detection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 23(4), pp. 341-355, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
oscillation ring (OR) test scheme, open faults, crosstalk glitches, IEEE P1500, wrapper cell design, stuck-at faults, delay faults, SOC testing, interconnect test |
23 | Haikun Zhu, Rui Shi 0003, Chung-Kuan Cheng, Hongyu Chen |
Approaching Speed-of-light Distortionless Communication for On-chip Interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 684-689, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
0.10 micron, speed-of-light distortionless communication, surfliner on-chip distortionless transmission line scheme, shunt resistors, shunt conductance, single-ended microstrip line, 10 Gbit/s, on-chip interconnect |
23 | Haikun Zhu, Yi Zhu 0002, Chung-Kuan Cheng, David M. Harris |
An Interconnect-Centric Approach to Cyclic Shifter Design Using Fanout Splitting and Cell Order Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 12th Conference on Asia South Pacific Design Automation, ASP-DAC 2007, Yokohama, Japan, January 23-26, 2007, pp. 616-621, 2007, IEEE Computer Society, 1-4244-0629-3. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
64 bit, interconnect-centric approach, fanout splitting, cell order optimization, logarithmic cyclic shifter design, demultiplexers, shifting path, nonshifting paths, accumulated wire load, switching probabilities, integer linear programming |
23 | Iris Hui-Ru Jiang, Song-Ra Pan, Yao-Wen Chang, Jing-Yang Jou |
Reliable crosstalk-driven interconnect optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 11(1), pp. 88-103, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
post-layout optimization, VLSI, interconnect, lagrangian relaxation |
23 | Cristian Grecu, Partha Pratim Pande, André Ivanov, Res Saleh |
BIST for Network-on-Chip Interconnect Infrastructures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 24th IEEE VLSI Test Symposium (VTS 2006), 30 April - 4 May 2006, Berkeley, California, USA, pp. 30-35, 2006, IEEE Computer Society, 0-7695-2514-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
interconnect infrastructure, unicast test, multicast test, built-in self-test, network-on-chip |
23 | Manuel Saldaña, Lesley Shannon, Paul Chow |
The routability of multiprocessor network topologies in FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Eigth International Workshop on System-Level Interconnect Prediction (SLIP 2006), Munich, Germany, March 4-5, 2006, Proceedings, pp. 49-56, 2006, ACM, 1-59593-255-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
FPGA, multiprocessor, network-on-chip, topology, interconnect |
23 | Baosheng Wang, Andy Kuo, Touraj Farahmand, André Ivanov, Yong B. Cho, Sassan Tabatabaei |
A Realistic Timing Test Model and Its Applications in High-Speed Interconnect Devices. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. Electron. Test. ![In: J. Electron. Test. 21(6), pp. 621-630, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
timing specifications testing, test environment, tester OTA and yield, high-speed interconnect testing, yield analysis |
23 | André DeHon |
Design of programmable interconnect for sublithographic programmable logic arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, FPGA 2005, Monterey, California, USA, February 20-22, 2005, pp. 127-137, 2005, ACM, 1-59593-029-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
Manhattan mesh, sublithographic architecture, programmable logic arrays, nanowires, programmable interconnect |
23 | Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell |
Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VTS ![In: 23rd IEEE VLSI Test Symposium (VTS 2005), 1-5 May 2005, Palm Springs, CA, USA, pp. 389-394, 2005, IEEE Computer Society, 0-7695-2314-5. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
FPAA testing, Mixed-signal test, interconnect testing, oscillation-based test |
23 | Quming Zhou, Kartik Mohanram, Athanasios C. Antoulas |
Structure preserving reduction of frequency-dependent interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 42nd Design Automation Conference, DAC 2005, San Diego, CA, USA, June 13-17, 2005, pp. 939-942, 2005, ACM, 1-59593-058-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
interconnect, model-order reduction, skin effect |
23 | Lakshmi Kalpana Vakati, Janet Meiling Wang |
A new multi-ramp driver model with RLC interconnect load. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2004 International Symposium on Physical Design, ISPD 2004, Phoenix, Arizona, USA, April 18-21, 2004, pp. 170-175, 2004, ACM, 1-58113-817-2. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
inductance criteria, multi-ramp driver model, transmission line effects, interconnect modeling, effective capacitance |
23 | Raphael Rubin, André DeHon |
Design of FPGA interconnect for multilevel metalization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2003, Monterey, CA, USA, February 23-25, 2003, pp. 154-163, 2003, ACM, 1-58113-651-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
multi-level metalization, FPGA, interconnect, hierarchical, mesh-of-trees |
23 | Baosheng Wang, Yong B. Cho, Sassan Tabatabaei, André Ivanov |
Yield, Overall Test Environment Timing Accuracy, and Defect Level Trade-Offs for High-Speed Interconnect Device Testing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, pp. 348-353, 2003, IEEE Computer Society, 0-7695-1951-2. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
Timing specifications testing, Test Environment, Tester OTA and yield, High-speed interconnect testing, Yield analysis |
23 | John Mayega, Okan Erdogan, Paul M. Belemjian, Kuan Zhou, John F. McDonald 0001, Russell P. Kraft |
3D direct vertical interconnect microprocessors test vehicle. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 141-146, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
SiGe HBT, direct vertical integration, finite state machine, interconnect, microprocessor, adder, register file, 3D integration, current mode logic |
23 | Magdy A. El-Moursy, Eby G. Friedman |
Optimum wire sizing of RLC interconnect with repeaters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 13th ACM Great Lakes Symposium on VLSI 2003, Washington, DC, USA, April 28-29, 2003, pp. 27-32, 2003, ACM, 1-58113-677-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
power delay product, transient power dissipation, propagation delay, repeater insertion, wire sizing, RLC interconnect |
23 | Partha Pratim Pande, Cristian Grecu, André Ivanov |
High-Throughput Switch-Based Interconnect for Future SoCs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IWSOC ![In: Proceedings of the 3rd IEEE International Workshop on System-on-Chip for Real-Time Applications (IWSOC'03), 30 June - 2 July 2003, Calgary, Alberta, Canada, pp. 304-310, 2003, IEEE Computer Society, 0-7695-1944-X. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
SoC, Wormhole Routing, Virtual Channels, Interconnect Architecture |
23 | Michael D. Hutton, Vinson Chan, Peter Kazarian, Victor Maruri, Tony Ngai, Jim Park, Rakesh H. Patel, Bruce Pedersen, Jay Schleicher, Sergey Y. Shumarayev |
Interconnect enhancements for a high-speed PLD architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, FPGA 2002, Monterey, CA, USA, February 24-26, 2002, pp. 3-10, 2002, ACM, 1-58113-452-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
FPGA, architecture, interconnect, programmable logic |
23 | Stephen E. Krufka, Phillip Christie |
Terminal optimization analysis for functional block re-use. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Fourth IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2002), April 6-7, 2002, San Diego, California, USA, Proceedings, pp. 3-8, 2002, ACM. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
optimization, SoC, interconnect, Rent's rule |
23 | Bin Liu, Fabrizio Lombardi, Wei-Kang Huang |
Testing programmable interconnect systems: an algorithmic approach. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Asian Test Symposium ![In: 9th Asian Test Symposium (ATS 2000), 4-6 December 2000, Taipei, Taiwan, pp. 311-316, 2000, IEEE Computer Society, 0-7695-0887-1. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
programmable circuits, interconnected systems, programmable interconnect systems testing, algorithmic approach, programmable wiring networks, comprehensive fault model, network faults, open faults, switch faults, stuck-off faults, programming faults, minimal configuration number, node-disjoint path-sets, network adjacencies, post-processing algorithm, fault diagnosis, graphs, interconnections, fault detection, fault coverage, circuit analysis computing, stuck-at faults, switching, bridge faults, automatic test software, circuit testing, figure of merit, programming phases, stuck-on faults, short circuits |
23 | Krishna Saraswat, Shukri J. Souri, Kaustav Banerjee, Pawan Kapur |
Performance analysis and technology of 3-D ICs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 85-90, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
VLSI, interconnect, circuits, ICs, 3-D |
23 | Dirk Stroobandt, Herwig Van Marck |
Efficient representation of interconnection length distributions using generating polynomials. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Second IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2000), April 8-9, 2000, San Diego, California, USA, Proceedings, pp. 99-105, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
interconnect length distributions, enumeration, VLSI CAD, generating polynomials |
23 | W. J. Bainbridge, Stephen B. Furber |
Asynchronous Macrocell Interconnect using MARBLE. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASYNC ![In: 4th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC '98), 30 March - 2 April 1998, San Diego, CA, USA, pp. 122-132, 1998, IEEE Computer Society, 0-8186-8392-9. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
Macrocell Bus, VLSI, Interconnect, Asynchronous |
23 | Takumi Okamoto, Jason Cong |
Buffered Steiner tree construction with wire sizing for interconnect layout optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1996 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1996, San Jose, CA, USA, November 10-14, 1996, pp. 44-49, 1996, IEEE Computer Society / ACM, 0-8186-7597-7. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
Steiner Tree, Buffer Insertion, Interconnect Optimization, Wire Sizing |
23 | Prasasth Palnati, Mario Gerla, Emilio Leonardi |
Deadlock-free routing in an optical interconnect for high-speed wormhole routing networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICPADS ![In: 1996 International Conference on Parallel and Distributed Systems (ICPADS '96), June 3-6, 1996, Tokyo, Japan, Proceedings, pp. 256-264, 1996, IEEE Computer Society, 0-8186-7267-6. The full citation details ...](Pics/full.jpeg) |
1996 |
DBLP DOI BibTeX RDF |
high-speed wormhole routing networks, Supercomputer SuperNet, two-level hierarchical high-speed network, electronic mesh fabric, WDM optical backbone network, metropolitan area, campus area, backpressure hop-by-hop flow control mechanism, shufflenet multihop virtual topology, physical channels, up/down deadlock free routing scheme, bidirectional shufflenet, optical backbone, multiprocessor interconnection networks, network routing, virtual channels, wavelength division multiplexing, optical interconnections, optical interconnect, deadlock-free routing, deadlock prevention |
23 | Jimmy Shinn-Hwa Wang, Wayne Wei-Ming Dai |
Transformation of min-max optimization to least-square estimation and application to interconnect design optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCD ![In: 1995 International Conference on Computer Design (ICCD '95), VLSI in Computers and Processors, October 2-4, 1995, Austin, TX, USA, Proceedings, pp. 664-670, 1995, IEEE Computer Society, 0-8186-7165-3. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
min-max optimization transformation, interconnect design optimization, tighter bound, circuit layout CAD, minimisation, least squares approximations, multichip modules, multichip modules, least-square estimation, minimax techniques |
23 | Tülin Erdim Mangir, Algirdas Avizienis |
Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 31(7), pp. 609-616, 1982. The full citation details ...](Pics/full.jpeg) |
1982 |
DBLP DOI BibTeX RDF |
VLSI fault tolerance, Interconnect area estimates, redundancy partitioning, redundancy placement, regular designs, VLSI yield improvement |
23 | Chris C. N. Chu, D. F. Wong 0001 |
A new approach to simultaneous buffer insertion and wire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1997, San Jose, CA, USA, November 9-13, 1997, pp. 614-621, 1997, IEEE Computer Society / ACM, 0-8186-8200-0. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
interconnect delay minimization, interconnect area minimization, convex quadratic programming, buffer insertion, wire sizing |
22 | Usman Ahmed, Guy G. Lemieux, Steven J. E. Wilton |
The impact of interconnect architecture on via-programmed structured ASICs (VPSAs). ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 18th International Symposium on Field Programmable Gate Arrays, FPGA 2010, Monterey, California, USA, February 21-23, 2010, pp. 263-272, 2010, ACM, 978-1-60558-911-4. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
structured asics, via programmable fabric |
22 | Zhuo Li 0001, David A. Papa, Charles J. Alpert, Shiyan Hu, Weiping Shi, Cliff C. N. Sze, Nancy Ying Zhou |
Ultra-fast interconnect driven cell cloning for minimizing critical path delay. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010, pp. 75-82, 2010, ACM, 978-1-60558-920-6. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
gate duplication, physical synthesis, timing-driven placement |
22 | Bruce Mathewson |
The evolution of SOC interconnect and how NOC fits within it. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 47th Design Automation Conference, DAC 2010, Anaheim, California, USA, July 13-18, 2010, pp. 312-313, 2010, ACM, 978-1-4503-0002-5. The full citation details ...](Pics/full.jpeg) |
2010 |
DBLP DOI BibTeX RDF |
AMBA AXI, network on chip |
22 | Houman Zarrabi, Asim J. Al-Khalili, Yvon Savaria |
An interconnect-aware delay model for dynamic voltage scaling in NM technologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Great Lakes Symposium on VLSI ![In: Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, Boston Area, MA, USA, May 10-12 2009, pp. 45-50, 2009, ACM, 978-1-60558-522-2. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
dynamic voltage scaling (dvs), interconnects, delay model |
22 | Tung-Chieh Chen, Yao-Wen Chang, Shyh-Chang Lin |
A New Multilevel Framework for Large-Scale Interconnect-Driven Floorplanning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(2), pp. 286-294, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Daniel Arumí, Rosa Rodríguez-Montañés, Joan Figueras |
Experimental Characterization of CMOS Interconnect Open Defects. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1), pp. 123-136, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
22 | Tzvetan S. Metodi, Darshan D. Thaker, Andrew W. Cross, Isaac L. Chuang, Frederic T. Chong |
High-level interconnect model for the quantum logic array architecture. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM J. Emerg. Technol. Comput. Syst. ![In: ACM J. Emerg. Technol. Comput. Syst. 4(1), pp. 1:1-1:28, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
QLA, Quantum computer architecture design, teleportation, fault tolerance, large scale, quantum |
22 | Yu Hu 0002, Yan Lin 0001, Lei He 0001, Tim Tuan |
Physical synthesis for FPGA interconnect power reduction by dual-Vdd budgeting and retiming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ACM Trans. Design Autom. Electr. Syst. ![In: ACM Trans. Design Autom. Electr. Syst. 13(2), pp. 30:1-30:29, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
FPGA, Low power, retiming |
22 | Md. Sajjad Rahaman, Masud H. Chowdhury |
BER performance comparison between CDMA and UWB for RF/wireless interconnect application. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EIT ![In: 2008 IEEE International Conference on Electro/Information Technology, EIT 2008, held at Iowa State University, Ames, Iowa, USA, May 18-20, 2008, pp. 494-497, 2008, IEEE, 978-1-4244-2030-8. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
Displaying result #401 - #500 of 5812 (100 per page; Change: ) Pages: [ <<][ 1][ 2][ 3][ 4][ 5][ 6][ 7][ 8][ 9][ 10][ 11][ 12][ 13][ 14][ >>] |
|