Search results for "processor"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
20	Hans Domjan, Thomas R. Gross	Extending a Best-Effort Operating System to Provide QoS Processor Management.	IWQoS	2001	DBLP DOI BibTeX RDF
20	Sungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi	Fast Hardware-Software Coverification by Optimistic Execution of Real Processor.	DATE	2000	DBLP DOI BibTeX RDF
20	Roberto Maro, Yu Bai 0001, R. Iris Bahar	Dynamically Reconfiguring Processor Resources to Reduce Power Consumption in High-Performance Processors.	PACS	2000	DBLP DOI BibTeX RDF	low-power, high-performance, architecture-level
20	Kentaro Shimada, Tatsuya Kawashimo, Makoto Hanawa, Ryo Yamagata, Eiki Kamada	A Superscalar RISC Processor with 160 FPRs for Large Scale Scientific Processing.	ICCD	1999	DBLP DOI BibTeX RDF	scientific processing, slide-windowed registers, large number of FPRs, SR8000, supercomputer, software prefetch
20	Md. Altaf-Ul-Amin, Zahari Mohamed Darus	VHDL Design of a Test Processor Based on Mixed-Mode Test Generation.	Great Lakes Symposium on VLSI	1999	DBLP DOI BibTeX RDF
20	Vishnu A. Patankar, Alok Jain, Randal E. Bryant	Formal Verification of an ARM Processor.	VLSI Design	1999	DBLP DOI BibTeX RDF
20	Shen-Fu Hsiao, Jen-Yin Chen	Design, Implementation and Analysis of a New Redundant CORDIC Processor with Constant Scaling Factor and Regular Structure.	J. VLSI Signal Process.	1998	DBLP DOI BibTeX RDF
20	Hiroshi Tomiyasu, Shigeru Kusakabe, Tetsuo Kawano, Makoto Amamiya	Co-processor System Design for Fine-Grain Message Handling in KUMP/D.	Euro-Par	1997	DBLP DOI BibTeX RDF
20	Gaurav Aggarwal, Nitin Thaper, Kamal Aggarwal, M. Balakrishnan, Shashi Kumar	A Novel Reconfigurable Co-Processor Architecture.	VLSI Design	1997	DBLP DOI BibTeX RDF
20	Debashis Basak, Dhabaleswar K. Panda 0001, Mohammad Banikazemi	Benefits of Processor Clustering in Designing Large Parallel Systems: When and How?	IPPS	1996	DBLP DOI BibTeX RDF
20	Pedro Furtado 0001, Henrique Madeira	Fault Injection Evaluation of Assigned Signatures in a RISC Processor.	EDCC	1996	DBLP DOI BibTeX RDF
20	Raj Vaswani, John Zahorjan	The Implications of Cache Affinity on Processor Scheduling for Multiprogrammed, Shared Memory Multiprocessors.	SOSP	1991	DBLP DOI BibTeX RDF
20	Earl E. Swartzlander Jr.	Generic signal processor implementation with VHSIC.	J. VLSI Signal Process.	1990	DBLP DOI BibTeX RDF
20	L. Lim, A. Park	Solving the processor identity problem in O(n) space.	SPDP	1990	DBLP DOI BibTeX RDF
20	Mitsuo Ishii, Hiroyuki Sato, Morio Ikesaka, Kouichi Murakami, Hiroaki Ishihata	Cellular array processor CAP and applications.	J. VLSI Signal Process.	1989	DBLP DOI BibTeX RDF
20	Kemal Oflazer	A reconfigurable VLSI architecture for a database processor.	AFIPS National Computer Conference	1983	DBLP DOI BibTeX RDF
20	Giovanni Mariani, Aleksandar Brankovic, Gianluca Palermo, Jovana Jovic, Vittorio Zaccaria, Cristina Silvano	A correlation-based design space exploration methodology for multi-processor systems-on-chip.	DAC	2010	DBLP DOI BibTeX RDF	design space exploration, kriging, response surface, multi-processor systems-on-chip
20	Satoshi Amamiya, Makoto Amamiya, Ryuzo Hasegawa, Hiroshi Fujita 0002	A continuation-based noninterruptible multithreading processor architecture.	J. Supercomput.	2009	DBLP DOI BibTeX RDF	Parallel processing, Multithreading, Processor architecture, Thread level parallelism, Multithreaded programming
20	Yi Pang, WeiDong Hu, Lifeng Sun, Shiqiang Yang	Adaptive data-driven parallelization of multi-view video coding on multi-core processor.	Sci. China Ser. F Inf. Sci.	2009	DBLP DOI BibTeX RDF	adaptive data-driven, Cell Broadband Engine™ Processor, parallelization, multi-view video coding
20	Joo-Young Kim 0001, Seungjin Lee 0001, Jinwook Oh, Minsu Kim, Hoi-Jun Yoo	A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management.	ISLPED	2009	DBLP DOI BibTeX RDF	energy efficient object recognition, multimedia processor, workload-aware dynamic power management
20	Shailender Chaudhry, Robert Cypher, Magnus Ekman, Martin Karlsson, Anders Landin, Sherman Yip, Håkan Zeffer, Marc Tremblay	Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor.	ISCA	2009	DBLP DOI BibTeX RDF	checkpoint-based architecture, hardware speculation, sst, chip multiprocessor, cmp, instruction-level parallelism, processor architecture, memory-level parallelism
20	Jorgen Peddersen, Sri Parameswaran	Low-Impact Processor for Dynamic Runtime Power Management.	IEEE Des. Test Comput.	2008	DBLP DOI BibTeX RDF	low-impact processor, runtime power management, power estimation, energy aware, macromodeling, counters
20	Jongeun Lee, Aviral Shrivastava	Static analysis of processor stall cycle aggregation.	CODES+ISSS	2008	DBLP DOI BibTeX RDF	memory bound loops, processor free time, stall cycle aggregation, embedded systems, low power, code transformation
20	Tanya René Beelders, Pieter J. Blignaut, Theo McDonald, Engela Dednam	Novice Word Processor User Performance with Pictorial and Text Icons.	APCHI	2008	DBLP DOI BibTeX RDF	Word processor, Usability, Text, Icons
20	Valeri Kirischian, Vadim Geurkov, Lev Kirischian	A multi-mode video-stream processor with cyclically reconfigurable architecture.	Conf. Computing Frontiers	2008	DBLP DOI BibTeX RDF	cost-performance ratio, video-stream processor, FPGA, computer architecture, reconfigurable computing, dynamic reconfiguration, pre-fetching, temporal partitioning
20	Darshika G. Perera, Kin Fun Li	Parallel Computation of Similarity Measures Using an FPGA-Based Processor Array.	AINA	2008	DBLP DOI BibTeX RDF	data mining, similarity measures, processor array
20	Hans G. Kerkhoff, Jarkko J. M. Huijts	Testing of a Highly Reconfigurable Processor Core for Dependable Data Streaming Applications.	DELTA	2008	DBLP DOI BibTeX RDF	reconfigurable multi-processor-cores SoC, embedded system test, dependable SoCs, ATPG, Design-for-Test, self-repair
20	Andy Lambrechts, Praveen Raghavan, Murali Jayapala, Francky Catthoor, Diederik Verkest	Energy-Aware Interconnect Optimization for a Coarse Grained Reconfigurable Processor.	VLSI Design	2008	DBLP DOI BibTeX RDF	Interconnect-Aware Design, Low Power, Processor Architecture, Energy-Aware Design
20	Wenjing Rao, Alex Orailoglu, Ramesh Karri	Towards Nanoelectronics Processor Architectures.	J. Electron. Test.	2007	DBLP DOI BibTeX RDF	fault tolerance, reliability, computational model, processor architecture, nanoelectronics, time redundancy, hardware redundancy
20	Medha Shukla Sarkar, Abisoye Mudasiru, Nilanjan Sarkar	Design and implementation of a command processor for high level human-robot interaction system.	ACM Southeast Regional Conference	2007	DBLP DOI BibTeX RDF	TXL, command processor, transformation languages
20	Flavius Gruian, Mark Westmijze	BlueJEP: a flexible and high-performance Java embedded processor.	JTRES	2007	DBLP DOI BibTeX RDF	embedded systems, Java processor, Bluespec
20	Roger Moussali, Nabil Ghanem, Mazen A. R. Saghir	Supporting multithreading in configurable soft processor cores.	CASES	2007	DBLP DOI BibTeX RDF	soft processor cores, multithreading
20	Ying Zhang 0032, Gen Li 0002, Xuejun Yang, Kun Zeng	Optimizing Stream Organization to Improve the Performance of Scientific Computing Applications on the Stream Processor.	ICA3PP	2007	DBLP DOI BibTeX RDF	stream reusing, stream transpose, inter-cluster communication, cluster, parallel computing, Scientific computing, SIMD, stream processor, stream programming model
20	An'an Luo, Chuang Lin 0002, Zhen Chen 0001, Xuehai Peng, Peter D. Ungsunan	TNC-compatible NAC System implemented on Network Processor.	LCN	2007	DBLP DOI BibTeX RDF	TNC, AES algorithm, network processor, network access control
20	Eitan Altman, Konstantin Avrachenkov, Urtzi Ayesta	A survey on discriminatory processor sharing.	Queueing Syst. Theory Appl.	2006	DBLP DOI BibTeX RDF	Discriminatory Processor Sharing, Conservation Law, Asymptotic Analysis, M/G/1
20	Robert C. Hampshire, Mor Harchol-Balter, William A. Massey	Fluid and diffusion limits for transient sojourn times of processor sharing queues with time varying rates.	Queueing Syst. Theory Appl.	2006	DBLP DOI BibTeX RDF	Diffusion limits, Time-varying queues, Uniform acceleration, Virtual customers, Processor sharing, Sojourn times, Transient behavior, Fluid limits
20	Dharani Sankar Vijayakumar, S. Vijay Ram	A network processor implementation for solving the ACK implosion problem.	ACM Southeast Regional Conference	2006	DBLP DOI BibTeX RDF	ACK implosion, Acknowledgement (ACK), Intel IXP 2400, Network Processor (NP), multicast clients, multicast server
20	H. Christian Gromoll, Philippe Robert, Bert Zwart, Richard Bakker	The impact of reneging in processor sharing queues.	SIGMETRICS/Performance	2006	DBLP DOI BibTeX RDF	measure valued process, queues in overload, queues with impatience, admission control, user behavior, processor sharing, fluid limits, delay-differential equation
20	Robert Ronan, Colm O'hEigeartaigh, Colin C. Murphy, Michael Scott, Tim Kerins, William P. Marnane	An Embedded Processor for a Pairing-Based Cryptosystem.	ITNG	2006	DBLP DOI BibTeX RDF	ç pairing, genus 2 hyperelliptic, characteristic 2, pairing-based cryptosystem, dedicated processor
20	Mei Wen, Nan Wu 0003, Changqing Xun, Wei Wu, Chunyuan Zhang	Optimization and Evaluating of StreamYGX2 on MASA Stream Processor.	Asia-Pacific Computer Systems Architecture Conference	2006	DBLP DOI BibTeX RDF	Ygx2, 2D Lagrange-Euler Method, scientific computing, stream processor
20	Zhichun Zhu, Xiaodong Zhang 0001	Look-Ahead Architecture Adaptation to Reduce Processor Power Consumption.	IEEE Micro	2005	DBLP DOI BibTeX RDF	Low-power design, Processor Architectures
20	Mancia Anguita, J. Manuel Martinez-Lechado	MP3 Optimization Exploiting Processor Architecture and using Better Algorithms.	IEEE Micro	2005	DBLP DOI BibTeX RDF	D.3.4.g Optimization, C.1 Processor Architectures, C.1.2.j SIMD processors, E.4.a Data compaction and compression, J.9.c Multimedia applications and multimedia signal processing
20	Yung-Chi Chang, Chao-Chih Huang, Wei-Min Chao, Liang-Gee Chen	An Efficient Embedded Bitstream Parsing Processor for MPEG-4 Video Decoding System.	J. VLSI Signal Process.	2005	DBLP DOI BibTeX RDF	bitstream parsing processor, data partitioned bitstream parsing, MPEG-4, video decoding
20	Jih-Fu Tu	Cache Management for Discrete Processor Architectures.	ISPA	2005	DBLP DOI BibTeX RDF	Discrete processor architectures, write-invalidate (WI) and cache block, multithreading, cache coherency, shared cache, memory latency
20	Liang Yang, Tushar Gohad, Pavel Ghosh, Devesh Sinha, Arunabha Sen, Andréa W. Richa	Resource mapping and scheduling for heterogeneous network processor systems.	ANCS	2005	DBLP DOI BibTeX RDF	HW-SW partitioning, network processor, codesign, randomized rounding
20	Rong-Tai Liu, Nen-Fu Huang, Chih-Hao Chen, Chia-Nan Kao	A fast string-matching algorithm for network processor-based intrusion detection system.	ACM Trans. Embed. Comput. Syst.	2004	DBLP DOI BibTeX RDF	network, Intrusion detection, pattern matching, processor
20	Richard B. Kujoth, Chi-Wei Wang, Derek B. Gottlieb, Jeffrey J. Cook, Nicholas P. Carter	A reconfigurable unit for a clustered programmable-reconfigurable processor.	FPGA	2004	DBLP DOI BibTeX RDF	FPGA, technology scaling, reconfigurable processor
20	Pierre G. Paulin, Chuck Pilkington, Michel Langevin, Essaid Bensoudane, Gabriela Nicolescu	Parallel programming models for a multi-processor SoC platform applied to high-speed traffic management.	CODES+ISSS	2004	DBLP DOI BibTeX RDF	system-on-chip, embedded software, multi-processor systems
20	Hideaki Yanagisawa, Minoru Uehara, Hideki Mori	Development Methodology of ASIP Based on Java Byte Code Using HW/SW Co-Design System for Processor Design.	ICDCS Workshops	2004	DBLP DOI BibTeX RDF	HW/SW Codesign system, C-DASH, ASIP, Java processor, ISA
20	Marcus Bednara, Jürgen Teich	Automatic Synthesis of FPGA Processor Arrays from Loop Algorithms.	J. Supercomput.	2003	DBLP DOI BibTeX RDF	regular processor arrays, FPGA, design automation, space-time mapping
20	Moonsoo Kang, Chansu Yu, Hee Yong Youn, Ben Lee, Myungchul Kim 0001	Isomorphic Strategy for Processor Allocation in k-Ary n-Cube Systems.	IEEE Trans. Computers	2003	DBLP DOI BibTeX RDF	performance evaluation, partitioning, job scheduling, processor allocation, k-ary n-cube
20	Karl-Heinz Zimmermann	A Special Purpose Array Processor Architecture for the Molecular Dynamics Simulation of Point-Mutated Proteins.	J. VLSI Signal Process.	2003	DBLP DOI BibTeX RDF	point mutation, penicillin amidase, parallel processing, molecular dynamics, protein, array processor
20	Dino Oliva, Rainer Buchty, Nevin Heintze	AES and the cryptonite crypto processor.	CASES	2003	DBLP DOI BibTeX RDF	round key generation, architecture, cryptography, AES, processor, high-speed, software implementation, high-bandwidth
20	Jason Stinson, Stefan Rusu	A 1.5GHz third generation itanium® 2 processor.	DAC	2003	DBLP DOI BibTeX RDF	on-die cache, reliability, test, design methodology, processor
20	Li Chen, Xiaoliang Bai, Sujit Dey	Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores.	J. Electron. Test.	2002	DBLP DOI BibTeX RDF	interconnect, crosstalk, processor, self-test
20	Andreas Svolos, Charalampos Konstantopoulos, Christos Kaklamanis	A Parallel Solution in Texture Analysis Employing a Massively Parallel Processor (Research Note).	Euro-Par	2002	DBLP DOI BibTeX RDF	hypercube, texture analysis, co-occurrence matrix, massively parallel processor
20	Juha-Pekka Soininen, Jari Kreku, Yang Qu, Martti Forsell	Fast processor core selection for WLAN modem using mappability estimation.	CODES	2002	DBLP DOI BibTeX RDF	mappability estimation, processor architecture evaluation, codesign, cost function
20	Jack Liu, Fred C. Chow	A near-optimal instruction scheduler for a tightly constrained, variable instruction set embedded processor.	CASES	2002	DBLP DOI BibTeX RDF	configurable code generation, variable instruction set, embedded processor, instruction scheduling, dictionary, enumeration, program representation, resource modeling
20	Rong Lin	Trading Bitwidth For Array Size: A Unified Reconfigurable Arithmetic Processor Design.	ISQED	2001	DBLP DOI BibTeX RDF	IP design, inner product processor, matrix multiplier, run-time reconfigurable architecture, SOC, array multiplier, polynomial evaluation
20	Tadayoshi Horita, Itsuo Takanami	Fault-Tolerant Processor Arrays Based on the 1½-Track Switches with Flexible Spare Distributions.	IEEE Trans. Computers	2000	DBLP DOI BibTeX RDF	The 1$frac{1}{2}$-track switch model, reconfiguration, yield enhancement, wafer scale integration, mesh-connected processor arrays
20	Sivarama P. Dandamudi, Samir Ayachi	Performance of Hierarchical Processor Scheduling in Shared-Memory Multiprocessor Systems.	IEEE Trans. Computers	1999	DBLP DOI BibTeX RDF	performance evaluation, multiprocessor systems, processor scheduling, time-sharing, Hierarchical scheduling, space-sharing
20	Peter M. Kuhn	Fast MPEG-4 Motion Estimation: Processor Based and Flexible VLSI Implementations.	J. VLSI Signal Process.	1999	DBLP DOI BibTeX RDF	algorithm, VLSI, motion estimation, MPEG-4, processor, complexity analysis
20	Takeiki Aizono, Katsumi Kawano, Masahiro Ohashi, Makoto Kogure	An Object Model of Autonomous Control Processor and the Message Selection Method.	ISADS	1999	DBLP DOI BibTeX RDF	ADS (Autonomous Decentralized System), ACP (Autonomous Control Processor), fault-tolerance, scalability, maintainability
20	Gerassimos D. Barlas	Collection-Aware Optimum Sequencing of Operations and Closed-Form Solutions for the Distribution of a Divisible Load on Arbitrary Processor Trees.	IEEE Trans. Parallel Distributed Syst.	1998	DBLP DOI BibTeX RDF	Optimum load distribution, optimum distribution and collection sequencing, data-parallel applications, arbitrary processor trees, collection-aware load distribution
20	Alan S. Wagner, Halsur V. Sreekantaswamy, Samuel T. Chanson	Performance Models for the Processor Farm Paradigm.	IEEE Trans. Parallel Distributed Syst.	1997	DBLP DOI BibTeX RDF	processor farm, master-slave, performance evaluation, network flow, tree networks, Parallel programming paradigms, message passing architecture
20	Byung S. Yoo, Chita R. Das	Good Processor Management = Fast Allocation + Efficient Scheduling.	ICPP	1997	DBLP DOI BibTeX RDF	Group scheduling policy, processor management, stack-based allocation algorithm, operating systems, mesh-connected multicomputers
20	B. Madhu Rao, Sub Ramakrishnan	Queueing Models for a Single Server LAN with Processor Sharing Disciplines.	Computing	1996	DBLP DOI BibTeX RDF	queueing local area networks, Markov chains, processor sharing, file server
20	Dirk Fimmel, Renate Merker	Propagation of I/O-Variables in Massively Parallel Processor Arrays.	PDP	1996	DBLP DOI BibTeX RDF	parallel processor arrays, systems of recurrence equations, automatic design methods, massive parallelism
20	Vijay S. Iyengar, Louise Trevillyan, Pradip Bose	Representative Traces for Processor Models with Infinite Cache.	HPCA	1996	DBLP DOI BibTeX RDF	dynamic traces, performance evaluation, timer, processor design
20	David Feldcamp, Alan Wagner	Using the Parsec environment to implement a high-performance processor farm.	HICSS (2)	1995	DBLP DOI BibTeX RDF	Parsec, high-performance processor farm, multicomputer programs, context-sensitive configuration, hand-optimized implementations, declarative structural information, parallel application structure specification, performance evaluation, performance, user interfaces, user interface, scalability, parallel programming, parallel architectures, static analysis, message passing, reuse, abstraction, optimisation, programming environments, software reusability, parallel programming environment, communication primitives
20	Heung-Nam Kim, Mary Jane Irwin, Robert Michael Owens	Motion Estimation Algorithms on Fine Grain Array Processor.	ASAP	1995	DBLP DOI BibTeX RDF	motion estimation, video compression, array processor, block matching, massively parallel processing
20	Giuseppe Ascia, Vincenzo Catania	Design of a VLSI parallel processor for fuzzy computing.	VLSI Design	1995	DBLP DOI BibTeX RDF	VLSI parallel processor, fuzzy computing, /spl alpha/-level sets theory, memory resources, processing units, 50 MHz, scalability, VLSI, parallelism, fuzzy logic, parallel architectures, inference mechanisms, fuzzy set theory, integrated circuit design, microprocessor chips, membership functions, fuzzy inferences, clock frequency, 8 bit
20	Ali Skaf, Alain Guyot	SAGA: the first general-purpose on-line arithmetic co-processor.	VLSI Design	1995	DBLP DOI BibTeX RDF	general-purpose co-processor, online arithmetic coprocessor, VLSI realisation, BKM algorithm, complex logarithm function, complex exponential function, VLSI, arithmetic, coprocessors, CMOS digital integrated circuits, redundant number systems, CMOS IC, SAGA
20	Egon Börger, Giuseppe Del Castillo	A formal method for provably correct composition of a real-life processor out of basic components. (The APE100 Reverse Engineering Study.	ICECCS	1995	DBLP DOI BibTeX RDF	real-life processor, APE100 Reverse Engineering, modular structuring, microprocessor zCPU, APE100 massively parallel machine, provably correct composition, formal specification, formal method, reverse engineering, parallel architectures
20	Kiran M. Rege, Bhaskar Sengupta	A decomposition theorem and related results for the discriminatory processor sharing queue.	Queueing Syst. Theory Appl.	1994	DBLP DOI BibTeX RDF	delay, Queueing, processor sharing, sojourn time
20	Louise E. Moser, P. M. Melliar-Smith, Vivek Agrawala	Processor Membership in Asynchronous Distributed Systems.	IEEE Trans. Parallel Distributed Syst.	1994	DBLP DOI BibTeX RDF	asynchronous distributedsystems, processor membership, broadcast messages, membership protocol, totalorder, fault tolerance, distributed systems, protocols, fault tolerant computing, distributed processing, reconfiguration, asynchrony, broadcast communication
20	Massimo Maresca	Polymorphic Processor Arrays.	IEEE Trans. Parallel Distributed Syst.	1993	DBLP DOI BibTeX RDF	polymorphic processor arrays, mesh-connected arrays, PPA, low complexity algorithms, PPA programming model, computational complexity, parallel processing, parallel computers, parallel architectures, multiprocessor interconnection networks
20	Chris J. Scheiman, Peter R. Cappello	A Processor-Time-Minimal Systolic Array for Transitive Closure.	IEEE Trans. Parallel Distributed Syst.	1992	DBLP DOI BibTeX RDF	processor-time-minimal multiprocessor schedules, 2-D mesh, parallel algorithms, systolic array, systolic arrays, directed acyclic graph, multiprocessor schedule, transitive closure
20	Sy-Yen Kuo, Kuochen Wang	Fault diagnosis in reconfigurable VLSI and WSI processor arrays.	J. VLSI Signal Process.	1990	DBLP DOI BibTeX RDF	design for diagnosability, VLSI/WSI processor array, fault diagnosis, reconfiguration, yield enhancement
20	Michael Deering, Stephanie Winner, Bic Schediwy, Chris Duffy, Neil Hunt	The triangle processor and normal vector shader: a VLSI system for high performance graphics.	SIGGRAPH	1988	DBLP DOI BibTeX RDF	graphics VLSI, hardware lighting models, real-time image display, triangle processor, interpolation, shading
20	Grant Martin	Processor Stew (review of Processor Description Languages by P. Mishra and N. Dutt, Eds.; 2008) [Book reviews].	IEEE Des. Test Comput.	2009	DBLP DOI BibTeX RDF
20	H. Peter Hofstee	Power Efficient Processor Architecture and The Cell Processor.	HPCA	2005	DBLP DOI BibTeX RDF
20	Silvia M. Müller, Christian Jacobi 0002, Hwa-Joon Oh, Kevin D. Tran, Scott R. Cottier, Brad W. Michael, Hiroo Nishikawa, Yonetaro Totsuka, Tatsuya Namatame, Naoka Yano, Takashi Machida, Sang H. Dhong	The Vector Floating-Point Unit in a Synergistic Processor Element of a CELL Processor.	IEEE Symposium on Computer Arithmetic	2005	DBLP DOI BibTeX RDF
20	Vitus J. Leung, Esther M. Arkin, Michael A. Bender, David P. Bunde, Jeanette Johnston, Alok Lal, Joseph S. B. Mitchell, Cynthia A. Phillips, Steven S. Seiden	Processor Allocation on Cplant: Achieving General Processor Locality Using One-Dimensional Allocation Strategies.	CLUSTER	2002	DBLP DOI BibTeX RDF
20	Ken-ichiro Murakami	A Pseudo Network Approach to Inter-processor Communication on a Shared-memory Multi-processor MacELIS.	Workshop on Parallel Lisp	1989	DBLP DOI BibTeX RDF
20	Thomas G. Price	A Note on the Effect or the Central Processor Service Time Distribution on Processor Utilization in Multiprogrammed Computer Systems.	J. ACM	1976	DBLP DOI BibTeX RDF
18	Cosmin E. Oancea, Alan Mycroft, Stephen M. Watt	A new approach to parallelising tracing algorithms.	ISMM	2009	DBLP DOI BibTeX RDF	memory-centric tracing algorithm, parallel
18	Huiyang Zhou	A case for fault tolerance and performance enhancement using chip multi-processors.	IEEE Comput. Archit. Lett.	2006	DBLP DOI BibTeX RDF
18	Rama Sangireddy	Reducing Rename Logic Complexity for High-Speed and Low-Power Front-End Architectures.	IEEE Trans. Computers	2006	DBLP DOI BibTeX RDF	Wide-issue processors, integer pipeline, rename logic complexity, front-end power consumption
18	Alex K. Jones, Raymond Hoare, Dara Kusic, Gayatri Mehta, Joshua Fazekas, John Foster 0001	Reducing power while increasing performance with supercisc.	ACM Trans. Embed. Comput. Syst.	2006	DBLP DOI BibTeX RDF	Low-power, synthesis, VLIW, predication, multicore architectures
18	V. Santhosh Kumar, Matthew J. Thazhuthaveetil, R. Govindarajan	Exploiting programmable network interfaces for parallel query execution in workstation clusters.	IPDPS	2006	DBLP DOI BibTeX RDF
18	Attila Egri-Nagy, Chrystopher L. Nehaniv	Evolvability of the Genotype-Phenotype Relation in Populations of Self-Replicating Digital Organisms in a Tierra-Like System.	ECAL	2003	DBLP DOI BibTeX RDF
18	Takayuki Osogami, Mor Harchol-Balter, Alan Scheller-Wolf	Analysis of cycle stealing with switching cost.	SIGMETRICS	2003	DBLP DOI BibTeX RDF	matrix analytic, distributed system, supercomputing, task assignment, load sharing, starvation, cycle stealing, unfairness, server farm
18	Ewa Z. Bem, Luke Petelczyc	MiniMIPS: a simulation project for the computer architecture laboratory.	SIGCSE	2003	DBLP DOI BibTeX RDF	simulation in lab environments, computer architecture
18	Hon Nin Cheung, Li-Minn Ang, Kamran Eshraghian	Parallel Architecture for the Implementation of the Embedded Zerotree Wavelet Algorithm.	ACAC	2000	DBLP DOI BibTeX RDF	EZW, Parallel processing, image coding
18	Alan A. Bertossi, Luigi V. Mancini, Federico Rossini	Fault-Tolerant Rate-Monotonic First-Fit Scheduling in Hard-Real-Time Systems.	IEEE Trans. Parallel Distributed Syst.	1999	DBLP DOI BibTeX RDF	Fault tolerance, multiprocessor systems, hard-real-time systems, periodic tasks, rate-monotonic scheduling, task replication
18	Santosh G. Abraham, Scott A. Mahlke	Automatic and Efficient Evaluation of Memory Hierarchies for Embedded Systems.	MICRO	1999	DBLP DOI BibTeX RDF
18	Srikat Subramaniam, Derek L. Eager	Affinity scheduling of unbalanced workloads.	SC	1994	DBLP DOI BibTeX RDF
18	Bruce Chittenden, James Hyde, Jeffrey P. Radick	A scheme for terminal I/O not requiring interrupts.	ACM Southeast Regional Conference	1982	DBLP DOI BibTeX RDF
18	Paula B. Hawthorn	The Effect of Target Applications on the Design of Database Machines.	SIGMOD Conference	1981	DBLP DOI BibTeX RDF