Hits ?▲ |
Authors |
Title |
Venue |
Year |
Link |
Author keywords |
19 | Sean X. Shi, David Z. Pan |
Wire sizing with scattering effect for nanoscale interconnection. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, Yokohama, Japan, January 24-27, 2006, pp. 503-508, 2006, IEEE, 0-7803-9451-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Srikant Nalatwad, Michael Devetsikiotis |
A Framework for Adaptive Wavelet Prediction in Self-Sizing Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Annual Simulation Symposium ![In: Proceedings 39th Annual Simulation Symposium (ANSS-39 2006), 2-6 April 2006, Huntsville, Alabama, USA, pp. 10-17, 2006, IEEE Computer Society, 0-7695-2559-8. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Tom Van Court, Martin C. Herbordt |
Sizing of Processing Arrays for FPGA-Based Computation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPL ![In: Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), Madrid, Spain, August 28-30, 2006, pp. 1-6, 2006, IEEE, 1-4244-0312-X. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli |
A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2006, Seoul, Korea, October 22-25, 2006, pp. 130-135, 2006, ACM, 1-59593-370-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
systems-on-chip, networks-on-chip, buffers, area |
19 | Eric Wong 0002, Jacob R. Minz, Sung Kyu Lim |
Decoupling capacitor planning and sizing for noise and leakage reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 395-400, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
3D floorplanning, power supply noise, decoupling capacitors, leakage power reduction |
19 | Mihir R. Choudhury, Quming Zhou, Kartik Mohanram |
Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2006 International Conference on Computer-Aided Design, ICCAD 2006, San Jose, CA, USA, November 5-9, 2006, pp. 204-209, 2006, ACM, 1-59593-389-1. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Timothy G. Constandinou, Chris Toumazou |
A micropower vision processor for parallel object positioning and sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS ![In: International Symposium on Circuits and Systems (ISCAS 2006), 21-24 May 2006, Island of Kos, Greece, 2006, IEEE, 0-7803-9389-9. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Jafar Rezaei 0001, Mansoor Davoodi |
Genetic Algorithm for Inventory Lot-Sizing with Supplier Selection Under Fuzzy Demand and Costs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEA/AIE ![In: Advances in Applied Artificial Intelligence, 19th International Conference on Industrial, Engineering and Other Applications of Applied Intelligent Systems, IEA/AIE 2006, Annecy, France, June 27-30, 2006, Proceedings, pp. 1100-1110, 2006, Springer, 3-540-35453-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
19 | Sampath Dechu, Zion Cien Shen, Chris C. N. Chu |
An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(4), pp. 600-608, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Kai Wang 0011, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska |
General skew constrained clock network sizing based on sequential linear programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 24(5), pp. 773-782, 2005. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | João Pedro Pedroso, Mikio Kubo |
Hybrid Tabu Search for Lot Sizing Problems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Hybrid Metaheuristics ![In: Hybrid Metaheuristics, Second International Workshop, HM 2005, Barcelona, Spain, August 29-30, 2005, Proceedings, pp. 66-77, 2005, Springer, 3-540-28535-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Sankalp Kallakuri, Alex Doboli, Eugene A. Feinberg |
Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 826-827, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Aseem Agarwal, Kaviraj Chopra, David T. Blaauw |
Statistical Timing Based Optimization using Gate Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2005 Design, Automation and Test in Europe Conference and Exposition (DATE 2005), 7-11 March 2005, Munich, Germany, pp. 400-405, 2005, IEEE Computer Society, 0-7695-2288-2. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Anand Ramalingam, Bin Zhang 0011, Anirudh Devgan, David Z. Pan |
Sleep transistor sizing using timing criticality and temporal currents. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2005 Conference on Asia South Pacific Design Automation, ASP-DAC 2005, Shanghai, China, January 18-21, 2005, pp. 1094-1097, 2005, ACM Press, 0-7803-8737-6. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Jerzy Duda |
Lot-Sizing in a Foundry Using Genetic Algorithm and Repair Functions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EvoCOP ![In: Evolutionary Computation in Combinatorial Optimization, 5th European Conference, EvoCOP 2005, Lausanne, Switzerland, March 30 - April 1, 2005, Proceedings, pp. 101-111, 2005, Springer, 3-540-25337-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Zhikui Wang, Xiaoyun Zhu, Sharad Singhal |
Utilization and SLO-Based Control for Dynamic Sizing of Resource Partitions. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DSOM ![In: Ambient Networks, 16th IFIP/IEEE International Workshop on Distributed Systems: Operations and Management, DSOM 2005, Barcelona, Spain, October 24-26, 2005, Proceedings, pp. 133-144, 2005, Springer, 3-540-29388-4. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Shrirang K. Karandikar, Sachin S. Sapatnekar |
Fast estimation of area-delay trade-offs in circuit sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (4) ![In: International Symposium on Circuits and Systems (ISCAS 2005), 23-26 May 2005, Kobe, Japan, pp. 3575-3578, 2005, IEEE, 0-7803-8834-8. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | José Manuel Cazeaux, Daniele Rossi 0001, Martin Omaña 0001, Cecilia Metra, Abhijit Chatterjee |
On Transistor Level Gate Sizing for Increased Robustness to Transient Faults. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IOLTS ![In: 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 6-8 July 2005, Saint Raphael, France, pp. 23-28, 2005, IEEE Computer Society, 0-7695-2406-0. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Weizhen Yan, Jianhua Zhao, Zhe Cao |
Fuzzy Programming Model for Lot Sizing Production Planning Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FSKD (1) ![In: Fuzzy Systems and Knowledge Discovery, Second International Conference, FSKD 2005, Changsha, China, August 27-29, 2005, Proceedings, Part I, pp. 285-294, 2005, Springer, 3-540-28312-9. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Vinita V. Deodhar, Jeffrey A. Davis |
Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 6th International Symposium on Quality of Electronic Design (ISQED 2005), 21-23 March 2005, San Jose, CA, USA, pp. 592-597, 2005, IEEE Computer Society, 0-7695-2301-3. The full citation details ...](Pics/full.jpeg) |
2005 |
DBLP DOI BibTeX RDF |
|
19 | Mathieu Van Vyve |
A solution approach of production planning problems based on compact formulations for single-item lot-sizing models. ![Search on Bibsonomy](Pics/bibsonomy.png) |
4OR ![In: 4OR 2(1), pp. 89-91, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Chris C. N. Chu, Evangeline F. Y. Young |
Nonrectangular shaping and sizing of soft modules for floorplan-design improvement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(1), pp. 71-79, 2004. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Ashish Srivastava, Dennis Sylvester, David T. Blaauw |
Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2004 Design, Automation and Test in Europe Conference and Exposition (DATE 2004), 16-20 February 2004, Paris, France, pp. 718-719, 2004, IEEE Computer Society, 0-7695-2085-5. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Sampath Dechu, Zion Cien Shen, Chris C. N. Chu |
An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of the 2004 Conference on Asia South Pacific Design Automation: Electronic Design and Solution Fair 2004, Yokohama, Japan, January 27-30, 2004, pp. 361-366, 2004, IEEE Computer Society, 0-7803-8175-0. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Ivanoe De Falco, Ernesto Tarantino, Antonio Della Cioppa, Francesco Gagliardi 0001 |
A Genetic Algorithm with Self-sizing Genomes for Data Clustering in Dermatological Semeiotics. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Applied Soft Computing Technologies: The Challenge of Complexity, Proceedings of the 9th Online World Conference on Soft Computing in Industrial Applications (WSC9), September 20th - October 8th, 2004, held on the World Wide Web, pp. 441-450, 2004, Springer, 978-3-540-31649-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Feng Chu 0001, Chengbin Chu, Xiao Liu |
Lot sizing models with backlog or out-sourcing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SMC (5) ![In: Proceedings of the IEEE International Conference on Systems, Man & Cybernetics: The Hague, Netherlands, 10-13 October 2004, pp. 4342-4347, 2004, IEEE, 0-7803-8566-7. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Ludmila Cherkasova, Wenting Tang |
Sizing the streaming media cluster solution for a given workload. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CCGRID ![In: 4th IEEE/ACM International Symposium on Cluster Computing and the Grid (CCGrid 2004), April 19-22, 2004, Chicago, Illinois, USA, pp. 144-151, 2004, IEEE Computer Society, 0-7803-8430-X. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Nithya N. Vijayakumar, Beth Plale |
Performance Evaluation of Rate-Based Join Window Sizing for Asynchronous Data Streams. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: 13th International Symposium on High-Performance Distributed Computing (HPDC-13 2004), 4-6 June 2004, Honolulu, Hawaii, USA, pp. 260-261, 2004, IEEE Computer Society, 0-7695-2175-4. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
|
19 | Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy 0001 |
Novel sizing algorithm for yield improvement under process variation in nanometer technology. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 454-459, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
Performance, Design, Algorithms, Reliability |
19 | Ashish Srivastava, Dennis Sylvester, David T. Blaauw |
Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 41th Design Automation Conference, DAC 2004, San Diego, CA, USA, June 7-11, 2004, pp. 783-787, 2004, ACM, 1-58113-828-8. The full citation details ...](Pics/full.jpeg) |
2004 |
DBLP DOI BibTeX RDF |
optimization, power dissipation, multiple voltages |
19 | Sheldon X.-D. Tan, C.-J. Richard Shi |
Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(3), pp. 277-284, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | David M. Binkley, C. E. Hopper, Steve D. Tucker, Brian C. Moss, James M. Rochelle, Daniel Foty |
A CAD methodology for optimizing transistor current and sizing in analog CMOS design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(2), pp. 225-237, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif |
Optimal decoupling capacitor sizing and placement for standard-cell layout designs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 22(4), pp. 428-436, 2003. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Franz Rothlauf |
Population Sizing for the Redundant Trivial Voting Mapping. ![Search on Bibsonomy](Pics/bibsonomy.png) |
GECCO ![In: Genetic and Evolutionary Computation - GECCO 2003, Genetic and Evolutionary Computation Conference, Chicago, IL, USA, July 12-16, 2003. Proceedings, Part II, pp. 1307-1319, 2003, Springer, 3-540-40603-4. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Miquel Albiol, José Luis González 0001, Eduard Alarcón |
Improved current-source sizing for high-speed high-accuracy current steering D/A converters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 2003 International Symposium on Circuits and Systems, ISCAS 2003, Bangkok, Thailand, May 25-28, 2003, pp. 837-840, 2003, IEEE, 0-7803-7761-3. The full citation details ...](Pics/full.jpeg) |
2003 |
DBLP DOI BibTeX RDF |
|
19 | Vikram Iyengar, Krishnendu Chakrabarty |
Test Bus Sizing for System-on-a-Chip. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Computers ![In: IEEE Trans. Computers 51(5), pp. 449-459, 2002. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
Core-based systems, integer linear programming, linearization, test access mechanism (TAM), testing time, embedded core testing, test bus |
19 | Wentao Shen, Michael Devetsikiotis |
A Self-Sizing Framework for Adaptive Resource Allocation in Label-Switched Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
MASCOTS ![In: 10th International Workshop on Modeling, Analysis, and Simulation of Computer and Telecommunication Systems (MASCOTS 2002), 11-16 October 2002, Fort Worth, Texas, USA, pp. 491-500, 2002, IEEE Computer Society, 0-7695-1840-0. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Elisa Ficarra, Luca Benini, Bruno Riccò, Giampaolo Zuccheri |
Automated DNA sizing in atomic force microscope images. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISBI ![In: Proceedings of the 2002 IEEE International Symposium on Biomedical Imaging, Ritz-Carlton Hotel, Washington, DC, USA, 7-10 June 2002, pp. 453-456, 2002, IEEE, 0-7803-7584-X. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Robert Schwencker, Frank Schenkel, Michael Pronath, Helmut E. Graeb |
Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2002 Design, Automation and Test in Europe Conference and Exposition (DATE 2002), 4-8 March 2002, Paris, France, pp. 581-585, 2002, IEEE Computer Society, 0-7695-1471-5. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif |
An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISPD ![In: Proceedings of 2002 International Symposium on Physical Design, ISPD 2002, Del Mar, CA, USA, April 7-10, 2002, pp. 68-73, 2002, ACM, 1-58113-460-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
adjoint sensitivity, optimization, placement, ASICs, decoupling capacitor, power grid noise |
19 | Mahesh Ketkar, Sachin S. Sapatnekar |
Standby power optimization via transistor sizing and dual threshold voltage assignment. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 2002 IEEE/ACM International Conference on Computer-aided Design, ICCAD 2002, San Jose, California, USA, November 10-14, 2002, pp. 375-378, 2002, ACM / IEEE Computer Society, 0-7803-7607-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Wu-chun Feng, Mike Fisk, Mark K. Gardner, Eric Weigle |
Dynamic Right-Sizing: An Automated, Lightweight, and Scalable Technique for Enhancing Grid Performance. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Protocols for High-Speed Networks ![In: Protocols for High Speed Networks, 7th IFIP/IEEE International Workshop, PfHSN 2002, Berlin, Germany, April 22-24, 2002, Proceedings, pp. 69-83, 2002, Springer, 3-540-43658-8. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Mark K. Gardner, Wu-chun Feng, Mike Fisk |
Dynamic Right-Sizing in FTP (drsFTP): Enhancing Grid Performance in User-Space. ![Search on Bibsonomy](Pics/bibsonomy.png) |
HPDC ![In: 11th IEEE International Symposium on High Performance Distributed Computing (HPDC-11 2002), 23-26 July 2002, Edinburgh, Scotland, UK, pp. 42-49, 2002, IEEE Computer Society, 0-7695-1686-6. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky |
Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC/VLSI Design ![In: Proceedings of the 7th Asia and South Pacific Design Automation Conference (ASP-DAC 2002), and the 15th International Conference on VLSI Design (VLSI Design 2002), Bangalore, India, January 7-11, 2002, pp. 580-, 2002, IEEE Computer Society, 0-7695-1299-2. The full citation details ...](Pics/full.jpeg) |
2002 |
DBLP DOI BibTeX RDF |
|
19 | Tamra Carpenter, Martin I. Eiger, David Shallcross, Paul D. Seymour |
Node Placement and Sizing for Copper Broadband Access Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
Ann. Oper. Res. ![In: Ann. Oper. Res. 106(1-4), pp. 199-228, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | P. Pant, R. K. Roy, A. Chatterjee |
Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 9(2), pp. 390-394, 2001. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Masanori Hashimoto, Hidetoshi Onodera |
Post-layout transistor sizing for power reduction in cell-based design. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ASP-DAC ![In: Proceedings of ASP-DAC 2001, Asia and South Pacific Design Automation Conference 2001, January 30-February 2, 2001, Yokohama, Japan, pp. 359-365, 2001, ACM, 0-7803-6634-4. The full citation details ...](Pics/full.jpeg) |
2001 |
DBLP DOI BibTeX RDF |
|
19 | Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou |
Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 19(9), pp. 999-1010, 2000. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Youxin Gao, D. F. Wong 0001 |
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2000 Design, Automation and Test in Europe (DATE 2000), 27-30 March 2000, Paris, France, pp. 512-516, 2000, IEEE Computer Society / ACM, 0-7695-0537-6. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Michael J. Engiles, Edward R. Stephan |
Large-scale applications: system sizing using modeling and simulation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the 32nd conference on Winter simulation, WSC 2000, Wyndham Palace Resort & Spa, Orlando, FL, USA, December 10-13, 2000, pp. 1222-1226, 2000, WSC, 0-7803-6582-8. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Pinghong Chen, Ernest S. Kuh |
Floorplan sizing by linear programming approximation. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 37th Conference on Design Automation, Los Angeles, CA, USA, June 5-9, 2000., pp. 468-471, 2000, ACM. The full citation details ...](Pics/full.jpeg) |
2000 |
DBLP DOI BibTeX RDF |
|
19 | Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone |
Power reduction through iterative gate sizing and voltage scaling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISCAS (1) ![In: Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30 - June 2, 1999, pp. 246-249, 1999, IEEE, 0-7803-5471-0. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Mircea R. Stan |
Optimal Voltages and Sizing for Low Power. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: 12th International Conference on VLSI Design (VLSI Design 1999), 10-13 January 1999, Goa, India, pp. 428-433, 1999, IEEE Computer Society, 0-7695-0013-7. The full citation details ...](Pics/full.jpeg) |
1999 |
DBLP DOI BibTeX RDF |
|
19 | Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau |
Data Cache Sizing for Embedded Processor Applications. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 1998 Design, Automation and Test in Europe (DATE '98), February 23-26, 1998, Le Palais des Congrès de Paris, Paris, France, pp. 925-926, 1998, IEEE Computer Society, 0-8186-8359-7. The full citation details ...](Pics/full.jpeg) |
1998 |
DBLP DOI BibTeX RDF |
|
19 | Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi |
Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 16(2), pp. 210-215, 1997. The full citation details ...](Pics/full.jpeg) |
1997 |
DBLP DOI BibTeX RDF |
|
19 | John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin |
Optimal wire sizing and buffer insertion for low power and a generalized delay model. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1995 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1995, San Jose, California, USA, November 5-9, 1995, pp. 138-143, 1995, IEEE Computer Society / ACM, 0-8186-7213-7. The full citation details ...](Pics/full.jpeg) |
1995 |
DBLP DOI BibTeX RDF |
Timing Optization, Dynamic Power Dissipation, Signal Slew, Dynamic Programming, Elmore Delay |
19 | Fernando Medeiro, Francisco V. Fernández 0001, Rafael Domínguez-Castro, Ángel Rodríguez-Vázquez |
A statistical optimization-based approach for automated sizing of analog cells. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 594-597, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | How-Rern Lin, TingTing Hwang |
Dynamical identification of critical paths for iterative gate sizing. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, ICCAD 1994, San Jose, California, USA, November 6-10, 1994, pp. 481-484, 1994, IEEE Computer Society / ACM, 0-89791-690-5. The full citation details ...](Pics/full.jpeg) |
1994 |
DBLP DOI BibTeX RDF |
|
19 | Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang |
An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 12(11), pp. 1621-1634, 1993. The full citation details ...](Pics/full.jpeg) |
1993 |
DBLP DOI BibTeX RDF |
|
19 | Pramod V. Argade |
Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 8(1), pp. 33-40, 1989. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
19 | Rajiv Dutta, Malgorzata Marek-Sadowska |
Automatic Sizing of Power/Ground (P/G) Networks in VLSI. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 26th ACM/IEEE Design Automation Conference, Las Vegas, Nevada, USA, June 25-29, 1989., pp. 783-786, 1989, ACM Press. The full citation details ...](Pics/full.jpeg) |
1989 |
DBLP DOI BibTeX RDF |
|
19 | Mehmet A. Cirit |
Transistor Sizing in CMOS Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 24th ACM/IEEE Design Automation Conference. Miami Beach, FL, USA, June 28 - July 1, 1987., pp. 121-124, 1987, IEEE Computer Society Press / ACM. The full citation details ...](Pics/full.jpeg) |
1987 |
DBLP DOI BibTeX RDF |
|
19 | Sant R. Arora, A. Gallo |
Optimization of Static Loading and Sizing of Multilevel Memory Systems. ![Search on Bibsonomy](Pics/bibsonomy.png) |
J. ACM ![In: J. ACM 20(2), pp. 307-319, 1973. The full citation details ...](Pics/full.jpeg) |
1973 |
DBLP DOI BibTeX RDF |
|
15 | Zhanshan (Sam) Ma |
Towards a Population Dynamics Theory for Evolutionary Computing: Learning from Biological Population Dynamics in Nature. ![Search on Bibsonomy](Pics/bibsonomy.png) |
AICI ![In: Artificial Intelligence and Computational Intelligence, International Conference, AICI 2009, Shanghai, China, November 7-8, 2009. Proceedings, pp. 195-205, 2009, Springer, 978-3-642-05252-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
Logistic Chaos Map, Insect Populations, Survival Selection, Genetic Algorithms, Evolutionary Computing, Power Law, Fitness Landscape, Survival Analysis, Population Dynamics, Spatial Distributions |
15 | Wei Sun |
Deciding model of Population Size in time-constrained task scheduling. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IPDPS ![In: 23rd IEEE International Symposium on Parallel and Distributed Processing, IPDPS 2009, Rome, Italy, May 23-29, 2009, pp. 1-8, 2009, IEEE. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Paul Bogdan, Radu Marculescu |
Statistical physics approaches for network-on-chip traffic characterization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
CODES+ISSS ![In: Proceedings of the 7th International Conference on Hardware/Software Codesign and System Synthesis, CODES+ISSS 2009, Grenoble, France, October 11-16, 2009, pp. 461-470, 2009, ACM, 978-1-60558-628-1. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
fractional calculus, systems-on-chip, networks-on-chip, multi-processor systems, master equation |
15 | Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay |
Slew-aware clock tree design for reliable subthreshold circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2009 International Symposium on Low Power Electronics and Design, 2009, San Fancisco, CA, USA, August 19-21, 2009, pp. 15-20, 2009, ACM, 978-1-60558-684-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
slew, clocks, subthreshold |
15 | Almitra Pradhan, Ranga Vemuri |
Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
VLSI Design ![In: VLSI Design 2009: Improving Productivity through Higher Abstraction, The 22nd International Conference on VLSI Design, New Delhi, India, 5-9 January 2009, pp. 131-136, 2009, IEEE Computer Society, 978-0-7695-3506-7. The full citation details ...](Pics/full.jpeg) |
2009 |
DBLP DOI BibTeX RDF |
|
15 | Yu Wang 0002, Ku He, Rong Luo, Hui Wang 0004, Huazhong Yang |
Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Very Large Scale Integr. Syst. ![In: IEEE Trans. Very Large Scale Integr. Syst. 16(9), pp. 1101-1113, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Shrirang K. Karandikar, Sachin S. Sapatnekar |
Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 27(1), pp. 45-58, 2008. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Priscila Solís Barreto, Paulo Henrique Portela de Carvalho |
Network Planning Optimization for Multimedia Networks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
NCA ![In: Proceedings of The Seventh IEEE International Symposium on Networking Computing and Applications, NCA 2008, July 10-12, 2008, Cambridge, Massachusetts, USA, pp. 60-67, 2008, IEEE Computer Society, 978-0-7695-3192-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
optimization, multimedia traffic, network planning |
15 | Amitay Isaacs, Tapabrata Ray, Warren F. Smith |
An Efficient Hybrid Algorithm for Optimization of Discrete Structures. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SEAL ![In: Simulated Evolution and Learning, 7th International Conference, SEAL 2008, Melbourne, Australia, December 7-10, 2008. Proceedings, pp. 625-634, 2008, Springer, 978-3-540-89693-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino |
Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating. ![Search on Bibsonomy](Pics/bibsonomy.png) |
PATMOS ![In: Integrated Circuit and System Design. Power and Timing Modeling, Optimization and Simulation, 18th International Workshop, PATMOS 2008, Lisbon, Portugal, September 10-12, 2008. Revised Selected Papers, pp. 42-51, 2008, Springer, 978-3-540-95947-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Ian Kuon, Jonathan Rose |
Area and delay trade-offs in the circuit and architecture design of FPGAs. ![Search on Bibsonomy](Pics/bibsonomy.png) |
FPGA ![In: Proceedings of the ACM/SIGDA 16th International Symposium on Field Programmable Gate Arrays, FPGA 2008, Monterey, California, USA, February 24-26, 2008, pp. 149-158, 2008, ACM, 978-1-59593-934-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
optimization, FPGA, architecture |
15 | Zhanshan (Sam) Ma, Axel W. Krings |
Dynamic populations in genetic algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SAC ![In: Proceedings of the 2008 ACM Symposium on Applied Computing (SAC), Fortaleza, Ceara, Brazil, March 16-20, 2008, pp. 1807-1811, 2008, ACM, 978-1-59593-753-7. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
dynamic population, ecological computation, fluctuating population, genetic algorithms, evolutionary computation |
15 | Etienne von Lavante, J. Alison Noble |
Segmentation of breast cancer masses in ultrasound using radio-frequency signal derived parameters and strain estimates. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISBI ![In: Proceedings of the 2008 IEEE International Symposium on Biomedical Imaging: From Nano to Macro, Paris, France, May 14-17, 2008, pp. 536-539, 2008, IEEE, 978-1-4244-2003-2. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Laura E. Grit, Jeffrey S. Chase |
Weighted fair sharing for dynamic virtual clusters. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SIGMETRICS ![In: Proceedings of the 2008 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, SIGMETRICS 2008, Annapolis, MD, USA, June 2-6, 2008, pp. 461-462, 2008, ACM, 978-1-60558-005-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
cluster computing, weighted fair queuing, virtual computing, fair sharing, proportional sharing |
15 | Ranko Sredojevic, Vladimir Stojanovic |
Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2008 International Conference on Computer-Aided Design, ICCAD 2008, San Jose, CA, USA, November 10-13, 2008, pp. 314-321, 2008, IEEE Computer Society, 978-1-4244-2820-5. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
|
15 | Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny |
Timing optimization in logic with interconnect. ![Search on Bibsonomy](Pics/bibsonomy.png) |
SLIP ![In: The Tenth International Workshop on System-Level Interconnect Prediction (SLIP 2008), Newcastle, UK, April 5-8, 2008, Proceedings, pp. 19-26, 2008, ACM, 978-1-59593-918-0. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
interconnect, logic circuits, timing optimization, repeaters, logical effort |
15 | Angan Das, Ranga Vemuri |
Topology synthesis of analog circuits based on adaptively generated building blocks. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 45th Design Automation Conference, DAC 2008, Anaheim, CA, USA, June 8-13, 2008, pp. 44-49, 2008, ACM, 978-1-60558-115-6. The full citation details ...](Pics/full.jpeg) |
2008 |
DBLP DOI BibTeX RDF |
genetic algorithm, automated design, topology generation |
15 | Chao-Yang Yeh, Malgorzata Marek-Sadowska |
Timing-Aware Power-Noise Reduction in Placement. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(3), pp. 527-541, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Chin Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi |
Path-Based Buffer Insertion. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(7), pp. 1346-1355, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Guido Stehr, Helmut E. Graeb, Kurt Antreich |
Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 26(10), pp. 1733-1748, 2007. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Daniel Mueller 0001, Helmut E. Graeb, Ulf Schlichtmann |
Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DATE ![In: 2007 Design, Automation and Test in Europe Conference and Exposition, DATE 2007, Nice, France, April 16-20, 2007, pp. 75-80, 2007, EDA Consortium, San Jose, CA, USA, 978-3-9810801-2-4. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman |
Robust Energy-Efficient Adder Topologies. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Symposium on Computer Arithmetic ![In: 18th IEEE Symposium on Computer Arithmetic (ARITH-18 2007), 25-27 June 2007, Montpellier, France, pp. 16-28, 2007, IEEE Computer Society, 0-7695-2854-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Marcelo K. Fugihara, Alain de Norman et d'Audenhove, Neuton T. Karassawa |
Randomless as a critical point: simulation fitting better planning of distribution centers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
WSC ![In: Proceedings of the Winter Simulation Conference, WSC 2007, Washington, DC, USA, December 9-12, 2007, pp. 2371, 2007, WSC, 1-4244-1306-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang |
Analysis and optimization of power-gated ICs with multiple power gating configurations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICCAD ![In: 2007 International Conference on Computer-Aided Design, ICCAD 2007, San Jose, CA, USA, November 5-8, 2007, pp. 783-790, 2007, IEEE Computer Society, 1-4244-1382-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Y. Pardhasaradhi, Safdar Ahmed |
Efficiency of electronic public service delivery in India: public-private partnership as a critical factor. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ICEGOV ![In: Proceedings of the 1st International Conference on Theory and Practice of Electronic Governance, ICEGOV 2007, Macao, China, December 10-13, 2007, pp. 357-365, 2007, ACM, 978-1-59593-822-0. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
Bhoomi, e-Seva, e-governance practices, public private collaboration, efficiency |
15 | Michael Affenzeller, Stefan Wagner 0002, Stephan M. Winkler |
Self-adaptive Population Size Adjustment for Genetic Algorithms. ![Search on Bibsonomy](Pics/bibsonomy.png) |
EUROCAST ![In: Computer Aided Systems Theory - EUROCAST 2007, 11th International Conference on Computer Aided Systems Theory, Las Palmas de Gran Canaria, Spain, February 12-16, 2007, Revised Selected Papers, pp. 820-828, 2007, Springer, 978-3-540-75866-2. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Rajani Kuchipudi, Hamid Mahmoodi |
Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 8th International Symposium on Quality of Electronic Design (ISQED 2007), 26-28 March 2007, San Jose, CA, USA, pp. 27-32, 2007, IEEE Computer Society, 978-0-7695-2795-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Xiaoji Ye, Yaping Zhan, Peng Li 0001 |
Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 853-858, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Rebecca L. Collins, Luca P. Carloni |
Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 410-415, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Kiran Puttaswamy, Gabriel H. Loh |
Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 622-625, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Minsik Cho, Hua Xiang 0001, Ruchir Puri, David Z. Pan |
TROY: Track Router with Yield-driven Wire Planning. ![Search on Bibsonomy](Pics/bibsonomy.png) |
DAC ![In: Proceedings of the 44th Design Automation Conference, DAC 2007, San Diego, CA, USA, June 4-8, 2007, pp. 55-58, 2007, IEEE. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Neda Beheshti, Jad Naous, Yashar Ganjali, Nick McKeown |
Experimenting with buffer sizes in routers. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ANCS ![In: Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, ANCS 2007, Orlando, Florida, USA, December 3-4, 2007, pp. 41-42, 2007, ACM, 978-1-59593-945-6. The full citation details ...](Pics/full.jpeg) |
2007 |
DBLP DOI BibTeX RDF |
|
15 | Debjit Sinha, Hai Zhou 0001 |
Gate-size optimization under timing constraints for coupling-noise reduction. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. ![In: IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(6), pp. 1064-1074, 2006. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Hang Si |
On Refinement of Constrained Delaunay Tetrahedralizations. ![Search on Bibsonomy](Pics/bibsonomy.png) |
IMR ![In: Proceedings of the 15th International Meshing Roundtable, Birmingham, Alabama, USA, September 17-20, 2006, Proceedings, pp. 509-528, 2006, Springer, 978-3-540-34957-0. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Yu Wang 0002, Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang 0004 |
Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISLPED ![In: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, Tegernsee, Bavaria, Germany, October 4-6, 2006, pp. 238-243, 2006, ACM, 1-59593-462-6. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
leakage current reduction, two-phase fine-grain sleep transistor insertion, mixed integer linear programming |
15 | Vivek Joshi, Rajeev R. Rao, David T. Blaauw, Dennis Sylvester |
Logic SER Reduction through Flipflop Redesign. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 611-616, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|
15 | Andrew Havlir, David Z. Pan |
Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines. ![Search on Bibsonomy](Pics/bibsonomy.png) |
ISQED ![In: 7th International Symposium on Quality of Electronic Design (ISQED 2006), 27-29 March 2006, San Jose, CA, USA, pp. 171-178, 2006, IEEE Computer Society, 0-7695-2523-7. The full citation details ...](Pics/full.jpeg) |
2006 |
DBLP DOI BibTeX RDF |
|