Search results for "sizing"

Hits ?▲	Authors	Title	Venue	Year	Link	Author keywords
19	Sean X. Shi, David Z. Pan	Wire sizing with scattering effect for nanoscale interconnection.	ASP-DAC	2006	DBLP DOI BibTeX RDF
19	Srikant Nalatwad, Michael Devetsikiotis	A Framework for Adaptive Wavelet Prediction in Self-Sizing Networks.	Annual Simulation Symposium	2006	DBLP DOI BibTeX RDF
19	Tom Van Court, Martin C. Herbordt	Sizing of Processing Arrays for FPGA-Based Computation.	FPL	2006	DBLP DOI BibTeX RDF
19	Martijn Coenen, Srinivasan Murali, Andrei Radulescu, Kees Goossens, Giovanni De Micheli	A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control.	CODES+ISSS	2006	DBLP DOI BibTeX RDF	systems-on-chip, networks-on-chip, buffers, area
19	Eric Wong 0002, Jacob R. Minz, Sung Kyu Lim	Decoupling capacitor planning and sizing for noise and leakage reduction.	ICCAD	2006	DBLP DOI BibTeX RDF	3D floorplanning, power supply noise, decoupling capacitors, leakage power reduction
19	Mihir R. Choudhury, Quming Zhou, Kartik Mohanram	Design optimization for single-event upset robustness using simultaneous dual-VDD and sizing techniques.	ICCAD	2006	DBLP DOI BibTeX RDF
19	Timothy G. Constandinou, Chris Toumazou	A micropower vision processor for parallel object positioning and sizing.	ISCAS	2006	DBLP DOI BibTeX RDF
19	Jafar Rezaei 0001, Mansoor Davoodi	Genetic Algorithm for Inventory Lot-Sizing with Supplier Selection Under Fuzzy Demand and Costs.	IEA/AIE	2006	DBLP DOI BibTeX RDF
19	Sampath Dechu, Zion Cien Shen, Chris C. N. Chu	An efficient routing tree construction algorithm with buffer insertion, wire sizing, and obstacle considerations.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
19	Kai Wang 0011, Yajun Ran, Hailin Jiang, Malgorzata Marek-Sadowska	General skew constrained clock network sizing based on sequential linear programming.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2005	DBLP DOI BibTeX RDF
19	João Pedro Pedroso, Mikio Kubo	Hybrid Tabu Search for Lot Sizing Problems.	Hybrid Metaheuristics	2005	DBLP DOI BibTeX RDF
19	Sankalp Kallakuri, Alex Doboli, Eugene A. Feinberg	Buffer Insertion for Bridges and Optimal Buffer Sizing for Communication Sub-System of Systems-on-Chip.	DATE	2005	DBLP DOI BibTeX RDF
19	Aseem Agarwal, Kaviraj Chopra, David T. Blaauw	Statistical Timing Based Optimization using Gate Sizing.	DATE	2005	DBLP DOI BibTeX RDF
19	Anand Ramalingam, Bin Zhang 0011, Anirudh Devgan, David Z. Pan	Sleep transistor sizing using timing criticality and temporal currents.	ASP-DAC	2005	DBLP DOI BibTeX RDF
19	Jerzy Duda	Lot-Sizing in a Foundry Using Genetic Algorithm and Repair Functions.	EvoCOP	2005	DBLP DOI BibTeX RDF
19	Zhikui Wang, Xiaoyun Zhu, Sharad Singhal	Utilization and SLO-Based Control for Dynamic Sizing of Resource Partitions.	DSOM	2005	DBLP DOI BibTeX RDF
19	Shrirang K. Karandikar, Sachin S. Sapatnekar	Fast estimation of area-delay trade-offs in circuit sizing.	ISCAS (4)	2005	DBLP DOI BibTeX RDF
19	José Manuel Cazeaux, Daniele Rossi 0001, Martin Omaña 0001, Cecilia Metra, Abhijit Chatterjee	On Transistor Level Gate Sizing for Increased Robustness to Transient Faults.	IOLTS	2005	DBLP DOI BibTeX RDF
19	Weizhen Yan, Jianhua Zhao, Zhe Cao	Fuzzy Programming Model for Lot Sizing Production Planning Problem.	FSKD (1)	2005	DBLP DOI BibTeX RDF
19	Vinita V. Deodhar, Jeffrey A. Davis	Voltage Scaling, Wire Sizing and Repeater Insertion Design Rules for Wave-Pipelined VLSI Global Interconnect Circuits.	ISQED	2005	DBLP DOI BibTeX RDF
19	Mathieu Van Vyve	A solution approach of production planning problems based on compact formulations for single-item lot-sizing models.	4OR	2004	DBLP DOI BibTeX RDF
19	Chris C. N. Chu, Evangeline F. Y. Young	Nonrectangular shaping and sizing of soft modules for floorplan-design improvement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2004	DBLP DOI BibTeX RDF
19	Ashish Srivastava, Dennis Sylvester, David T. Blaauw	Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design.	DATE	2004	DBLP DOI BibTeX RDF
19	Sampath Dechu, Zion Cien Shen, Chris C. N. Chu	An efficient routing tree construction algorithm with buffer insertion, wire sizing and obstacle considerations.	ASP-DAC	2004	DBLP DOI BibTeX RDF
19	Ivanoe De Falco, Ernesto Tarantino, Antonio Della Cioppa, Francesco Gagliardi 0001	A Genetic Algorithm with Self-sizing Genomes for Data Clustering in Dermatological Semeiotics.	WSC	2004	DBLP DOI BibTeX RDF
19	Feng Chu 0001, Chengbin Chu, Xiao Liu	Lot sizing models with backlog or out-sourcing.	SMC (5)	2004	DBLP DOI BibTeX RDF
19	Ludmila Cherkasova, Wenting Tang	Sizing the streaming media cluster solution for a given workload.	CCGRID	2004	DBLP DOI BibTeX RDF
19	Nithya N. Vijayakumar, Beth Plale	Performance Evaluation of Rate-Based Join Window Sizing for Asynchronous Data Streams.	HPDC	2004	DBLP DOI BibTeX RDF
19	Seung Hoon Choi, Bipul Chandra Paul, Kaushik Roy 0001	Novel sizing algorithm for yield improvement under process variation in nanometer technology.	DAC	2004	DBLP DOI BibTeX RDF	Performance, Design, Algorithms, Reliability
19	Ashish Srivastava, Dennis Sylvester, David T. Blaauw	Power minimization using simultaneous gate sizing, dual-Vdd and dual-Vth assignment.	DAC	2004	DBLP DOI BibTeX RDF	optimization, power dissipation, multiple voltages
19	Sheldon X.-D. Tan, C.-J. Richard Shi	Efficient very large scale integration power/ground network sizing based on equivalent circuit modeling.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
19	David M. Binkley, C. E. Hopper, Steve D. Tucker, Brian C. Moss, James M. Rochelle, Daniel Foty	A CAD methodology for optimizing transistor current and sizing in analog CMOS design.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
19	Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif	Optimal decoupling capacitor sizing and placement for standard-cell layout designs.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2003	DBLP DOI BibTeX RDF
19	Franz Rothlauf	Population Sizing for the Redundant Trivial Voting Mapping.	GECCO	2003	DBLP DOI BibTeX RDF
19	Miquel Albiol, José Luis González 0001, Eduard Alarcón	Improved current-source sizing for high-speed high-accuracy current steering D/A converters.	ISCAS (1)	2003	DBLP DOI BibTeX RDF
19	Vikram Iyengar, Krishnendu Chakrabarty	Test Bus Sizing for System-on-a-Chip.	IEEE Trans. Computers	2002	DBLP DOI BibTeX RDF	Core-based systems, integer linear programming, linearization, test access mechanism (TAM), testing time, embedded core testing, test bus
19	Wentao Shen, Michael Devetsikiotis	A Self-Sizing Framework for Adaptive Resource Allocation in Label-Switched Networks.	MASCOTS	2002	DBLP DOI BibTeX RDF
19	Elisa Ficarra, Luca Benini, Bruno Riccò, Giampaolo Zuccheri	Automated DNA sizing in atomic force microscope images.	ISBI	2002	DBLP DOI BibTeX RDF
19	Robert Schwencker, Frank Schenkel, Michael Pronath, Helmut E. Graeb	Analog Circuit Sizing Using Adaptive Worst-Case Parameter Sets.	DATE	2002	DBLP DOI BibTeX RDF
19	Haihua Su, Sachin S. Sapatnekar, Sani R. Nassif	An algorithm for optimal decoupling capacitor sizing and placement for standard cell layouts.	ISPD	2002	DBLP DOI BibTeX RDF	adjoint sensitivity, optimization, placement, ASICs, decoupling capacitor, power grid noise
19	Mahesh Ketkar, Sachin S. Sapatnekar	Standby power optimization via transistor sizing and dual threshold voltage assignment.	ICCAD	2002	DBLP DOI BibTeX RDF
19	Wu-chun Feng, Mike Fisk, Mark K. Gardner, Eric Weigle	Dynamic Right-Sizing: An Automated, Lightweight, and Scalable Technique for Enhancing Grid Performance.	Protocols for High-Speed Networks	2002	DBLP DOI BibTeX RDF
19	Mark K. Gardner, Wu-chun Feng, Mike Fisk	Dynamic Right-Sizing in FTP (drsFTP): Enhancing Grid Performance in User-Space.	HPDC	2002	DBLP DOI BibTeX RDF
19	Christoph Albrecht, Andrew B. Kahng, Ion I. Mandoiu, Alexander Zelikovsky	Floorplan Evaluation with Timing-Driven Global Wireplanning, Pin Assignment and Buffer/Wire Sizing.	ASP-DAC/VLSI Design	2002	DBLP DOI BibTeX RDF
19	Tamra Carpenter, Martin I. Eiger, David Shallcross, Paul D. Seymour	Node Placement and Sizing for Copper Broadband Access Networks.	Ann. Oper. Res.	2001	DBLP DOI BibTeX RDF
19	P. Pant, R. K. Roy, A. Chatterjee	Dual-threshold voltage assignment with transistor sizing for low power CMOS circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2001	DBLP DOI BibTeX RDF
19	Masanori Hashimoto, Hidetoshi Onodera	Post-layout transistor sizing for power reduction in cell-based design.	ASP-DAC	2001	DBLP DOI BibTeX RDF
19	Iris Hui-Ru Jiang, Yao-Wen Chang, Jing-Yang Jou	Crosstalk-driven interconnect optimization by simultaneous gate andwire sizing.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2000	DBLP DOI BibTeX RDF
19	Youxin Gao, D. F. Wong 0001	Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model.	DATE	2000	DBLP DOI BibTeX RDF
19	Michael J. Engiles, Edward R. Stephan	Large-scale applications: system sizing using modeling and simulation.	WSC	2000	DBLP DOI BibTeX RDF
19	Pinghong Chen, Ernest S. Kuh	Floorplan sizing by linear programming approximation.	DAC	2000	DBLP DOI BibTeX RDF
19	Chingwei Yeh, Min-Cheng Chang, Shih-Chieh Chang, Wen-Ben Jone	Power reduction through iterative gate sizing and voltage scaling.	ISCAS (1)	1999	DBLP DOI BibTeX RDF
19	Mircea R. Stan	Optimal Voltages and Sizing for Low Power.	VLSI Design	1999	DBLP DOI BibTeX RDF
19	Preeti Ranjan Panda, Nikil D. Dutt, Alexandru Nicolau	Data Cache Sizing for Embedded Processor Applications.	DATE	1998	DBLP DOI BibTeX RDF
19	Satyamurthy Pullela, Noel Menezes, Lawrence T. Pileggi	Moment-sensitivity-based wire sizing for skew reduction in on-chip clock nets.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1997	DBLP DOI BibTeX RDF
19	John Lillis, Chung-Kuan Cheng, Ting-Ting Y. Lin	Optimal wire sizing and buffer insertion for low power and a generalized delay model.	ICCAD	1995	DBLP DOI BibTeX RDF	Timing Optization, Dynamic Power Dissipation, Signal Slew, Dynamic Programming, Elmore Delay
19	Fernando Medeiro, Francisco V. Fernández 0001, Rafael Domínguez-Castro, Ángel Rodríguez-Vázquez	A statistical optimization-based approach for automated sizing of analog cells.	ICCAD	1994	DBLP DOI BibTeX RDF
19	How-Rern Lin, TingTing Hwang	Dynamical identification of critical paths for iterative gate sizing.	ICCAD	1994	DBLP DOI BibTeX RDF
19	Sachin S. Sapatnekar, Vasant B. Rao, Pravin M. Vaidya, Sung-Mo Kang	An exact solution to the transistor sizing problem for CMOS circuits using convex optimization.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1993	DBLP DOI BibTeX RDF
19	Pramod V. Argade	Sizing an inverter with a precise delay: generation of complementary signals with minimal skew and pulsewidth distortion in CMOS.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	1989	DBLP DOI BibTeX RDF
19	Rajiv Dutta, Malgorzata Marek-Sadowska	Automatic Sizing of Power/Ground (P/G) Networks in VLSI.	DAC	1989	DBLP DOI BibTeX RDF
19	Mehmet A. Cirit	Transistor Sizing in CMOS Circuits.	DAC	1987	DBLP DOI BibTeX RDF
19	Sant R. Arora, A. Gallo	Optimization of Static Loading and Sizing of Multilevel Memory Systems.	J. ACM	1973	DBLP DOI BibTeX RDF
15	Zhanshan (Sam) Ma	Towards a Population Dynamics Theory for Evolutionary Computing: Learning from Biological Population Dynamics in Nature.	AICI	2009	DBLP DOI BibTeX RDF	Logistic Chaos Map, Insect Populations, Survival Selection, Genetic Algorithms, Evolutionary Computing, Power Law, Fitness Landscape, Survival Analysis, Population Dynamics, Spatial Distributions
15	Wei Sun	Deciding model of Population Size in time-constrained task scheduling.	IPDPS	2009	DBLP DOI BibTeX RDF
15	Paul Bogdan, Radu Marculescu	Statistical physics approaches for network-on-chip traffic characterization.	CODES+ISSS	2009	DBLP DOI BibTeX RDF	fractional calculus, systems-on-chip, networks-on-chip, multi-processor systems, master equation
15	Jeremy R. Tolbert, Xin Zhao 0001, Sung Kyu Lim, Saibal Mukhopadhyay	Slew-aware clock tree design for reliable subthreshold circuits.	ISLPED	2009	DBLP DOI BibTeX RDF	slew, clocks, subthreshold
15	Almitra Pradhan, Ranga Vemuri	Efficient Synthesis of a Uniformly Spread Layout Aware Pareto Surface for Analog Circuits.	VLSI Design	2009	DBLP DOI BibTeX RDF
15	Yu Wang 0002, Ku He, Rong Luo, Hui Wang 0004, Huazhong Yang	Two-Phase Fine-Grain Sleep Transistor Insertion Technique in Leakage Critical Circuits.	IEEE Trans. Very Large Scale Integr. Syst.	2008	DBLP DOI BibTeX RDF
15	Shrirang K. Karandikar, Sachin S. Sapatnekar	Technology Mapping Using Logical Effort for Solving the Load-Distribution Problem.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2008	DBLP DOI BibTeX RDF
15	Priscila Solís Barreto, Paulo Henrique Portela de Carvalho	Network Planning Optimization for Multimedia Networks.	NCA	2008	DBLP DOI BibTeX RDF	optimization, multimedia traffic, network planning
15	Amitay Isaacs, Tapabrata Ray, Warren F. Smith	An Efficient Hybrid Algorithm for Optimization of Discrete Structures.	SEAL	2008	DBLP DOI BibTeX RDF
15	Ashoka Visweswara Sathanur, Luca Benini, Alberto Macii, Enrico Macii, Massimo Poncino	Temporal Discharge Current Driven Clustering for Improved Leakage Power Reduction in Row-Based Power-Gating.	PATMOS	2008	DBLP DOI BibTeX RDF
15	Ian Kuon, Jonathan Rose	Area and delay trade-offs in the circuit and architecture design of FPGAs.	FPGA	2008	DBLP DOI BibTeX RDF	optimization, FPGA, architecture
15	Zhanshan (Sam) Ma, Axel W. Krings	Dynamic populations in genetic algorithms.	SAC	2008	DBLP DOI BibTeX RDF	dynamic population, ecological computation, fluctuating population, genetic algorithms, evolutionary computation
15	Etienne von Lavante, J. Alison Noble	Segmentation of breast cancer masses in ultrasound using radio-frequency signal derived parameters and strain estimates.	ISBI	2008	DBLP DOI BibTeX RDF
15	Laura E. Grit, Jeffrey S. Chase	Weighted fair sharing for dynamic virtual clusters.	SIGMETRICS	2008	DBLP DOI BibTeX RDF	cluster computing, weighted fair queuing, virtual computing, fair sharing, proportional sharing
15	Ranko Sredojevic, Vladimir Stojanovic	Optimization-based framework for simultaneous circuit-and-system design-space exploration: a high-speed link example.	ICCAD	2008	DBLP DOI BibTeX RDF
15	Arkadiy Morgenshtein, Eby G. Friedman, Ran Ginosar, Avinoam Kolodny	Timing optimization in logic with interconnect.	SLIP	2008	DBLP DOI BibTeX RDF	interconnect, logic circuits, timing optimization, repeaters, logical effort
15	Angan Das, Ranga Vemuri	Topology synthesis of analog circuits based on adaptively generated building blocks.	DAC	2008	DBLP DOI BibTeX RDF	genetic algorithm, automated design, topology generation
15	Chao-Yang Yeh, Malgorzata Marek-Sadowska	Timing-Aware Power-Noise Reduction in Placement.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
15	Chin Ngai Sze, Charles J. Alpert, Jiang Hu, Weiping Shi	Path-Based Buffer Insertion.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
15	Guido Stehr, Helmut E. Graeb, Kurt Antreich	Analog Performance Space Exploration by Normal-Boundary Intersection and by Fourier-Motzkin Elimination.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2007	DBLP DOI BibTeX RDF
15	Daniel Mueller 0001, Helmut E. Graeb, Ulf Schlichtmann	Trade-off design of analog circuits using goal attainment and "Wave Front" sequential quadratic programming.	DATE	2007	DBLP DOI BibTeX RDF
15	Dinesh Patil, Omid Azizi, Mark Horowitz, Ron Ho, Rajesh Ananthraman	Robust Energy-Efficient Adder Topologies.	IEEE Symposium on Computer Arithmetic	2007	DBLP DOI BibTeX RDF
15	Marcelo K. Fugihara, Alain de Norman et d'Audenhove, Neuton T. Karassawa	Randomless as a critical point: simulation fitting better planning of distribution centers.	WSC	2007	DBLP DOI BibTeX RDF
15	Aida Todri, Malgorzata Marek-Sadowska, Shih-Chieh Chang	Analysis and optimization of power-gated ICs with multiple power gating configurations.	ICCAD	2007	DBLP DOI BibTeX RDF
15	Y. Pardhasaradhi, Safdar Ahmed	Efficiency of electronic public service delivery in India: public-private partnership as a critical factor.	ICEGOV	2007	DBLP DOI BibTeX RDF	Bhoomi, e-Seva, e-governance practices, public private collaboration, efficiency
15	Michael Affenzeller, Stefan Wagner 0002, Stephan M. Winkler	Self-adaptive Population Size Adjustment for Genetic Algorithms.	EUROCAST	2007	DBLP DOI BibTeX RDF
15	Rajani Kuchipudi, Hamid Mahmoodi	Strain Silicon Optimization for Memory and Logic in Nano-Scale CMOS.	ISQED	2007	DBLP DOI BibTeX RDF
15	Xiaoji Ye, Yaping Zhan, Peng Li 0001	Statistical Leakage Power Minimization Using Fast Equi-Slack Shell Based Optimization.	DAC	2007	DBLP DOI BibTeX RDF
15	Rebecca L. Collins, Luca P. Carloni	Topology-Based Optimization of Maximal Sustainable Throughput in a Latency-Insensitive System.	DAC	2007	DBLP DOI BibTeX RDF
15	Kiran Puttaswamy, Gabriel H. Loh	Scalability of 3D-Integrated Arithmetic Units in High-Performance Microprocessors.	DAC	2007	DBLP DOI BibTeX RDF
15	Minsik Cho, Hua Xiang 0001, Ruchir Puri, David Z. Pan	TROY: Track Router with Yield-driven Wire Planning.	DAC	2007	DBLP DOI BibTeX RDF
15	Neda Beheshti, Jad Naous, Yashar Ganjali, Nick McKeown	Experimenting with buffer sizes in routers.	ANCS	2007	DBLP DOI BibTeX RDF
15	Debjit Sinha, Hai Zhou 0001	Gate-size optimization under timing constraints for coupling-noise reduction.	IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.	2006	DBLP DOI BibTeX RDF
15	Hang Si	On Refinement of Constrained Delaunay Tetrahedralizations.	IMR	2006	DBLP DOI BibTeX RDF
15	Yu Wang 0002, Yongpan Liu, Rong Luo, Huazhong Yang, Hui Wang 0004	Two-phase fine-grain sleep transistor insertion technique in leakage critical circuits.	ISLPED	2006	DBLP DOI BibTeX RDF	leakage current reduction, two-phase fine-grain sleep transistor insertion, mixed integer linear programming
15	Vivek Joshi, Rajeev R. Rao, David T. Blaauw, Dennis Sylvester	Logic SER Reduction through Flipflop Redesign.	ISQED	2006	DBLP DOI BibTeX RDF
15	Andrew Havlir, David Z. Pan	Simultaneous Statistical Delay and Slew Optimization for Interconnect Pipelines.	ISQED	2006	DBLP DOI BibTeX RDF